1 /* 2 * Xilinx Zynq GPIO device driver 3 * 4 * Copyright (C) 2009 - 2014 Xilinx, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it under 7 * the terms of the GNU General Public License as published by the Free Software 8 * Foundation; either version 2 of the License, or (at your option) any later 9 * version. 10 */ 11 12 #include <linux/bitops.h> 13 #include <linux/clk.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/module.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/of.h> 22 23 #define DRIVER_NAME "zynq-gpio" 24 25 /* Maximum banks */ 26 #define ZYNQ_GPIO_MAX_BANK 4 27 #define ZYNQMP_GPIO_MAX_BANK 6 28 29 #define ZYNQ_GPIO_BANK0_NGPIO 32 30 #define ZYNQ_GPIO_BANK1_NGPIO 22 31 #define ZYNQ_GPIO_BANK2_NGPIO 32 32 #define ZYNQ_GPIO_BANK3_NGPIO 32 33 34 #define ZYNQMP_GPIO_BANK0_NGPIO 26 35 #define ZYNQMP_GPIO_BANK1_NGPIO 26 36 #define ZYNQMP_GPIO_BANK2_NGPIO 26 37 #define ZYNQMP_GPIO_BANK3_NGPIO 32 38 #define ZYNQMP_GPIO_BANK4_NGPIO 32 39 #define ZYNQMP_GPIO_BANK5_NGPIO 32 40 41 #define ZYNQ_GPIO_NR_GPIOS 118 42 #define ZYNQMP_GPIO_NR_GPIOS 174 43 44 #define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0 45 #define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \ 46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1) 47 #define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1) 48 #define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \ 49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1) 50 #define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1) 51 #define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \ 52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1) 53 #define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1) 54 #define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \ 55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1) 56 #define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1) 57 #define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \ 58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1) 59 #define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1) 60 #define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \ 61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1) 62 63 64 /* Register offsets for the GPIO device */ 65 /* LSW Mask & Data -WO */ 66 #define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK)) 67 /* MSW Mask & Data -WO */ 68 #define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK)) 69 /* Data Register-RW */ 70 #define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK)) 71 /* Direction mode reg-RW */ 72 #define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK)) 73 /* Output enable reg-RW */ 74 #define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK)) 75 /* Interrupt mask reg-RO */ 76 #define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK)) 77 /* Interrupt enable reg-WO */ 78 #define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK)) 79 /* Interrupt disable reg-WO */ 80 #define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK)) 81 /* Interrupt status reg-RO */ 82 #define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK)) 83 /* Interrupt type reg-RW */ 84 #define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK)) 85 /* Interrupt polarity reg-RW */ 86 #define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK)) 87 /* Interrupt on any, reg-RW */ 88 #define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK)) 89 90 /* Disable all interrupts mask */ 91 #define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF 92 93 /* Mid pin number of a bank */ 94 #define ZYNQ_GPIO_MID_PIN_NUM 16 95 96 /* GPIO upper 16 bit mask */ 97 #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000 98 99 /** 100 * struct zynq_gpio - gpio device private data structure 101 * @chip: instance of the gpio_chip 102 * @base_addr: base address of the GPIO device 103 * @clk: clock resource for this controller 104 * @irq: interrupt for the GPIO device 105 * @p_data: pointer to platform data 106 */ 107 struct zynq_gpio { 108 struct gpio_chip chip; 109 void __iomem *base_addr; 110 struct clk *clk; 111 int irq; 112 const struct zynq_platform_data *p_data; 113 }; 114 115 /** 116 * struct zynq_platform_data - zynq gpio platform data structure 117 * @label: string to store in gpio->label 118 * @ngpio: max number of gpio pins 119 * @max_bank: maximum number of gpio banks 120 * @bank_min: this array represents bank's min pin 121 * @bank_max: this array represents bank's max pin 122 */ 123 struct zynq_platform_data { 124 const char *label; 125 u16 ngpio; 126 int max_bank; 127 int bank_min[ZYNQMP_GPIO_MAX_BANK]; 128 int bank_max[ZYNQMP_GPIO_MAX_BANK]; 129 }; 130 131 static struct irq_chip zynq_gpio_level_irqchip; 132 static struct irq_chip zynq_gpio_edge_irqchip; 133 134 static struct zynq_gpio *to_zynq_gpio(struct gpio_chip *gc) 135 { 136 return container_of(gc, struct zynq_gpio, chip); 137 } 138 139 /** 140 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank 141 * for a given pin in the GPIO device 142 * @pin_num: gpio pin number within the device 143 * @bank_num: an output parameter used to return the bank number of the gpio 144 * pin 145 * @bank_pin_num: an output parameter used to return pin number within a bank 146 * for the given gpio pin 147 * 148 * Returns the bank number and pin offset within the bank. 149 */ 150 static inline void zynq_gpio_get_bank_pin(unsigned int pin_num, 151 unsigned int *bank_num, 152 unsigned int *bank_pin_num, 153 struct zynq_gpio *gpio) 154 { 155 int bank; 156 157 for (bank = 0; bank < gpio->p_data->max_bank; bank++) { 158 if ((pin_num >= gpio->p_data->bank_min[bank]) && 159 (pin_num <= gpio->p_data->bank_max[bank])) { 160 *bank_num = bank; 161 *bank_pin_num = pin_num - 162 gpio->p_data->bank_min[bank]; 163 return; 164 } 165 } 166 167 /* default */ 168 WARN(true, "invalid GPIO pin number: %u", pin_num); 169 *bank_num = 0; 170 *bank_pin_num = 0; 171 } 172 173 /** 174 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device 175 * @chip: gpio_chip instance to be worked on 176 * @pin: gpio pin number within the device 177 * 178 * This function reads the state of the specified pin of the GPIO device. 179 * 180 * Return: 0 if the pin is low, 1 if pin is high. 181 */ 182 static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin) 183 { 184 u32 data; 185 unsigned int bank_num, bank_pin_num; 186 struct zynq_gpio *gpio = to_zynq_gpio(chip); 187 188 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); 189 190 data = readl_relaxed(gpio->base_addr + 191 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); 192 193 return (data >> bank_pin_num) & 1; 194 } 195 196 /** 197 * zynq_gpio_set_value - Modify the state of the pin with specified value 198 * @chip: gpio_chip instance to be worked on 199 * @pin: gpio pin number within the device 200 * @state: value used to modify the state of the specified pin 201 * 202 * This function calculates the register offset (i.e to lower 16 bits or 203 * upper 16 bits) based on the given pin number and sets the state of a 204 * gpio pin to the specified value. The state is either 0 or non-zero. 205 */ 206 static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin, 207 int state) 208 { 209 unsigned int reg_offset, bank_num, bank_pin_num; 210 struct zynq_gpio *gpio = to_zynq_gpio(chip); 211 212 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); 213 214 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) { 215 /* only 16 data bits in bit maskable reg */ 216 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM; 217 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num); 218 } else { 219 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num); 220 } 221 222 /* 223 * get the 32 bit value to be written to the mask/data register where 224 * the upper 16 bits is the mask and lower 16 bits is the data 225 */ 226 state = !!state; 227 state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) & 228 ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK); 229 230 writel_relaxed(state, gpio->base_addr + reg_offset); 231 } 232 233 /** 234 * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input 235 * @chip: gpio_chip instance to be worked on 236 * @pin: gpio pin number within the device 237 * 238 * This function uses the read-modify-write sequence to set the direction of 239 * the gpio pin as input. 240 * 241 * Return: 0 always 242 */ 243 static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin) 244 { 245 u32 reg; 246 unsigned int bank_num, bank_pin_num; 247 struct zynq_gpio *gpio = to_zynq_gpio(chip); 248 249 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); 250 251 /* bank 0 pins 7 and 8 are special and cannot be used as inputs */ 252 if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8)) 253 return -EINVAL; 254 255 /* clear the bit in direction mode reg to set the pin as input */ 256 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 257 reg &= ~BIT(bank_pin_num); 258 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 259 260 return 0; 261 } 262 263 /** 264 * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output 265 * @chip: gpio_chip instance to be worked on 266 * @pin: gpio pin number within the device 267 * @state: value to be written to specified pin 268 * 269 * This function sets the direction of specified GPIO pin as output, configures 270 * the Output Enable register for the pin and uses zynq_gpio_set to set 271 * the state of the pin to the value specified. 272 * 273 * Return: 0 always 274 */ 275 static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, 276 int state) 277 { 278 u32 reg; 279 unsigned int bank_num, bank_pin_num; 280 struct zynq_gpio *gpio = to_zynq_gpio(chip); 281 282 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); 283 284 /* set the GPIO pin as output */ 285 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 286 reg |= BIT(bank_pin_num); 287 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 288 289 /* configure the output enable reg for the pin */ 290 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); 291 reg |= BIT(bank_pin_num); 292 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); 293 294 /* set the state of the pin */ 295 zynq_gpio_set_value(chip, pin, state); 296 return 0; 297 } 298 299 /** 300 * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin 301 * @irq_data: per irq and chip data passed down to chip functions 302 * 303 * This function calculates gpio pin number from irq number and sets the 304 * bit in the Interrupt Disable register of the corresponding bank to disable 305 * interrupts for that pin. 306 */ 307 static void zynq_gpio_irq_mask(struct irq_data *irq_data) 308 { 309 unsigned int device_pin_num, bank_num, bank_pin_num; 310 struct zynq_gpio *gpio = 311 to_zynq_gpio(irq_data_get_irq_chip_data(irq_data)); 312 313 device_pin_num = irq_data->hwirq; 314 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); 315 writel_relaxed(BIT(bank_pin_num), 316 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); 317 } 318 319 /** 320 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin 321 * @irq_data: irq data containing irq number of gpio pin for the interrupt 322 * to enable 323 * 324 * This function calculates the gpio pin number from irq number and sets the 325 * bit in the Interrupt Enable register of the corresponding bank to enable 326 * interrupts for that pin. 327 */ 328 static void zynq_gpio_irq_unmask(struct irq_data *irq_data) 329 { 330 unsigned int device_pin_num, bank_num, bank_pin_num; 331 struct zynq_gpio *gpio = 332 to_zynq_gpio(irq_data_get_irq_chip_data(irq_data)); 333 334 device_pin_num = irq_data->hwirq; 335 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); 336 writel_relaxed(BIT(bank_pin_num), 337 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num)); 338 } 339 340 /** 341 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin 342 * @irq_data: irq data containing irq number of gpio pin for the interrupt 343 * to ack 344 * 345 * This function calculates gpio pin number from irq number and sets the bit 346 * in the Interrupt Status Register of the corresponding bank, to ACK the irq. 347 */ 348 static void zynq_gpio_irq_ack(struct irq_data *irq_data) 349 { 350 unsigned int device_pin_num, bank_num, bank_pin_num; 351 struct zynq_gpio *gpio = 352 to_zynq_gpio(irq_data_get_irq_chip_data(irq_data)); 353 354 device_pin_num = irq_data->hwirq; 355 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); 356 writel_relaxed(BIT(bank_pin_num), 357 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num)); 358 } 359 360 /** 361 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin 362 * @irq_data: irq data containing irq number of gpio pin for the interrupt 363 * to enable 364 * 365 * Clears the INTSTS bit and unmasks the given interrupt. 366 */ 367 static void zynq_gpio_irq_enable(struct irq_data *irq_data) 368 { 369 /* 370 * The Zynq GPIO controller does not disable interrupt detection when 371 * the interrupt is masked and only disables the propagation of the 372 * interrupt. This means when the controller detects an interrupt 373 * condition while the interrupt is logically disabled it will propagate 374 * that interrupt event once the interrupt is enabled. This will cause 375 * the interrupt consumer to see spurious interrupts to prevent this 376 * first make sure that the interrupt is not asserted and then enable 377 * it. 378 */ 379 zynq_gpio_irq_ack(irq_data); 380 zynq_gpio_irq_unmask(irq_data); 381 } 382 383 /** 384 * zynq_gpio_set_irq_type - Set the irq type for a gpio pin 385 * @irq_data: irq data containing irq number of gpio pin 386 * @type: interrupt type that is to be set for the gpio pin 387 * 388 * This function gets the gpio pin number and its bank from the gpio pin number 389 * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers. 390 * 391 * Return: 0, negative error otherwise. 392 * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0; 393 * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0; 394 * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1; 395 * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA; 396 * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA 397 */ 398 static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type) 399 { 400 u32 int_type, int_pol, int_any; 401 unsigned int device_pin_num, bank_num, bank_pin_num; 402 struct zynq_gpio *gpio = 403 to_zynq_gpio(irq_data_get_irq_chip_data(irq_data)); 404 405 device_pin_num = irq_data->hwirq; 406 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); 407 408 int_type = readl_relaxed(gpio->base_addr + 409 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); 410 int_pol = readl_relaxed(gpio->base_addr + 411 ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); 412 int_any = readl_relaxed(gpio->base_addr + 413 ZYNQ_GPIO_INTANY_OFFSET(bank_num)); 414 415 /* 416 * based on the type requested, configure the INT_TYPE, INT_POLARITY 417 * and INT_ANY registers 418 */ 419 switch (type) { 420 case IRQ_TYPE_EDGE_RISING: 421 int_type |= BIT(bank_pin_num); 422 int_pol |= BIT(bank_pin_num); 423 int_any &= ~BIT(bank_pin_num); 424 break; 425 case IRQ_TYPE_EDGE_FALLING: 426 int_type |= BIT(bank_pin_num); 427 int_pol &= ~BIT(bank_pin_num); 428 int_any &= ~BIT(bank_pin_num); 429 break; 430 case IRQ_TYPE_EDGE_BOTH: 431 int_type |= BIT(bank_pin_num); 432 int_any |= BIT(bank_pin_num); 433 break; 434 case IRQ_TYPE_LEVEL_HIGH: 435 int_type &= ~BIT(bank_pin_num); 436 int_pol |= BIT(bank_pin_num); 437 break; 438 case IRQ_TYPE_LEVEL_LOW: 439 int_type &= ~BIT(bank_pin_num); 440 int_pol &= ~BIT(bank_pin_num); 441 break; 442 default: 443 return -EINVAL; 444 } 445 446 writel_relaxed(int_type, 447 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); 448 writel_relaxed(int_pol, 449 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); 450 writel_relaxed(int_any, 451 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num)); 452 453 if (type & IRQ_TYPE_LEVEL_MASK) { 454 irq_set_chip_handler_name_locked(irq_data, 455 &zynq_gpio_level_irqchip, handle_fasteoi_irq, NULL); 456 } else { 457 irq_set_chip_handler_name_locked(irq_data, 458 &zynq_gpio_edge_irqchip, handle_level_irq, NULL); 459 } 460 461 return 0; 462 } 463 464 static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on) 465 { 466 struct zynq_gpio *gpio = 467 to_zynq_gpio(irq_data_get_irq_chip_data(data)); 468 469 irq_set_irq_wake(gpio->irq, on); 470 471 return 0; 472 } 473 474 /* irq chip descriptor */ 475 static struct irq_chip zynq_gpio_level_irqchip = { 476 .name = DRIVER_NAME, 477 .irq_enable = zynq_gpio_irq_enable, 478 .irq_eoi = zynq_gpio_irq_ack, 479 .irq_mask = zynq_gpio_irq_mask, 480 .irq_unmask = zynq_gpio_irq_unmask, 481 .irq_set_type = zynq_gpio_set_irq_type, 482 .irq_set_wake = zynq_gpio_set_wake, 483 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED | 484 IRQCHIP_MASK_ON_SUSPEND, 485 }; 486 487 static struct irq_chip zynq_gpio_edge_irqchip = { 488 .name = DRIVER_NAME, 489 .irq_enable = zynq_gpio_irq_enable, 490 .irq_ack = zynq_gpio_irq_ack, 491 .irq_mask = zynq_gpio_irq_mask, 492 .irq_unmask = zynq_gpio_irq_unmask, 493 .irq_set_type = zynq_gpio_set_irq_type, 494 .irq_set_wake = zynq_gpio_set_wake, 495 .flags = IRQCHIP_MASK_ON_SUSPEND, 496 }; 497 498 static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio, 499 unsigned int bank_num, 500 unsigned long pending) 501 { 502 unsigned int bank_offset = gpio->p_data->bank_min[bank_num]; 503 struct irq_domain *irqdomain = gpio->chip.irqdomain; 504 int offset; 505 506 if (!pending) 507 return; 508 509 for_each_set_bit(offset, &pending, 32) { 510 unsigned int gpio_irq; 511 512 gpio_irq = irq_find_mapping(irqdomain, offset + bank_offset); 513 generic_handle_irq(gpio_irq); 514 } 515 } 516 517 /** 518 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device 519 * @irq: irq number of the gpio bank where interrupt has occurred 520 * @desc: irq descriptor instance of the 'irq' 521 * 522 * This function reads the Interrupt Status Register of each bank to get the 523 * gpio pin number which has triggered an interrupt. It then acks the triggered 524 * interrupt and calls the pin specific handler set by the higher layer 525 * application for that pin. 526 * Note: A bug is reported if no handler is set for the gpio pin. 527 */ 528 static void zynq_gpio_irqhandler(struct irq_desc *desc) 529 { 530 u32 int_sts, int_enb; 531 unsigned int bank_num; 532 struct zynq_gpio *gpio = 533 to_zynq_gpio(irq_desc_get_handler_data(desc)); 534 struct irq_chip *irqchip = irq_desc_get_chip(desc); 535 536 chained_irq_enter(irqchip, desc); 537 538 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { 539 int_sts = readl_relaxed(gpio->base_addr + 540 ZYNQ_GPIO_INTSTS_OFFSET(bank_num)); 541 int_enb = readl_relaxed(gpio->base_addr + 542 ZYNQ_GPIO_INTMASK_OFFSET(bank_num)); 543 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb); 544 } 545 546 chained_irq_exit(irqchip, desc); 547 } 548 549 static int __maybe_unused zynq_gpio_suspend(struct device *dev) 550 { 551 struct platform_device *pdev = to_platform_device(dev); 552 int irq = platform_get_irq(pdev, 0); 553 struct irq_data *data = irq_get_irq_data(irq); 554 555 if (!irqd_is_wakeup_set(data)) 556 return pm_runtime_force_suspend(dev); 557 558 return 0; 559 } 560 561 static int __maybe_unused zynq_gpio_resume(struct device *dev) 562 { 563 struct platform_device *pdev = to_platform_device(dev); 564 int irq = platform_get_irq(pdev, 0); 565 struct irq_data *data = irq_get_irq_data(irq); 566 567 if (!irqd_is_wakeup_set(data)) 568 return pm_runtime_force_resume(dev); 569 570 return 0; 571 } 572 573 static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev) 574 { 575 struct platform_device *pdev = to_platform_device(dev); 576 struct zynq_gpio *gpio = platform_get_drvdata(pdev); 577 578 clk_disable_unprepare(gpio->clk); 579 580 return 0; 581 } 582 583 static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev) 584 { 585 struct platform_device *pdev = to_platform_device(dev); 586 struct zynq_gpio *gpio = platform_get_drvdata(pdev); 587 588 return clk_prepare_enable(gpio->clk); 589 } 590 591 static int zynq_gpio_request(struct gpio_chip *chip, unsigned offset) 592 { 593 int ret; 594 595 ret = pm_runtime_get_sync(chip->dev); 596 597 /* 598 * If the device is already active pm_runtime_get() will return 1 on 599 * success, but gpio_request still needs to return 0. 600 */ 601 return ret < 0 ? ret : 0; 602 } 603 604 static void zynq_gpio_free(struct gpio_chip *chip, unsigned offset) 605 { 606 pm_runtime_put(chip->dev); 607 } 608 609 static const struct dev_pm_ops zynq_gpio_dev_pm_ops = { 610 SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume) 611 SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend, 612 zynq_gpio_runtime_resume, NULL) 613 }; 614 615 static const struct zynq_platform_data zynqmp_gpio_def = { 616 .label = "zynqmp_gpio", 617 .ngpio = ZYNQMP_GPIO_NR_GPIOS, 618 .max_bank = ZYNQMP_GPIO_MAX_BANK, 619 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP), 620 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP), 621 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP), 622 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP), 623 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP), 624 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP), 625 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP), 626 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP), 627 .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP), 628 .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP), 629 .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP), 630 .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP), 631 }; 632 633 static const struct zynq_platform_data zynq_gpio_def = { 634 .label = "zynq_gpio", 635 .ngpio = ZYNQ_GPIO_NR_GPIOS, 636 .max_bank = ZYNQ_GPIO_MAX_BANK, 637 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(), 638 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(), 639 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(), 640 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(), 641 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(), 642 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(), 643 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(), 644 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(), 645 }; 646 647 static const struct of_device_id zynq_gpio_of_match[] = { 648 { .compatible = "xlnx,zynq-gpio-1.0", .data = (void *)&zynq_gpio_def }, 649 { .compatible = "xlnx,zynqmp-gpio-1.0", 650 .data = (void *)&zynqmp_gpio_def }, 651 { /* end of table */ } 652 }; 653 MODULE_DEVICE_TABLE(of, zynq_gpio_of_match); 654 655 /** 656 * zynq_gpio_probe - Initialization method for a zynq_gpio device 657 * @pdev: platform device instance 658 * 659 * This function allocates memory resources for the gpio device and registers 660 * all the banks of the device. It will also set up interrupts for the gpio 661 * pins. 662 * Note: Interrupts are disabled for all the banks during initialization. 663 * 664 * Return: 0 on success, negative error otherwise. 665 */ 666 static int zynq_gpio_probe(struct platform_device *pdev) 667 { 668 int ret, bank_num; 669 struct zynq_gpio *gpio; 670 struct gpio_chip *chip; 671 struct resource *res; 672 const struct of_device_id *match; 673 674 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 675 if (!gpio) 676 return -ENOMEM; 677 678 match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node); 679 if (!match) { 680 dev_err(&pdev->dev, "of_match_node() failed\n"); 681 return -EINVAL; 682 } 683 gpio->p_data = match->data; 684 platform_set_drvdata(pdev, gpio); 685 686 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 687 gpio->base_addr = devm_ioremap_resource(&pdev->dev, res); 688 if (IS_ERR(gpio->base_addr)) 689 return PTR_ERR(gpio->base_addr); 690 691 gpio->irq = platform_get_irq(pdev, 0); 692 if (gpio->irq < 0) { 693 dev_err(&pdev->dev, "invalid IRQ\n"); 694 return gpio->irq; 695 } 696 697 /* configure the gpio chip */ 698 chip = &gpio->chip; 699 chip->label = gpio->p_data->label; 700 chip->owner = THIS_MODULE; 701 chip->dev = &pdev->dev; 702 chip->get = zynq_gpio_get_value; 703 chip->set = zynq_gpio_set_value; 704 chip->request = zynq_gpio_request; 705 chip->free = zynq_gpio_free; 706 chip->direction_input = zynq_gpio_dir_in; 707 chip->direction_output = zynq_gpio_dir_out; 708 chip->base = -1; 709 chip->ngpio = gpio->p_data->ngpio; 710 711 /* Enable GPIO clock */ 712 gpio->clk = devm_clk_get(&pdev->dev, NULL); 713 if (IS_ERR(gpio->clk)) { 714 dev_err(&pdev->dev, "input clock not found.\n"); 715 return PTR_ERR(gpio->clk); 716 } 717 ret = clk_prepare_enable(gpio->clk); 718 if (ret) { 719 dev_err(&pdev->dev, "Unable to enable clock.\n"); 720 return ret; 721 } 722 723 /* report a bug if gpio chip registration fails */ 724 ret = gpiochip_add(chip); 725 if (ret) { 726 dev_err(&pdev->dev, "Failed to add gpio chip\n"); 727 goto err_disable_clk; 728 } 729 730 /* disable interrupts for all banks */ 731 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) 732 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr + 733 ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); 734 735 ret = gpiochip_irqchip_add(chip, &zynq_gpio_edge_irqchip, 0, 736 handle_level_irq, IRQ_TYPE_NONE); 737 if (ret) { 738 dev_err(&pdev->dev, "Failed to add irq chip\n"); 739 goto err_rm_gpiochip; 740 } 741 742 gpiochip_set_chained_irqchip(chip, &zynq_gpio_edge_irqchip, gpio->irq, 743 zynq_gpio_irqhandler); 744 745 pm_runtime_set_active(&pdev->dev); 746 pm_runtime_enable(&pdev->dev); 747 748 return 0; 749 750 err_rm_gpiochip: 751 gpiochip_remove(chip); 752 err_disable_clk: 753 clk_disable_unprepare(gpio->clk); 754 755 return ret; 756 } 757 758 /** 759 * zynq_gpio_remove - Driver removal function 760 * @pdev: platform device instance 761 * 762 * Return: 0 always 763 */ 764 static int zynq_gpio_remove(struct platform_device *pdev) 765 { 766 struct zynq_gpio *gpio = platform_get_drvdata(pdev); 767 768 pm_runtime_get_sync(&pdev->dev); 769 gpiochip_remove(&gpio->chip); 770 clk_disable_unprepare(gpio->clk); 771 device_set_wakeup_capable(&pdev->dev, 0); 772 pm_runtime_disable(&pdev->dev); 773 return 0; 774 } 775 776 static struct platform_driver zynq_gpio_driver = { 777 .driver = { 778 .name = DRIVER_NAME, 779 .pm = &zynq_gpio_dev_pm_ops, 780 .of_match_table = zynq_gpio_of_match, 781 }, 782 .probe = zynq_gpio_probe, 783 .remove = zynq_gpio_remove, 784 }; 785 786 /** 787 * zynq_gpio_init - Initial driver registration call 788 * 789 * Return: value from platform_driver_register 790 */ 791 static int __init zynq_gpio_init(void) 792 { 793 return platform_driver_register(&zynq_gpio_driver); 794 } 795 postcore_initcall(zynq_gpio_init); 796 797 static void __exit zynq_gpio_exit(void) 798 { 799 platform_driver_unregister(&zynq_gpio_driver); 800 } 801 module_exit(zynq_gpio_exit); 802 803 MODULE_AUTHOR("Xilinx Inc."); 804 MODULE_DESCRIPTION("Zynq GPIO driver"); 805 MODULE_LICENSE("GPL"); 806