1 /* 2 * Xilinx Zynq GPIO device driver 3 * 4 * Copyright (C) 2009 - 2014 Xilinx, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it under 7 * the terms of the GNU General Public License as published by the Free Software 8 * Foundation; either version 2 of the License, or (at your option) any later 9 * version. 10 */ 11 12 #include <linux/bitops.h> 13 #include <linux/clk.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/module.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/of.h> 22 23 #define DRIVER_NAME "zynq-gpio" 24 25 /* Maximum banks */ 26 #define ZYNQ_GPIO_MAX_BANK 4 27 #define ZYNQMP_GPIO_MAX_BANK 6 28 29 #define ZYNQ_GPIO_BANK0_NGPIO 32 30 #define ZYNQ_GPIO_BANK1_NGPIO 22 31 #define ZYNQ_GPIO_BANK2_NGPIO 32 32 #define ZYNQ_GPIO_BANK3_NGPIO 32 33 34 #define ZYNQMP_GPIO_BANK0_NGPIO 26 35 #define ZYNQMP_GPIO_BANK1_NGPIO 26 36 #define ZYNQMP_GPIO_BANK2_NGPIO 26 37 #define ZYNQMP_GPIO_BANK3_NGPIO 32 38 #define ZYNQMP_GPIO_BANK4_NGPIO 32 39 #define ZYNQMP_GPIO_BANK5_NGPIO 32 40 41 #define ZYNQ_GPIO_NR_GPIOS 118 42 #define ZYNQMP_GPIO_NR_GPIOS 174 43 44 #define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0 45 #define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \ 46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1) 47 #define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1) 48 #define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \ 49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1) 50 #define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1) 51 #define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \ 52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1) 53 #define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1) 54 #define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \ 55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1) 56 #define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1) 57 #define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \ 58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1) 59 #define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1) 60 #define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \ 61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1) 62 63 /* Register offsets for the GPIO device */ 64 /* LSW Mask & Data -WO */ 65 #define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK)) 66 /* MSW Mask & Data -WO */ 67 #define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK)) 68 /* Data Register-RW */ 69 #define ZYNQ_GPIO_DATA_OFFSET(BANK) (0x040 + (4 * BANK)) 70 #define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK)) 71 /* Direction mode reg-RW */ 72 #define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK)) 73 /* Output enable reg-RW */ 74 #define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK)) 75 /* Interrupt mask reg-RO */ 76 #define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK)) 77 /* Interrupt enable reg-WO */ 78 #define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK)) 79 /* Interrupt disable reg-WO */ 80 #define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK)) 81 /* Interrupt status reg-RO */ 82 #define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK)) 83 /* Interrupt type reg-RW */ 84 #define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK)) 85 /* Interrupt polarity reg-RW */ 86 #define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK)) 87 /* Interrupt on any, reg-RW */ 88 #define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK)) 89 90 /* Disable all interrupts mask */ 91 #define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF 92 93 /* Mid pin number of a bank */ 94 #define ZYNQ_GPIO_MID_PIN_NUM 16 95 96 /* GPIO upper 16 bit mask */ 97 #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000 98 99 /* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */ 100 #define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0) 101 #define GPIO_QUIRK_DATA_RO_BUG BIT(1) 102 103 struct gpio_regs { 104 u32 datamsw[ZYNQMP_GPIO_MAX_BANK]; 105 u32 datalsw[ZYNQMP_GPIO_MAX_BANK]; 106 u32 dirm[ZYNQMP_GPIO_MAX_BANK]; 107 u32 outen[ZYNQMP_GPIO_MAX_BANK]; 108 u32 int_en[ZYNQMP_GPIO_MAX_BANK]; 109 u32 int_dis[ZYNQMP_GPIO_MAX_BANK]; 110 u32 int_type[ZYNQMP_GPIO_MAX_BANK]; 111 u32 int_polarity[ZYNQMP_GPIO_MAX_BANK]; 112 u32 int_any[ZYNQMP_GPIO_MAX_BANK]; 113 }; 114 115 /** 116 * struct zynq_gpio - gpio device private data structure 117 * @chip: instance of the gpio_chip 118 * @base_addr: base address of the GPIO device 119 * @clk: clock resource for this controller 120 * @irq: interrupt for the GPIO device 121 * @p_data: pointer to platform data 122 * @context: context registers 123 */ 124 struct zynq_gpio { 125 struct gpio_chip chip; 126 void __iomem *base_addr; 127 struct clk *clk; 128 int irq; 129 const struct zynq_platform_data *p_data; 130 struct gpio_regs context; 131 }; 132 133 /** 134 * struct zynq_platform_data - zynq gpio platform data structure 135 * @label: string to store in gpio->label 136 * @quirks: Flags is used to identify the platform 137 * @ngpio: max number of gpio pins 138 * @max_bank: maximum number of gpio banks 139 * @bank_min: this array represents bank's min pin 140 * @bank_max: this array represents bank's max pin 141 */ 142 struct zynq_platform_data { 143 const char *label; 144 u32 quirks; 145 u16 ngpio; 146 int max_bank; 147 int bank_min[ZYNQMP_GPIO_MAX_BANK]; 148 int bank_max[ZYNQMP_GPIO_MAX_BANK]; 149 }; 150 151 static struct irq_chip zynq_gpio_level_irqchip; 152 static struct irq_chip zynq_gpio_edge_irqchip; 153 154 /** 155 * zynq_gpio_is_zynq - test if HW is zynq or zynqmp 156 * @gpio: Pointer to driver data struct 157 * 158 * Return: 0 if zynqmp, 1 if zynq. 159 */ 160 static int zynq_gpio_is_zynq(struct zynq_gpio *gpio) 161 { 162 return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ); 163 } 164 165 /** 166 * gpio_data_ro_bug - test if HW bug exists or not 167 * @gpio: Pointer to driver data struct 168 * 169 * Return: 0 if bug doesnot exist, 1 if bug exists. 170 */ 171 static int gpio_data_ro_bug(struct zynq_gpio *gpio) 172 { 173 return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG); 174 } 175 176 /** 177 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank 178 * for a given pin in the GPIO device 179 * @pin_num: gpio pin number within the device 180 * @bank_num: an output parameter used to return the bank number of the gpio 181 * pin 182 * @bank_pin_num: an output parameter used to return pin number within a bank 183 * for the given gpio pin 184 * @gpio: gpio device data structure 185 * 186 * Returns the bank number and pin offset within the bank. 187 */ 188 static inline void zynq_gpio_get_bank_pin(unsigned int pin_num, 189 unsigned int *bank_num, 190 unsigned int *bank_pin_num, 191 struct zynq_gpio *gpio) 192 { 193 int bank; 194 195 for (bank = 0; bank < gpio->p_data->max_bank; bank++) { 196 if ((pin_num >= gpio->p_data->bank_min[bank]) && 197 (pin_num <= gpio->p_data->bank_max[bank])) { 198 *bank_num = bank; 199 *bank_pin_num = pin_num - 200 gpio->p_data->bank_min[bank]; 201 return; 202 } 203 } 204 205 /* default */ 206 WARN(true, "invalid GPIO pin number: %u", pin_num); 207 *bank_num = 0; 208 *bank_pin_num = 0; 209 } 210 211 /** 212 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device 213 * @chip: gpio_chip instance to be worked on 214 * @pin: gpio pin number within the device 215 * 216 * This function reads the state of the specified pin of the GPIO device. 217 * 218 * Return: 0 if the pin is low, 1 if pin is high. 219 */ 220 static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin) 221 { 222 u32 data; 223 unsigned int bank_num, bank_pin_num; 224 struct zynq_gpio *gpio = gpiochip_get_data(chip); 225 226 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); 227 228 if (gpio_data_ro_bug(gpio)) { 229 if (zynq_gpio_is_zynq(gpio)) { 230 if (bank_num <= 1) { 231 data = readl_relaxed(gpio->base_addr + 232 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); 233 } else { 234 data = readl_relaxed(gpio->base_addr + 235 ZYNQ_GPIO_DATA_OFFSET(bank_num)); 236 } 237 } else { 238 if (bank_num <= 2) { 239 data = readl_relaxed(gpio->base_addr + 240 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); 241 } else { 242 data = readl_relaxed(gpio->base_addr + 243 ZYNQ_GPIO_DATA_OFFSET(bank_num)); 244 } 245 } 246 } else { 247 data = readl_relaxed(gpio->base_addr + 248 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); 249 } 250 return (data >> bank_pin_num) & 1; 251 } 252 253 /** 254 * zynq_gpio_set_value - Modify the state of the pin with specified value 255 * @chip: gpio_chip instance to be worked on 256 * @pin: gpio pin number within the device 257 * @state: value used to modify the state of the specified pin 258 * 259 * This function calculates the register offset (i.e to lower 16 bits or 260 * upper 16 bits) based on the given pin number and sets the state of a 261 * gpio pin to the specified value. The state is either 0 or non-zero. 262 */ 263 static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin, 264 int state) 265 { 266 unsigned int reg_offset, bank_num, bank_pin_num; 267 struct zynq_gpio *gpio = gpiochip_get_data(chip); 268 269 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); 270 271 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) { 272 /* only 16 data bits in bit maskable reg */ 273 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM; 274 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num); 275 } else { 276 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num); 277 } 278 279 /* 280 * get the 32 bit value to be written to the mask/data register where 281 * the upper 16 bits is the mask and lower 16 bits is the data 282 */ 283 state = !!state; 284 state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) & 285 ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK); 286 287 writel_relaxed(state, gpio->base_addr + reg_offset); 288 } 289 290 /** 291 * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input 292 * @chip: gpio_chip instance to be worked on 293 * @pin: gpio pin number within the device 294 * 295 * This function uses the read-modify-write sequence to set the direction of 296 * the gpio pin as input. 297 * 298 * Return: 0 always 299 */ 300 static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin) 301 { 302 u32 reg; 303 unsigned int bank_num, bank_pin_num; 304 struct zynq_gpio *gpio = gpiochip_get_data(chip); 305 306 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); 307 308 /* 309 * On zynq bank 0 pins 7 and 8 are special and cannot be used 310 * as inputs. 311 */ 312 if (zynq_gpio_is_zynq(gpio) && bank_num == 0 && 313 (bank_pin_num == 7 || bank_pin_num == 8)) 314 return -EINVAL; 315 316 /* clear the bit in direction mode reg to set the pin as input */ 317 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 318 reg &= ~BIT(bank_pin_num); 319 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 320 321 return 0; 322 } 323 324 /** 325 * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output 326 * @chip: gpio_chip instance to be worked on 327 * @pin: gpio pin number within the device 328 * @state: value to be written to specified pin 329 * 330 * This function sets the direction of specified GPIO pin as output, configures 331 * the Output Enable register for the pin and uses zynq_gpio_set to set 332 * the state of the pin to the value specified. 333 * 334 * Return: 0 always 335 */ 336 static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, 337 int state) 338 { 339 u32 reg; 340 unsigned int bank_num, bank_pin_num; 341 struct zynq_gpio *gpio = gpiochip_get_data(chip); 342 343 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); 344 345 /* set the GPIO pin as output */ 346 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 347 reg |= BIT(bank_pin_num); 348 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 349 350 /* configure the output enable reg for the pin */ 351 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); 352 reg |= BIT(bank_pin_num); 353 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); 354 355 /* set the state of the pin */ 356 zynq_gpio_set_value(chip, pin, state); 357 return 0; 358 } 359 360 /** 361 * zynq_gpio_get_direction - Read the direction of the specified GPIO pin 362 * @chip: gpio_chip instance to be worked on 363 * @pin: gpio pin number within the device 364 * 365 * This function returns the direction of the specified GPIO. 366 * 367 * Return: 0 for output, 1 for input 368 */ 369 static int zynq_gpio_get_direction(struct gpio_chip *chip, unsigned int pin) 370 { 371 u32 reg; 372 unsigned int bank_num, bank_pin_num; 373 struct zynq_gpio *gpio = gpiochip_get_data(chip); 374 375 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); 376 377 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 378 379 return !(reg & BIT(bank_pin_num)); 380 } 381 382 /** 383 * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin 384 * @irq_data: per irq and chip data passed down to chip functions 385 * 386 * This function calculates gpio pin number from irq number and sets the 387 * bit in the Interrupt Disable register of the corresponding bank to disable 388 * interrupts for that pin. 389 */ 390 static void zynq_gpio_irq_mask(struct irq_data *irq_data) 391 { 392 unsigned int device_pin_num, bank_num, bank_pin_num; 393 struct zynq_gpio *gpio = 394 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data)); 395 396 device_pin_num = irq_data->hwirq; 397 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); 398 writel_relaxed(BIT(bank_pin_num), 399 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); 400 } 401 402 /** 403 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin 404 * @irq_data: irq data containing irq number of gpio pin for the interrupt 405 * to enable 406 * 407 * This function calculates the gpio pin number from irq number and sets the 408 * bit in the Interrupt Enable register of the corresponding bank to enable 409 * interrupts for that pin. 410 */ 411 static void zynq_gpio_irq_unmask(struct irq_data *irq_data) 412 { 413 unsigned int device_pin_num, bank_num, bank_pin_num; 414 struct zynq_gpio *gpio = 415 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data)); 416 417 device_pin_num = irq_data->hwirq; 418 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); 419 writel_relaxed(BIT(bank_pin_num), 420 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num)); 421 } 422 423 /** 424 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin 425 * @irq_data: irq data containing irq number of gpio pin for the interrupt 426 * to ack 427 * 428 * This function calculates gpio pin number from irq number and sets the bit 429 * in the Interrupt Status Register of the corresponding bank, to ACK the irq. 430 */ 431 static void zynq_gpio_irq_ack(struct irq_data *irq_data) 432 { 433 unsigned int device_pin_num, bank_num, bank_pin_num; 434 struct zynq_gpio *gpio = 435 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data)); 436 437 device_pin_num = irq_data->hwirq; 438 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); 439 writel_relaxed(BIT(bank_pin_num), 440 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num)); 441 } 442 443 /** 444 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin 445 * @irq_data: irq data containing irq number of gpio pin for the interrupt 446 * to enable 447 * 448 * Clears the INTSTS bit and unmasks the given interrupt. 449 */ 450 static void zynq_gpio_irq_enable(struct irq_data *irq_data) 451 { 452 /* 453 * The Zynq GPIO controller does not disable interrupt detection when 454 * the interrupt is masked and only disables the propagation of the 455 * interrupt. This means when the controller detects an interrupt 456 * condition while the interrupt is logically disabled it will propagate 457 * that interrupt event once the interrupt is enabled. This will cause 458 * the interrupt consumer to see spurious interrupts to prevent this 459 * first make sure that the interrupt is not asserted and then enable 460 * it. 461 */ 462 zynq_gpio_irq_ack(irq_data); 463 zynq_gpio_irq_unmask(irq_data); 464 } 465 466 /** 467 * zynq_gpio_set_irq_type - Set the irq type for a gpio pin 468 * @irq_data: irq data containing irq number of gpio pin 469 * @type: interrupt type that is to be set for the gpio pin 470 * 471 * This function gets the gpio pin number and its bank from the gpio pin number 472 * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers. 473 * 474 * Return: 0, negative error otherwise. 475 * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0; 476 * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0; 477 * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1; 478 * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA; 479 * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA 480 */ 481 static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type) 482 { 483 u32 int_type, int_pol, int_any; 484 unsigned int device_pin_num, bank_num, bank_pin_num; 485 struct zynq_gpio *gpio = 486 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data)); 487 488 device_pin_num = irq_data->hwirq; 489 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); 490 491 int_type = readl_relaxed(gpio->base_addr + 492 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); 493 int_pol = readl_relaxed(gpio->base_addr + 494 ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); 495 int_any = readl_relaxed(gpio->base_addr + 496 ZYNQ_GPIO_INTANY_OFFSET(bank_num)); 497 498 /* 499 * based on the type requested, configure the INT_TYPE, INT_POLARITY 500 * and INT_ANY registers 501 */ 502 switch (type) { 503 case IRQ_TYPE_EDGE_RISING: 504 int_type |= BIT(bank_pin_num); 505 int_pol |= BIT(bank_pin_num); 506 int_any &= ~BIT(bank_pin_num); 507 break; 508 case IRQ_TYPE_EDGE_FALLING: 509 int_type |= BIT(bank_pin_num); 510 int_pol &= ~BIT(bank_pin_num); 511 int_any &= ~BIT(bank_pin_num); 512 break; 513 case IRQ_TYPE_EDGE_BOTH: 514 int_type |= BIT(bank_pin_num); 515 int_any |= BIT(bank_pin_num); 516 break; 517 case IRQ_TYPE_LEVEL_HIGH: 518 int_type &= ~BIT(bank_pin_num); 519 int_pol |= BIT(bank_pin_num); 520 break; 521 case IRQ_TYPE_LEVEL_LOW: 522 int_type &= ~BIT(bank_pin_num); 523 int_pol &= ~BIT(bank_pin_num); 524 break; 525 default: 526 return -EINVAL; 527 } 528 529 writel_relaxed(int_type, 530 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); 531 writel_relaxed(int_pol, 532 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); 533 writel_relaxed(int_any, 534 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num)); 535 536 if (type & IRQ_TYPE_LEVEL_MASK) 537 irq_set_chip_handler_name_locked(irq_data, 538 &zynq_gpio_level_irqchip, 539 handle_fasteoi_irq, NULL); 540 else 541 irq_set_chip_handler_name_locked(irq_data, 542 &zynq_gpio_edge_irqchip, 543 handle_level_irq, NULL); 544 545 return 0; 546 } 547 548 static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on) 549 { 550 struct zynq_gpio *gpio = 551 gpiochip_get_data(irq_data_get_irq_chip_data(data)); 552 553 irq_set_irq_wake(gpio->irq, on); 554 555 return 0; 556 } 557 558 static int zynq_gpio_irq_reqres(struct irq_data *d) 559 { 560 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 561 int ret; 562 563 ret = pm_runtime_get_sync(chip->parent); 564 if (ret < 0) 565 return ret; 566 567 return gpiochip_reqres_irq(chip, d->hwirq); 568 } 569 570 static void zynq_gpio_irq_relres(struct irq_data *d) 571 { 572 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 573 574 gpiochip_relres_irq(chip, d->hwirq); 575 pm_runtime_put(chip->parent); 576 } 577 578 /* irq chip descriptor */ 579 static struct irq_chip zynq_gpio_level_irqchip = { 580 .name = DRIVER_NAME, 581 .irq_enable = zynq_gpio_irq_enable, 582 .irq_eoi = zynq_gpio_irq_ack, 583 .irq_mask = zynq_gpio_irq_mask, 584 .irq_unmask = zynq_gpio_irq_unmask, 585 .irq_set_type = zynq_gpio_set_irq_type, 586 .irq_set_wake = zynq_gpio_set_wake, 587 .irq_request_resources = zynq_gpio_irq_reqres, 588 .irq_release_resources = zynq_gpio_irq_relres, 589 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED | 590 IRQCHIP_MASK_ON_SUSPEND, 591 }; 592 593 static struct irq_chip zynq_gpio_edge_irqchip = { 594 .name = DRIVER_NAME, 595 .irq_enable = zynq_gpio_irq_enable, 596 .irq_ack = zynq_gpio_irq_ack, 597 .irq_mask = zynq_gpio_irq_mask, 598 .irq_unmask = zynq_gpio_irq_unmask, 599 .irq_set_type = zynq_gpio_set_irq_type, 600 .irq_set_wake = zynq_gpio_set_wake, 601 .irq_request_resources = zynq_gpio_irq_reqres, 602 .irq_release_resources = zynq_gpio_irq_relres, 603 .flags = IRQCHIP_MASK_ON_SUSPEND, 604 }; 605 606 static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio, 607 unsigned int bank_num, 608 unsigned long pending) 609 { 610 unsigned int bank_offset = gpio->p_data->bank_min[bank_num]; 611 struct irq_domain *irqdomain = gpio->chip.irq.domain; 612 int offset; 613 614 if (!pending) 615 return; 616 617 for_each_set_bit(offset, &pending, 32) { 618 unsigned int gpio_irq; 619 620 gpio_irq = irq_find_mapping(irqdomain, offset + bank_offset); 621 generic_handle_irq(gpio_irq); 622 } 623 } 624 625 /** 626 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device 627 * @desc: irq descriptor instance of the 'irq' 628 * 629 * This function reads the Interrupt Status Register of each bank to get the 630 * gpio pin number which has triggered an interrupt. It then acks the triggered 631 * interrupt and calls the pin specific handler set by the higher layer 632 * application for that pin. 633 * Note: A bug is reported if no handler is set for the gpio pin. 634 */ 635 static void zynq_gpio_irqhandler(struct irq_desc *desc) 636 { 637 u32 int_sts, int_enb; 638 unsigned int bank_num; 639 struct zynq_gpio *gpio = 640 gpiochip_get_data(irq_desc_get_handler_data(desc)); 641 struct irq_chip *irqchip = irq_desc_get_chip(desc); 642 643 chained_irq_enter(irqchip, desc); 644 645 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { 646 int_sts = readl_relaxed(gpio->base_addr + 647 ZYNQ_GPIO_INTSTS_OFFSET(bank_num)); 648 int_enb = readl_relaxed(gpio->base_addr + 649 ZYNQ_GPIO_INTMASK_OFFSET(bank_num)); 650 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb); 651 } 652 653 chained_irq_exit(irqchip, desc); 654 } 655 656 static void zynq_gpio_save_context(struct zynq_gpio *gpio) 657 { 658 unsigned int bank_num; 659 660 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { 661 gpio->context.datalsw[bank_num] = 662 readl_relaxed(gpio->base_addr + 663 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num)); 664 gpio->context.datamsw[bank_num] = 665 readl_relaxed(gpio->base_addr + 666 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num)); 667 gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr + 668 ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 669 gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr + 670 ZYNQ_GPIO_INTMASK_OFFSET(bank_num)); 671 gpio->context.int_type[bank_num] = 672 readl_relaxed(gpio->base_addr + 673 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); 674 gpio->context.int_polarity[bank_num] = 675 readl_relaxed(gpio->base_addr + 676 ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); 677 gpio->context.int_any[bank_num] = 678 readl_relaxed(gpio->base_addr + 679 ZYNQ_GPIO_INTANY_OFFSET(bank_num)); 680 } 681 } 682 683 static void zynq_gpio_restore_context(struct zynq_gpio *gpio) 684 { 685 unsigned int bank_num; 686 687 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { 688 writel_relaxed(gpio->context.datalsw[bank_num], 689 gpio->base_addr + 690 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num)); 691 writel_relaxed(gpio->context.datamsw[bank_num], 692 gpio->base_addr + 693 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num)); 694 writel_relaxed(gpio->context.dirm[bank_num], 695 gpio->base_addr + 696 ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 697 writel_relaxed(gpio->context.int_en[bank_num], 698 gpio->base_addr + 699 ZYNQ_GPIO_INTEN_OFFSET(bank_num)); 700 writel_relaxed(gpio->context.int_type[bank_num], 701 gpio->base_addr + 702 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); 703 writel_relaxed(gpio->context.int_polarity[bank_num], 704 gpio->base_addr + 705 ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); 706 writel_relaxed(gpio->context.int_any[bank_num], 707 gpio->base_addr + 708 ZYNQ_GPIO_INTANY_OFFSET(bank_num)); 709 } 710 } 711 712 static int __maybe_unused zynq_gpio_suspend(struct device *dev) 713 { 714 struct zynq_gpio *gpio = dev_get_drvdata(dev); 715 struct irq_data *data = irq_get_irq_data(gpio->irq); 716 717 if (!irqd_is_wakeup_set(data)) { 718 zynq_gpio_save_context(gpio); 719 return pm_runtime_force_suspend(dev); 720 } 721 722 return 0; 723 } 724 725 static int __maybe_unused zynq_gpio_resume(struct device *dev) 726 { 727 struct zynq_gpio *gpio = dev_get_drvdata(dev); 728 struct irq_data *data = irq_get_irq_data(gpio->irq); 729 int ret; 730 731 if (!irqd_is_wakeup_set(data)) { 732 ret = pm_runtime_force_resume(dev); 733 zynq_gpio_restore_context(gpio); 734 return ret; 735 } 736 737 return 0; 738 } 739 740 static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev) 741 { 742 struct zynq_gpio *gpio = dev_get_drvdata(dev); 743 744 clk_disable_unprepare(gpio->clk); 745 746 return 0; 747 } 748 749 static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev) 750 { 751 struct zynq_gpio *gpio = dev_get_drvdata(dev); 752 753 return clk_prepare_enable(gpio->clk); 754 } 755 756 static int zynq_gpio_request(struct gpio_chip *chip, unsigned int offset) 757 { 758 int ret; 759 760 ret = pm_runtime_get_sync(chip->parent); 761 762 /* 763 * If the device is already active pm_runtime_get() will return 1 on 764 * success, but gpio_request still needs to return 0. 765 */ 766 return ret < 0 ? ret : 0; 767 } 768 769 static void zynq_gpio_free(struct gpio_chip *chip, unsigned int offset) 770 { 771 pm_runtime_put(chip->parent); 772 } 773 774 static const struct dev_pm_ops zynq_gpio_dev_pm_ops = { 775 SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume) 776 SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend, 777 zynq_gpio_runtime_resume, NULL) 778 }; 779 780 static const struct zynq_platform_data zynqmp_gpio_def = { 781 .label = "zynqmp_gpio", 782 .quirks = GPIO_QUIRK_DATA_RO_BUG, 783 .ngpio = ZYNQMP_GPIO_NR_GPIOS, 784 .max_bank = ZYNQMP_GPIO_MAX_BANK, 785 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP), 786 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP), 787 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP), 788 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP), 789 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP), 790 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP), 791 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP), 792 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP), 793 .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP), 794 .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP), 795 .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP), 796 .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP), 797 }; 798 799 static const struct zynq_platform_data zynq_gpio_def = { 800 .label = "zynq_gpio", 801 .quirks = ZYNQ_GPIO_QUIRK_IS_ZYNQ | GPIO_QUIRK_DATA_RO_BUG, 802 .ngpio = ZYNQ_GPIO_NR_GPIOS, 803 .max_bank = ZYNQ_GPIO_MAX_BANK, 804 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(), 805 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(), 806 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(), 807 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(), 808 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(), 809 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(), 810 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(), 811 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(), 812 }; 813 814 static const struct of_device_id zynq_gpio_of_match[] = { 815 { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def }, 816 { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def }, 817 { /* end of table */ } 818 }; 819 MODULE_DEVICE_TABLE(of, zynq_gpio_of_match); 820 821 /** 822 * zynq_gpio_probe - Initialization method for a zynq_gpio device 823 * @pdev: platform device instance 824 * 825 * This function allocates memory resources for the gpio device and registers 826 * all the banks of the device. It will also set up interrupts for the gpio 827 * pins. 828 * Note: Interrupts are disabled for all the banks during initialization. 829 * 830 * Return: 0 on success, negative error otherwise. 831 */ 832 static int zynq_gpio_probe(struct platform_device *pdev) 833 { 834 int ret, bank_num; 835 struct zynq_gpio *gpio; 836 struct gpio_chip *chip; 837 struct resource *res; 838 const struct of_device_id *match; 839 840 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 841 if (!gpio) 842 return -ENOMEM; 843 844 match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node); 845 if (!match) { 846 dev_err(&pdev->dev, "of_match_node() failed\n"); 847 return -EINVAL; 848 } 849 gpio->p_data = match->data; 850 platform_set_drvdata(pdev, gpio); 851 852 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 853 gpio->base_addr = devm_ioremap_resource(&pdev->dev, res); 854 if (IS_ERR(gpio->base_addr)) 855 return PTR_ERR(gpio->base_addr); 856 857 gpio->irq = platform_get_irq(pdev, 0); 858 if (gpio->irq < 0) { 859 dev_err(&pdev->dev, "invalid IRQ\n"); 860 return gpio->irq; 861 } 862 863 /* configure the gpio chip */ 864 chip = &gpio->chip; 865 chip->label = gpio->p_data->label; 866 chip->owner = THIS_MODULE; 867 chip->parent = &pdev->dev; 868 chip->get = zynq_gpio_get_value; 869 chip->set = zynq_gpio_set_value; 870 chip->request = zynq_gpio_request; 871 chip->free = zynq_gpio_free; 872 chip->direction_input = zynq_gpio_dir_in; 873 chip->direction_output = zynq_gpio_dir_out; 874 chip->get_direction = zynq_gpio_get_direction; 875 chip->base = of_alias_get_id(pdev->dev.of_node, "gpio"); 876 chip->ngpio = gpio->p_data->ngpio; 877 878 /* Retrieve GPIO clock */ 879 gpio->clk = devm_clk_get(&pdev->dev, NULL); 880 if (IS_ERR(gpio->clk)) { 881 dev_err(&pdev->dev, "input clock not found.\n"); 882 return PTR_ERR(gpio->clk); 883 } 884 ret = clk_prepare_enable(gpio->clk); 885 if (ret) { 886 dev_err(&pdev->dev, "Unable to enable clock.\n"); 887 return ret; 888 } 889 890 pm_runtime_set_active(&pdev->dev); 891 pm_runtime_enable(&pdev->dev); 892 ret = pm_runtime_get_sync(&pdev->dev); 893 if (ret < 0) 894 goto err_pm_dis; 895 896 /* report a bug if gpio chip registration fails */ 897 ret = gpiochip_add_data(chip, gpio); 898 if (ret) { 899 dev_err(&pdev->dev, "Failed to add gpio chip\n"); 900 goto err_pm_put; 901 } 902 903 /* disable interrupts for all banks */ 904 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) 905 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr + 906 ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); 907 908 ret = gpiochip_irqchip_add(chip, &zynq_gpio_edge_irqchip, 0, 909 handle_level_irq, IRQ_TYPE_NONE); 910 if (ret) { 911 dev_err(&pdev->dev, "Failed to add irq chip\n"); 912 goto err_rm_gpiochip; 913 } 914 915 gpiochip_set_chained_irqchip(chip, &zynq_gpio_edge_irqchip, gpio->irq, 916 zynq_gpio_irqhandler); 917 918 pm_runtime_put(&pdev->dev); 919 920 return 0; 921 922 err_rm_gpiochip: 923 gpiochip_remove(chip); 924 err_pm_put: 925 pm_runtime_put(&pdev->dev); 926 err_pm_dis: 927 pm_runtime_disable(&pdev->dev); 928 clk_disable_unprepare(gpio->clk); 929 930 return ret; 931 } 932 933 /** 934 * zynq_gpio_remove - Driver removal function 935 * @pdev: platform device instance 936 * 937 * Return: 0 always 938 */ 939 static int zynq_gpio_remove(struct platform_device *pdev) 940 { 941 struct zynq_gpio *gpio = platform_get_drvdata(pdev); 942 943 pm_runtime_get_sync(&pdev->dev); 944 gpiochip_remove(&gpio->chip); 945 clk_disable_unprepare(gpio->clk); 946 device_set_wakeup_capable(&pdev->dev, 0); 947 pm_runtime_disable(&pdev->dev); 948 return 0; 949 } 950 951 static struct platform_driver zynq_gpio_driver = { 952 .driver = { 953 .name = DRIVER_NAME, 954 .pm = &zynq_gpio_dev_pm_ops, 955 .of_match_table = zynq_gpio_of_match, 956 }, 957 .probe = zynq_gpio_probe, 958 .remove = zynq_gpio_remove, 959 }; 960 961 /** 962 * zynq_gpio_init - Initial driver registration call 963 * 964 * Return: value from platform_driver_register 965 */ 966 static int __init zynq_gpio_init(void) 967 { 968 return platform_driver_register(&zynq_gpio_driver); 969 } 970 postcore_initcall(zynq_gpio_init); 971 972 static void __exit zynq_gpio_exit(void) 973 { 974 platform_driver_unregister(&zynq_gpio_driver); 975 } 976 module_exit(zynq_gpio_exit); 977 978 MODULE_AUTHOR("Xilinx Inc."); 979 MODULE_DESCRIPTION("Zynq GPIO driver"); 980 MODULE_LICENSE("GPL"); 981