1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Xilinx Zynq GPIO device driver 4 * 5 * Copyright (C) 2009 - 2014 Xilinx, Inc. 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/of.h> 18 19 #define DRIVER_NAME "zynq-gpio" 20 21 /* Maximum banks */ 22 #define ZYNQ_GPIO_MAX_BANK 4 23 #define ZYNQMP_GPIO_MAX_BANK 6 24 25 #define ZYNQ_GPIO_BANK0_NGPIO 32 26 #define ZYNQ_GPIO_BANK1_NGPIO 22 27 #define ZYNQ_GPIO_BANK2_NGPIO 32 28 #define ZYNQ_GPIO_BANK3_NGPIO 32 29 30 #define ZYNQMP_GPIO_BANK0_NGPIO 26 31 #define ZYNQMP_GPIO_BANK1_NGPIO 26 32 #define ZYNQMP_GPIO_BANK2_NGPIO 26 33 #define ZYNQMP_GPIO_BANK3_NGPIO 32 34 #define ZYNQMP_GPIO_BANK4_NGPIO 32 35 #define ZYNQMP_GPIO_BANK5_NGPIO 32 36 37 #define ZYNQ_GPIO_NR_GPIOS 118 38 #define ZYNQMP_GPIO_NR_GPIOS 174 39 40 #define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0 41 #define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \ 42 ZYNQ##str##_GPIO_BANK0_NGPIO - 1) 43 #define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1) 44 #define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \ 45 ZYNQ##str##_GPIO_BANK1_NGPIO - 1) 46 #define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1) 47 #define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \ 48 ZYNQ##str##_GPIO_BANK2_NGPIO - 1) 49 #define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1) 50 #define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \ 51 ZYNQ##str##_GPIO_BANK3_NGPIO - 1) 52 #define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1) 53 #define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \ 54 ZYNQ##str##_GPIO_BANK4_NGPIO - 1) 55 #define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1) 56 #define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \ 57 ZYNQ##str##_GPIO_BANK5_NGPIO - 1) 58 59 /* Register offsets for the GPIO device */ 60 /* LSW Mask & Data -WO */ 61 #define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK)) 62 /* MSW Mask & Data -WO */ 63 #define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK)) 64 /* Data Register-RW */ 65 #define ZYNQ_GPIO_DATA_OFFSET(BANK) (0x040 + (4 * BANK)) 66 #define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK)) 67 /* Direction mode reg-RW */ 68 #define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK)) 69 /* Output enable reg-RW */ 70 #define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK)) 71 /* Interrupt mask reg-RO */ 72 #define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK)) 73 /* Interrupt enable reg-WO */ 74 #define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK)) 75 /* Interrupt disable reg-WO */ 76 #define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK)) 77 /* Interrupt status reg-RO */ 78 #define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK)) 79 /* Interrupt type reg-RW */ 80 #define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK)) 81 /* Interrupt polarity reg-RW */ 82 #define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK)) 83 /* Interrupt on any, reg-RW */ 84 #define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK)) 85 86 /* Disable all interrupts mask */ 87 #define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF 88 89 /* Mid pin number of a bank */ 90 #define ZYNQ_GPIO_MID_PIN_NUM 16 91 92 /* GPIO upper 16 bit mask */ 93 #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000 94 95 /* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */ 96 #define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0) 97 #define GPIO_QUIRK_DATA_RO_BUG BIT(1) 98 99 struct gpio_regs { 100 u32 datamsw[ZYNQMP_GPIO_MAX_BANK]; 101 u32 datalsw[ZYNQMP_GPIO_MAX_BANK]; 102 u32 dirm[ZYNQMP_GPIO_MAX_BANK]; 103 u32 outen[ZYNQMP_GPIO_MAX_BANK]; 104 u32 int_en[ZYNQMP_GPIO_MAX_BANK]; 105 u32 int_dis[ZYNQMP_GPIO_MAX_BANK]; 106 u32 int_type[ZYNQMP_GPIO_MAX_BANK]; 107 u32 int_polarity[ZYNQMP_GPIO_MAX_BANK]; 108 u32 int_any[ZYNQMP_GPIO_MAX_BANK]; 109 }; 110 111 /** 112 * struct zynq_gpio - gpio device private data structure 113 * @chip: instance of the gpio_chip 114 * @base_addr: base address of the GPIO device 115 * @clk: clock resource for this controller 116 * @irq: interrupt for the GPIO device 117 * @p_data: pointer to platform data 118 * @context: context registers 119 */ 120 struct zynq_gpio { 121 struct gpio_chip chip; 122 void __iomem *base_addr; 123 struct clk *clk; 124 int irq; 125 const struct zynq_platform_data *p_data; 126 struct gpio_regs context; 127 }; 128 129 /** 130 * struct zynq_platform_data - zynq gpio platform data structure 131 * @label: string to store in gpio->label 132 * @quirks: Flags is used to identify the platform 133 * @ngpio: max number of gpio pins 134 * @max_bank: maximum number of gpio banks 135 * @bank_min: this array represents bank's min pin 136 * @bank_max: this array represents bank's max pin 137 */ 138 struct zynq_platform_data { 139 const char *label; 140 u32 quirks; 141 u16 ngpio; 142 int max_bank; 143 int bank_min[ZYNQMP_GPIO_MAX_BANK]; 144 int bank_max[ZYNQMP_GPIO_MAX_BANK]; 145 }; 146 147 static struct irq_chip zynq_gpio_level_irqchip; 148 static struct irq_chip zynq_gpio_edge_irqchip; 149 150 /** 151 * zynq_gpio_is_zynq - test if HW is zynq or zynqmp 152 * @gpio: Pointer to driver data struct 153 * 154 * Return: 0 if zynqmp, 1 if zynq. 155 */ 156 static int zynq_gpio_is_zynq(struct zynq_gpio *gpio) 157 { 158 return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ); 159 } 160 161 /** 162 * gpio_data_ro_bug - test if HW bug exists or not 163 * @gpio: Pointer to driver data struct 164 * 165 * Return: 0 if bug doesnot exist, 1 if bug exists. 166 */ 167 static int gpio_data_ro_bug(struct zynq_gpio *gpio) 168 { 169 return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG); 170 } 171 172 /** 173 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank 174 * for a given pin in the GPIO device 175 * @pin_num: gpio pin number within the device 176 * @bank_num: an output parameter used to return the bank number of the gpio 177 * pin 178 * @bank_pin_num: an output parameter used to return pin number within a bank 179 * for the given gpio pin 180 * @gpio: gpio device data structure 181 * 182 * Returns the bank number and pin offset within the bank. 183 */ 184 static inline void zynq_gpio_get_bank_pin(unsigned int pin_num, 185 unsigned int *bank_num, 186 unsigned int *bank_pin_num, 187 struct zynq_gpio *gpio) 188 { 189 int bank; 190 191 for (bank = 0; bank < gpio->p_data->max_bank; bank++) { 192 if ((pin_num >= gpio->p_data->bank_min[bank]) && 193 (pin_num <= gpio->p_data->bank_max[bank])) { 194 *bank_num = bank; 195 *bank_pin_num = pin_num - 196 gpio->p_data->bank_min[bank]; 197 return; 198 } 199 } 200 201 /* default */ 202 WARN(true, "invalid GPIO pin number: %u", pin_num); 203 *bank_num = 0; 204 *bank_pin_num = 0; 205 } 206 207 /** 208 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device 209 * @chip: gpio_chip instance to be worked on 210 * @pin: gpio pin number within the device 211 * 212 * This function reads the state of the specified pin of the GPIO device. 213 * 214 * Return: 0 if the pin is low, 1 if pin is high. 215 */ 216 static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin) 217 { 218 u32 data; 219 unsigned int bank_num, bank_pin_num; 220 struct zynq_gpio *gpio = gpiochip_get_data(chip); 221 222 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); 223 224 if (gpio_data_ro_bug(gpio)) { 225 if (zynq_gpio_is_zynq(gpio)) { 226 if (bank_num <= 1) { 227 data = readl_relaxed(gpio->base_addr + 228 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); 229 } else { 230 data = readl_relaxed(gpio->base_addr + 231 ZYNQ_GPIO_DATA_OFFSET(bank_num)); 232 } 233 } else { 234 if (bank_num <= 2) { 235 data = readl_relaxed(gpio->base_addr + 236 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); 237 } else { 238 data = readl_relaxed(gpio->base_addr + 239 ZYNQ_GPIO_DATA_OFFSET(bank_num)); 240 } 241 } 242 } else { 243 data = readl_relaxed(gpio->base_addr + 244 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); 245 } 246 return (data >> bank_pin_num) & 1; 247 } 248 249 /** 250 * zynq_gpio_set_value - Modify the state of the pin with specified value 251 * @chip: gpio_chip instance to be worked on 252 * @pin: gpio pin number within the device 253 * @state: value used to modify the state of the specified pin 254 * 255 * This function calculates the register offset (i.e to lower 16 bits or 256 * upper 16 bits) based on the given pin number and sets the state of a 257 * gpio pin to the specified value. The state is either 0 or non-zero. 258 */ 259 static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin, 260 int state) 261 { 262 unsigned int reg_offset, bank_num, bank_pin_num; 263 struct zynq_gpio *gpio = gpiochip_get_data(chip); 264 265 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); 266 267 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) { 268 /* only 16 data bits in bit maskable reg */ 269 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM; 270 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num); 271 } else { 272 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num); 273 } 274 275 /* 276 * get the 32 bit value to be written to the mask/data register where 277 * the upper 16 bits is the mask and lower 16 bits is the data 278 */ 279 state = !!state; 280 state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) & 281 ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK); 282 283 writel_relaxed(state, gpio->base_addr + reg_offset); 284 } 285 286 /** 287 * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input 288 * @chip: gpio_chip instance to be worked on 289 * @pin: gpio pin number within the device 290 * 291 * This function uses the read-modify-write sequence to set the direction of 292 * the gpio pin as input. 293 * 294 * Return: 0 always 295 */ 296 static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin) 297 { 298 u32 reg; 299 unsigned int bank_num, bank_pin_num; 300 struct zynq_gpio *gpio = gpiochip_get_data(chip); 301 302 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); 303 304 /* 305 * On zynq bank 0 pins 7 and 8 are special and cannot be used 306 * as inputs. 307 */ 308 if (zynq_gpio_is_zynq(gpio) && bank_num == 0 && 309 (bank_pin_num == 7 || bank_pin_num == 8)) 310 return -EINVAL; 311 312 /* clear the bit in direction mode reg to set the pin as input */ 313 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 314 reg &= ~BIT(bank_pin_num); 315 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 316 317 return 0; 318 } 319 320 /** 321 * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output 322 * @chip: gpio_chip instance to be worked on 323 * @pin: gpio pin number within the device 324 * @state: value to be written to specified pin 325 * 326 * This function sets the direction of specified GPIO pin as output, configures 327 * the Output Enable register for the pin and uses zynq_gpio_set to set 328 * the state of the pin to the value specified. 329 * 330 * Return: 0 always 331 */ 332 static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, 333 int state) 334 { 335 u32 reg; 336 unsigned int bank_num, bank_pin_num; 337 struct zynq_gpio *gpio = gpiochip_get_data(chip); 338 339 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); 340 341 /* set the GPIO pin as output */ 342 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 343 reg |= BIT(bank_pin_num); 344 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 345 346 /* configure the output enable reg for the pin */ 347 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); 348 reg |= BIT(bank_pin_num); 349 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); 350 351 /* set the state of the pin */ 352 zynq_gpio_set_value(chip, pin, state); 353 return 0; 354 } 355 356 /** 357 * zynq_gpio_get_direction - Read the direction of the specified GPIO pin 358 * @chip: gpio_chip instance to be worked on 359 * @pin: gpio pin number within the device 360 * 361 * This function returns the direction of the specified GPIO. 362 * 363 * Return: 0 for output, 1 for input 364 */ 365 static int zynq_gpio_get_direction(struct gpio_chip *chip, unsigned int pin) 366 { 367 u32 reg; 368 unsigned int bank_num, bank_pin_num; 369 struct zynq_gpio *gpio = gpiochip_get_data(chip); 370 371 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); 372 373 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 374 375 return !(reg & BIT(bank_pin_num)); 376 } 377 378 /** 379 * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin 380 * @irq_data: per irq and chip data passed down to chip functions 381 * 382 * This function calculates gpio pin number from irq number and sets the 383 * bit in the Interrupt Disable register of the corresponding bank to disable 384 * interrupts for that pin. 385 */ 386 static void zynq_gpio_irq_mask(struct irq_data *irq_data) 387 { 388 unsigned int device_pin_num, bank_num, bank_pin_num; 389 struct zynq_gpio *gpio = 390 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data)); 391 392 device_pin_num = irq_data->hwirq; 393 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); 394 writel_relaxed(BIT(bank_pin_num), 395 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); 396 } 397 398 /** 399 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin 400 * @irq_data: irq data containing irq number of gpio pin for the interrupt 401 * to enable 402 * 403 * This function calculates the gpio pin number from irq number and sets the 404 * bit in the Interrupt Enable register of the corresponding bank to enable 405 * interrupts for that pin. 406 */ 407 static void zynq_gpio_irq_unmask(struct irq_data *irq_data) 408 { 409 unsigned int device_pin_num, bank_num, bank_pin_num; 410 struct zynq_gpio *gpio = 411 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data)); 412 413 device_pin_num = irq_data->hwirq; 414 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); 415 writel_relaxed(BIT(bank_pin_num), 416 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num)); 417 } 418 419 /** 420 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin 421 * @irq_data: irq data containing irq number of gpio pin for the interrupt 422 * to ack 423 * 424 * This function calculates gpio pin number from irq number and sets the bit 425 * in the Interrupt Status Register of the corresponding bank, to ACK the irq. 426 */ 427 static void zynq_gpio_irq_ack(struct irq_data *irq_data) 428 { 429 unsigned int device_pin_num, bank_num, bank_pin_num; 430 struct zynq_gpio *gpio = 431 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data)); 432 433 device_pin_num = irq_data->hwirq; 434 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); 435 writel_relaxed(BIT(bank_pin_num), 436 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num)); 437 } 438 439 /** 440 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin 441 * @irq_data: irq data containing irq number of gpio pin for the interrupt 442 * to enable 443 * 444 * Clears the INTSTS bit and unmasks the given interrupt. 445 */ 446 static void zynq_gpio_irq_enable(struct irq_data *irq_data) 447 { 448 /* 449 * The Zynq GPIO controller does not disable interrupt detection when 450 * the interrupt is masked and only disables the propagation of the 451 * interrupt. This means when the controller detects an interrupt 452 * condition while the interrupt is logically disabled it will propagate 453 * that interrupt event once the interrupt is enabled. This will cause 454 * the interrupt consumer to see spurious interrupts to prevent this 455 * first make sure that the interrupt is not asserted and then enable 456 * it. 457 */ 458 zynq_gpio_irq_ack(irq_data); 459 zynq_gpio_irq_unmask(irq_data); 460 } 461 462 /** 463 * zynq_gpio_set_irq_type - Set the irq type for a gpio pin 464 * @irq_data: irq data containing irq number of gpio pin 465 * @type: interrupt type that is to be set for the gpio pin 466 * 467 * This function gets the gpio pin number and its bank from the gpio pin number 468 * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers. 469 * 470 * Return: 0, negative error otherwise. 471 * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0; 472 * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0; 473 * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1; 474 * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA; 475 * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA 476 */ 477 static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type) 478 { 479 u32 int_type, int_pol, int_any; 480 unsigned int device_pin_num, bank_num, bank_pin_num; 481 struct zynq_gpio *gpio = 482 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data)); 483 484 device_pin_num = irq_data->hwirq; 485 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); 486 487 int_type = readl_relaxed(gpio->base_addr + 488 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); 489 int_pol = readl_relaxed(gpio->base_addr + 490 ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); 491 int_any = readl_relaxed(gpio->base_addr + 492 ZYNQ_GPIO_INTANY_OFFSET(bank_num)); 493 494 /* 495 * based on the type requested, configure the INT_TYPE, INT_POLARITY 496 * and INT_ANY registers 497 */ 498 switch (type) { 499 case IRQ_TYPE_EDGE_RISING: 500 int_type |= BIT(bank_pin_num); 501 int_pol |= BIT(bank_pin_num); 502 int_any &= ~BIT(bank_pin_num); 503 break; 504 case IRQ_TYPE_EDGE_FALLING: 505 int_type |= BIT(bank_pin_num); 506 int_pol &= ~BIT(bank_pin_num); 507 int_any &= ~BIT(bank_pin_num); 508 break; 509 case IRQ_TYPE_EDGE_BOTH: 510 int_type |= BIT(bank_pin_num); 511 int_any |= BIT(bank_pin_num); 512 break; 513 case IRQ_TYPE_LEVEL_HIGH: 514 int_type &= ~BIT(bank_pin_num); 515 int_pol |= BIT(bank_pin_num); 516 break; 517 case IRQ_TYPE_LEVEL_LOW: 518 int_type &= ~BIT(bank_pin_num); 519 int_pol &= ~BIT(bank_pin_num); 520 break; 521 default: 522 return -EINVAL; 523 } 524 525 writel_relaxed(int_type, 526 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); 527 writel_relaxed(int_pol, 528 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); 529 writel_relaxed(int_any, 530 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num)); 531 532 if (type & IRQ_TYPE_LEVEL_MASK) 533 irq_set_chip_handler_name_locked(irq_data, 534 &zynq_gpio_level_irqchip, 535 handle_fasteoi_irq, NULL); 536 else 537 irq_set_chip_handler_name_locked(irq_data, 538 &zynq_gpio_edge_irqchip, 539 handle_level_irq, NULL); 540 541 return 0; 542 } 543 544 static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on) 545 { 546 struct zynq_gpio *gpio = 547 gpiochip_get_data(irq_data_get_irq_chip_data(data)); 548 549 irq_set_irq_wake(gpio->irq, on); 550 551 return 0; 552 } 553 554 static int zynq_gpio_irq_reqres(struct irq_data *d) 555 { 556 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 557 int ret; 558 559 ret = pm_runtime_get_sync(chip->parent); 560 if (ret < 0) 561 return ret; 562 563 return gpiochip_reqres_irq(chip, d->hwirq); 564 } 565 566 static void zynq_gpio_irq_relres(struct irq_data *d) 567 { 568 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 569 570 gpiochip_relres_irq(chip, d->hwirq); 571 pm_runtime_put(chip->parent); 572 } 573 574 /* irq chip descriptor */ 575 static struct irq_chip zynq_gpio_level_irqchip = { 576 .name = DRIVER_NAME, 577 .irq_enable = zynq_gpio_irq_enable, 578 .irq_eoi = zynq_gpio_irq_ack, 579 .irq_mask = zynq_gpio_irq_mask, 580 .irq_unmask = zynq_gpio_irq_unmask, 581 .irq_set_type = zynq_gpio_set_irq_type, 582 .irq_set_wake = zynq_gpio_set_wake, 583 .irq_request_resources = zynq_gpio_irq_reqres, 584 .irq_release_resources = zynq_gpio_irq_relres, 585 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED | 586 IRQCHIP_MASK_ON_SUSPEND, 587 }; 588 589 static struct irq_chip zynq_gpio_edge_irqchip = { 590 .name = DRIVER_NAME, 591 .irq_enable = zynq_gpio_irq_enable, 592 .irq_ack = zynq_gpio_irq_ack, 593 .irq_mask = zynq_gpio_irq_mask, 594 .irq_unmask = zynq_gpio_irq_unmask, 595 .irq_set_type = zynq_gpio_set_irq_type, 596 .irq_set_wake = zynq_gpio_set_wake, 597 .irq_request_resources = zynq_gpio_irq_reqres, 598 .irq_release_resources = zynq_gpio_irq_relres, 599 .flags = IRQCHIP_MASK_ON_SUSPEND, 600 }; 601 602 static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio, 603 unsigned int bank_num, 604 unsigned long pending) 605 { 606 unsigned int bank_offset = gpio->p_data->bank_min[bank_num]; 607 struct irq_domain *irqdomain = gpio->chip.irq.domain; 608 int offset; 609 610 if (!pending) 611 return; 612 613 for_each_set_bit(offset, &pending, 32) { 614 unsigned int gpio_irq; 615 616 gpio_irq = irq_find_mapping(irqdomain, offset + bank_offset); 617 generic_handle_irq(gpio_irq); 618 } 619 } 620 621 /** 622 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device 623 * @desc: irq descriptor instance of the 'irq' 624 * 625 * This function reads the Interrupt Status Register of each bank to get the 626 * gpio pin number which has triggered an interrupt. It then acks the triggered 627 * interrupt and calls the pin specific handler set by the higher layer 628 * application for that pin. 629 * Note: A bug is reported if no handler is set for the gpio pin. 630 */ 631 static void zynq_gpio_irqhandler(struct irq_desc *desc) 632 { 633 u32 int_sts, int_enb; 634 unsigned int bank_num; 635 struct zynq_gpio *gpio = 636 gpiochip_get_data(irq_desc_get_handler_data(desc)); 637 struct irq_chip *irqchip = irq_desc_get_chip(desc); 638 639 chained_irq_enter(irqchip, desc); 640 641 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { 642 int_sts = readl_relaxed(gpio->base_addr + 643 ZYNQ_GPIO_INTSTS_OFFSET(bank_num)); 644 int_enb = readl_relaxed(gpio->base_addr + 645 ZYNQ_GPIO_INTMASK_OFFSET(bank_num)); 646 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb); 647 } 648 649 chained_irq_exit(irqchip, desc); 650 } 651 652 static void zynq_gpio_save_context(struct zynq_gpio *gpio) 653 { 654 unsigned int bank_num; 655 656 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { 657 gpio->context.datalsw[bank_num] = 658 readl_relaxed(gpio->base_addr + 659 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num)); 660 gpio->context.datamsw[bank_num] = 661 readl_relaxed(gpio->base_addr + 662 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num)); 663 gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr + 664 ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 665 gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr + 666 ZYNQ_GPIO_INTMASK_OFFSET(bank_num)); 667 gpio->context.int_type[bank_num] = 668 readl_relaxed(gpio->base_addr + 669 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); 670 gpio->context.int_polarity[bank_num] = 671 readl_relaxed(gpio->base_addr + 672 ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); 673 gpio->context.int_any[bank_num] = 674 readl_relaxed(gpio->base_addr + 675 ZYNQ_GPIO_INTANY_OFFSET(bank_num)); 676 } 677 } 678 679 static void zynq_gpio_restore_context(struct zynq_gpio *gpio) 680 { 681 unsigned int bank_num; 682 683 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { 684 writel_relaxed(gpio->context.datalsw[bank_num], 685 gpio->base_addr + 686 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num)); 687 writel_relaxed(gpio->context.datamsw[bank_num], 688 gpio->base_addr + 689 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num)); 690 writel_relaxed(gpio->context.dirm[bank_num], 691 gpio->base_addr + 692 ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 693 writel_relaxed(gpio->context.int_en[bank_num], 694 gpio->base_addr + 695 ZYNQ_GPIO_INTEN_OFFSET(bank_num)); 696 writel_relaxed(gpio->context.int_type[bank_num], 697 gpio->base_addr + 698 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); 699 writel_relaxed(gpio->context.int_polarity[bank_num], 700 gpio->base_addr + 701 ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); 702 writel_relaxed(gpio->context.int_any[bank_num], 703 gpio->base_addr + 704 ZYNQ_GPIO_INTANY_OFFSET(bank_num)); 705 } 706 } 707 708 static int __maybe_unused zynq_gpio_suspend(struct device *dev) 709 { 710 struct zynq_gpio *gpio = dev_get_drvdata(dev); 711 struct irq_data *data = irq_get_irq_data(gpio->irq); 712 713 if (!irqd_is_wakeup_set(data)) { 714 zynq_gpio_save_context(gpio); 715 return pm_runtime_force_suspend(dev); 716 } 717 718 return 0; 719 } 720 721 static int __maybe_unused zynq_gpio_resume(struct device *dev) 722 { 723 struct zynq_gpio *gpio = dev_get_drvdata(dev); 724 struct irq_data *data = irq_get_irq_data(gpio->irq); 725 int ret; 726 727 if (!irqd_is_wakeup_set(data)) { 728 ret = pm_runtime_force_resume(dev); 729 zynq_gpio_restore_context(gpio); 730 return ret; 731 } 732 733 return 0; 734 } 735 736 static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev) 737 { 738 struct zynq_gpio *gpio = dev_get_drvdata(dev); 739 740 clk_disable_unprepare(gpio->clk); 741 742 return 0; 743 } 744 745 static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev) 746 { 747 struct zynq_gpio *gpio = dev_get_drvdata(dev); 748 749 return clk_prepare_enable(gpio->clk); 750 } 751 752 static int zynq_gpio_request(struct gpio_chip *chip, unsigned int offset) 753 { 754 int ret; 755 756 ret = pm_runtime_get_sync(chip->parent); 757 758 /* 759 * If the device is already active pm_runtime_get() will return 1 on 760 * success, but gpio_request still needs to return 0. 761 */ 762 return ret < 0 ? ret : 0; 763 } 764 765 static void zynq_gpio_free(struct gpio_chip *chip, unsigned int offset) 766 { 767 pm_runtime_put(chip->parent); 768 } 769 770 static const struct dev_pm_ops zynq_gpio_dev_pm_ops = { 771 SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume) 772 SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend, 773 zynq_gpio_runtime_resume, NULL) 774 }; 775 776 static const struct zynq_platform_data zynqmp_gpio_def = { 777 .label = "zynqmp_gpio", 778 .quirks = GPIO_QUIRK_DATA_RO_BUG, 779 .ngpio = ZYNQMP_GPIO_NR_GPIOS, 780 .max_bank = ZYNQMP_GPIO_MAX_BANK, 781 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP), 782 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP), 783 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP), 784 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP), 785 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP), 786 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP), 787 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP), 788 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP), 789 .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP), 790 .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP), 791 .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP), 792 .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP), 793 }; 794 795 static const struct zynq_platform_data zynq_gpio_def = { 796 .label = "zynq_gpio", 797 .quirks = ZYNQ_GPIO_QUIRK_IS_ZYNQ | GPIO_QUIRK_DATA_RO_BUG, 798 .ngpio = ZYNQ_GPIO_NR_GPIOS, 799 .max_bank = ZYNQ_GPIO_MAX_BANK, 800 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(), 801 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(), 802 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(), 803 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(), 804 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(), 805 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(), 806 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(), 807 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(), 808 }; 809 810 static const struct of_device_id zynq_gpio_of_match[] = { 811 { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def }, 812 { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def }, 813 { /* end of table */ } 814 }; 815 MODULE_DEVICE_TABLE(of, zynq_gpio_of_match); 816 817 /** 818 * zynq_gpio_probe - Initialization method for a zynq_gpio device 819 * @pdev: platform device instance 820 * 821 * This function allocates memory resources for the gpio device and registers 822 * all the banks of the device. It will also set up interrupts for the gpio 823 * pins. 824 * Note: Interrupts are disabled for all the banks during initialization. 825 * 826 * Return: 0 on success, negative error otherwise. 827 */ 828 static int zynq_gpio_probe(struct platform_device *pdev) 829 { 830 int ret, bank_num; 831 struct zynq_gpio *gpio; 832 struct gpio_chip *chip; 833 struct gpio_irq_chip *girq; 834 const struct of_device_id *match; 835 836 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 837 if (!gpio) 838 return -ENOMEM; 839 840 match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node); 841 if (!match) { 842 dev_err(&pdev->dev, "of_match_node() failed\n"); 843 return -EINVAL; 844 } 845 gpio->p_data = match->data; 846 platform_set_drvdata(pdev, gpio); 847 848 gpio->base_addr = devm_platform_ioremap_resource(pdev, 0); 849 if (IS_ERR(gpio->base_addr)) 850 return PTR_ERR(gpio->base_addr); 851 852 gpio->irq = platform_get_irq(pdev, 0); 853 if (gpio->irq < 0) 854 return gpio->irq; 855 856 /* configure the gpio chip */ 857 chip = &gpio->chip; 858 chip->label = gpio->p_data->label; 859 chip->owner = THIS_MODULE; 860 chip->parent = &pdev->dev; 861 chip->get = zynq_gpio_get_value; 862 chip->set = zynq_gpio_set_value; 863 chip->request = zynq_gpio_request; 864 chip->free = zynq_gpio_free; 865 chip->direction_input = zynq_gpio_dir_in; 866 chip->direction_output = zynq_gpio_dir_out; 867 chip->get_direction = zynq_gpio_get_direction; 868 chip->base = of_alias_get_id(pdev->dev.of_node, "gpio"); 869 chip->ngpio = gpio->p_data->ngpio; 870 871 /* Retrieve GPIO clock */ 872 gpio->clk = devm_clk_get(&pdev->dev, NULL); 873 if (IS_ERR(gpio->clk)) { 874 dev_err(&pdev->dev, "input clock not found.\n"); 875 return PTR_ERR(gpio->clk); 876 } 877 ret = clk_prepare_enable(gpio->clk); 878 if (ret) { 879 dev_err(&pdev->dev, "Unable to enable clock.\n"); 880 return ret; 881 } 882 883 pm_runtime_set_active(&pdev->dev); 884 pm_runtime_enable(&pdev->dev); 885 ret = pm_runtime_get_sync(&pdev->dev); 886 if (ret < 0) 887 goto err_pm_dis; 888 889 /* disable interrupts for all banks */ 890 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) 891 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr + 892 ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); 893 894 /* Set up the GPIO irqchip */ 895 girq = &chip->irq; 896 girq->chip = &zynq_gpio_edge_irqchip; 897 girq->parent_handler = zynq_gpio_irqhandler; 898 girq->num_parents = 1; 899 girq->parents = devm_kcalloc(&pdev->dev, 1, 900 sizeof(*girq->parents), 901 GFP_KERNEL); 902 if (!girq->parents) { 903 ret = -ENOMEM; 904 goto err_pm_put; 905 } 906 girq->parents[0] = gpio->irq; 907 girq->default_type = IRQ_TYPE_NONE; 908 girq->handler = handle_level_irq; 909 910 /* report a bug if gpio chip registration fails */ 911 ret = gpiochip_add_data(chip, gpio); 912 if (ret) { 913 dev_err(&pdev->dev, "Failed to add gpio chip\n"); 914 goto err_pm_put; 915 } 916 917 pm_runtime_put(&pdev->dev); 918 919 return 0; 920 921 err_pm_put: 922 pm_runtime_put(&pdev->dev); 923 err_pm_dis: 924 pm_runtime_disable(&pdev->dev); 925 clk_disable_unprepare(gpio->clk); 926 927 return ret; 928 } 929 930 /** 931 * zynq_gpio_remove - Driver removal function 932 * @pdev: platform device instance 933 * 934 * Return: 0 always 935 */ 936 static int zynq_gpio_remove(struct platform_device *pdev) 937 { 938 struct zynq_gpio *gpio = platform_get_drvdata(pdev); 939 940 pm_runtime_get_sync(&pdev->dev); 941 gpiochip_remove(&gpio->chip); 942 clk_disable_unprepare(gpio->clk); 943 device_set_wakeup_capable(&pdev->dev, 0); 944 pm_runtime_disable(&pdev->dev); 945 return 0; 946 } 947 948 static struct platform_driver zynq_gpio_driver = { 949 .driver = { 950 .name = DRIVER_NAME, 951 .pm = &zynq_gpio_dev_pm_ops, 952 .of_match_table = zynq_gpio_of_match, 953 }, 954 .probe = zynq_gpio_probe, 955 .remove = zynq_gpio_remove, 956 }; 957 958 /** 959 * zynq_gpio_init - Initial driver registration call 960 * 961 * Return: value from platform_driver_register 962 */ 963 static int __init zynq_gpio_init(void) 964 { 965 return platform_driver_register(&zynq_gpio_driver); 966 } 967 postcore_initcall(zynq_gpio_init); 968 969 static void __exit zynq_gpio_exit(void) 970 { 971 platform_driver_unregister(&zynq_gpio_driver); 972 } 973 module_exit(zynq_gpio_exit); 974 975 MODULE_AUTHOR("Xilinx Inc."); 976 MODULE_DESCRIPTION("Zynq GPIO driver"); 977 MODULE_LICENSE("GPL"); 978