1 /* 2 * Copyright (C) 2013 TangoTec Ltd. 3 * Author: Baruch Siach <baruch@tkos.co.il> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * Driver for the Xtensa LX4 GPIO32 Option 10 * 11 * Documentation: Xtensa LX4 Microprocessor Data Book, Section 2.22 12 * 13 * GPIO32 is a standard optional extension to the Xtensa architecture core that 14 * provides preconfigured output and input ports for intra SoC signaling. The 15 * GPIO32 option is implemented as 32bit Tensilica Instruction Extension (TIE) 16 * output state called EXPSTATE, and 32bit input wire called IMPWIRE. This 17 * driver treats input and output states as two distinct devices. 18 * 19 * Access to GPIO32 specific instructions is controlled by the CPENABLE 20 * (Coprocessor Enable Bits) register. By default Xtensa Linux startup code 21 * disables access to all coprocessors. This driver sets the CPENABLE bit 22 * corresponding to GPIO32 before any GPIO32 specific instruction, and restores 23 * CPENABLE state after that. 24 * 25 * This driver is currently incompatible with SMP. The GPIO32 extension is not 26 * guaranteed to be available in all cores. Moreover, each core controls a 27 * different set of IO wires. A theoretical SMP aware version of this driver 28 * would need to have a per core workqueue to do the actual GPIO manipulation. 29 */ 30 31 #include <linux/err.h> 32 #include <linux/module.h> 33 #include <linux/gpio.h> 34 #include <linux/bitops.h> 35 #include <linux/platform_device.h> 36 37 #include <asm/coprocessor.h> /* CPENABLE read/write macros */ 38 39 #ifndef XCHAL_CP_ID_XTIOP 40 #error GPIO32 option is not enabled for your xtensa core variant 41 #endif 42 43 #if XCHAL_HAVE_CP 44 45 static inline unsigned long enable_cp(unsigned long *cpenable) 46 { 47 unsigned long flags; 48 49 local_irq_save(flags); 50 RSR_CPENABLE(*cpenable); 51 WSR_CPENABLE(*cpenable | BIT(XCHAL_CP_ID_XTIOP)); 52 53 return flags; 54 } 55 56 static inline void disable_cp(unsigned long flags, unsigned long cpenable) 57 { 58 WSR_CPENABLE(cpenable); 59 local_irq_restore(flags); 60 } 61 62 #else 63 64 static inline unsigned long enable_cp(unsigned long *cpenable) 65 { 66 *cpenable = 0; /* avoid uninitialized value warning */ 67 return 0; 68 } 69 70 static inline void disable_cp(unsigned long flags, unsigned long cpenable) 71 { 72 } 73 74 #endif /* XCHAL_HAVE_CP */ 75 76 static int xtensa_impwire_get_direction(struct gpio_chip *gc, unsigned offset) 77 { 78 return 1; /* input only */ 79 } 80 81 static int xtensa_impwire_get_value(struct gpio_chip *gc, unsigned offset) 82 { 83 unsigned long flags, saved_cpenable; 84 u32 impwire; 85 86 flags = enable_cp(&saved_cpenable); 87 __asm__ __volatile__("read_impwire %0" : "=a" (impwire)); 88 disable_cp(flags, saved_cpenable); 89 90 return !!(impwire & BIT(offset)); 91 } 92 93 static void xtensa_impwire_set_value(struct gpio_chip *gc, unsigned offset, 94 int value) 95 { 96 BUG(); /* output only; should never be called */ 97 } 98 99 static int xtensa_expstate_get_direction(struct gpio_chip *gc, unsigned offset) 100 { 101 return 0; /* output only */ 102 } 103 104 static int xtensa_expstate_get_value(struct gpio_chip *gc, unsigned offset) 105 { 106 unsigned long flags, saved_cpenable; 107 u32 expstate; 108 109 flags = enable_cp(&saved_cpenable); 110 __asm__ __volatile__("rur.expstate %0" : "=a" (expstate)); 111 disable_cp(flags, saved_cpenable); 112 113 return !!(expstate & BIT(offset)); 114 } 115 116 static void xtensa_expstate_set_value(struct gpio_chip *gc, unsigned offset, 117 int value) 118 { 119 unsigned long flags, saved_cpenable; 120 u32 mask = BIT(offset); 121 u32 val = value ? BIT(offset) : 0; 122 123 flags = enable_cp(&saved_cpenable); 124 __asm__ __volatile__("wrmsk_expstate %0, %1" 125 :: "a" (val), "a" (mask)); 126 disable_cp(flags, saved_cpenable); 127 } 128 129 static struct gpio_chip impwire_chip = { 130 .label = "impwire", 131 .base = -1, 132 .ngpio = 32, 133 .get_direction = xtensa_impwire_get_direction, 134 .get = xtensa_impwire_get_value, 135 .set = xtensa_impwire_set_value, 136 }; 137 138 static struct gpio_chip expstate_chip = { 139 .label = "expstate", 140 .base = -1, 141 .ngpio = 32, 142 .get_direction = xtensa_expstate_get_direction, 143 .get = xtensa_expstate_get_value, 144 .set = xtensa_expstate_set_value, 145 }; 146 147 static int xtensa_gpio_probe(struct platform_device *pdev) 148 { 149 int ret; 150 151 ret = gpiochip_add(&impwire_chip); 152 if (ret) 153 return ret; 154 return gpiochip_add(&expstate_chip); 155 } 156 157 static struct platform_driver xtensa_gpio_driver = { 158 .driver = { 159 .name = "xtensa-gpio", 160 }, 161 .probe = xtensa_gpio_probe, 162 }; 163 164 static int __init xtensa_gpio_init(void) 165 { 166 struct platform_device *pdev; 167 168 pdev = platform_device_register_simple("xtensa-gpio", 0, NULL, 0); 169 if (IS_ERR(pdev)) 170 return PTR_ERR(pdev); 171 172 return platform_driver_register(&xtensa_gpio_driver); 173 } 174 device_initcall(xtensa_gpio_init); 175 176 MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>"); 177 MODULE_DESCRIPTION("Xtensa LX4 GPIO32 driver"); 178 MODULE_LICENSE("GPL"); 179