1 /* 2 * Copyright (C) 2003-2015 Broadcom Corporation 3 * All Rights Reserved 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/gpio/driver.h> 16 #include <linux/platform_device.h> 17 #include <linux/of_device.h> 18 #include <linux/module.h> 19 #include <linux/irq.h> 20 #include <linux/interrupt.h> 21 #include <linux/irqchip/chained_irq.h> 22 #include <linux/acpi.h> 23 24 /* 25 * XLP GPIO has multiple 32 bit registers for each feature where each register 26 * controls 32 pins. So, pins up to 64 require 2 32-bit registers and up to 96 27 * require 3 32-bit registers for each feature. 28 * Here we only define offset of the first register for each feature. Offset of 29 * the registers for pins greater than 32 can be calculated as following(Use 30 * GPIO_INT_STAT as example): 31 * 32 * offset = (gpio / XLP_GPIO_REGSZ) * 4; 33 * reg_addr = addr + offset; 34 * 35 * where addr is base address of the that feature register and gpio is the pin. 36 */ 37 #define GPIO_OUTPUT_EN 0x00 38 #define GPIO_PADDRV 0x08 39 #define GPIO_INT_EN00 0x18 40 #define GPIO_INT_EN10 0x20 41 #define GPIO_INT_EN20 0x28 42 #define GPIO_INT_EN30 0x30 43 #define GPIO_INT_POL 0x38 44 #define GPIO_INT_TYPE 0x40 45 #define GPIO_INT_STAT 0x48 46 47 #define GPIO_9XX_BYTESWAP 0X00 48 #define GPIO_9XX_CTRL 0X04 49 #define GPIO_9XX_OUTPUT_EN 0x14 50 #define GPIO_9XX_PADDRV 0x24 51 /* 52 * Only for 4 interrupt enable reg are defined for now, 53 * total reg available are 12. 54 */ 55 #define GPIO_9XX_INT_EN00 0x44 56 #define GPIO_9XX_INT_EN10 0x54 57 #define GPIO_9XX_INT_EN20 0x64 58 #define GPIO_9XX_INT_EN30 0x74 59 #define GPIO_9XX_INT_POL 0x104 60 #define GPIO_9XX_INT_TYPE 0x114 61 #define GPIO_9XX_INT_STAT 0x124 62 63 #define GPIO_3XX_INT_EN00 0x18 64 #define GPIO_3XX_INT_EN10 0x20 65 #define GPIO_3XX_INT_EN20 0x28 66 #define GPIO_3XX_INT_EN30 0x30 67 #define GPIO_3XX_INT_POL 0x78 68 #define GPIO_3XX_INT_TYPE 0x80 69 #define GPIO_3XX_INT_STAT 0x88 70 71 /* Interrupt type register mask */ 72 #define XLP_GPIO_IRQ_TYPE_LVL 0x0 73 #define XLP_GPIO_IRQ_TYPE_EDGE 0x1 74 75 /* Interrupt polarity register mask */ 76 #define XLP_GPIO_IRQ_POL_HIGH 0x0 77 #define XLP_GPIO_IRQ_POL_LOW 0x1 78 79 #define XLP_GPIO_REGSZ 32 80 #define XLP_GPIO_IRQ_BASE 768 81 #define XLP_MAX_NR_GPIO 96 82 83 /* XLP variants supported by this driver */ 84 enum { 85 XLP_GPIO_VARIANT_XLP832 = 1, 86 XLP_GPIO_VARIANT_XLP316, 87 XLP_GPIO_VARIANT_XLP208, 88 XLP_GPIO_VARIANT_XLP980, 89 XLP_GPIO_VARIANT_XLP532, 90 GPIO_VARIANT_VULCAN 91 }; 92 93 struct xlp_gpio_priv { 94 struct gpio_chip chip; 95 DECLARE_BITMAP(gpio_enabled_mask, XLP_MAX_NR_GPIO); 96 void __iomem *gpio_intr_en; /* pointer to first intr enable reg */ 97 void __iomem *gpio_intr_stat; /* pointer to first intr status reg */ 98 void __iomem *gpio_intr_type; /* pointer to first intr type reg */ 99 void __iomem *gpio_intr_pol; /* pointer to first intr polarity reg */ 100 void __iomem *gpio_out_en; /* pointer to first output enable reg */ 101 void __iomem *gpio_paddrv; /* pointer to first pad drive reg */ 102 spinlock_t lock; 103 }; 104 105 static int xlp_gpio_get_reg(void __iomem *addr, unsigned gpio) 106 { 107 u32 pos, regset; 108 109 pos = gpio % XLP_GPIO_REGSZ; 110 regset = (gpio / XLP_GPIO_REGSZ) * 4; 111 return !!(readl(addr + regset) & BIT(pos)); 112 } 113 114 static void xlp_gpio_set_reg(void __iomem *addr, unsigned gpio, int state) 115 { 116 u32 value, pos, regset; 117 118 pos = gpio % XLP_GPIO_REGSZ; 119 regset = (gpio / XLP_GPIO_REGSZ) * 4; 120 value = readl(addr + regset); 121 122 if (state) 123 value |= BIT(pos); 124 else 125 value &= ~BIT(pos); 126 127 writel(value, addr + regset); 128 } 129 130 static void xlp_gpio_irq_disable(struct irq_data *d) 131 { 132 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 133 struct xlp_gpio_priv *priv = gpiochip_get_data(gc); 134 unsigned long flags; 135 136 spin_lock_irqsave(&priv->lock, flags); 137 xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0); 138 __clear_bit(d->hwirq, priv->gpio_enabled_mask); 139 spin_unlock_irqrestore(&priv->lock, flags); 140 } 141 142 static void xlp_gpio_irq_mask_ack(struct irq_data *d) 143 { 144 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 145 struct xlp_gpio_priv *priv = gpiochip_get_data(gc); 146 unsigned long flags; 147 148 spin_lock_irqsave(&priv->lock, flags); 149 xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0); 150 xlp_gpio_set_reg(priv->gpio_intr_stat, d->hwirq, 0x1); 151 __clear_bit(d->hwirq, priv->gpio_enabled_mask); 152 spin_unlock_irqrestore(&priv->lock, flags); 153 } 154 155 static void xlp_gpio_irq_unmask(struct irq_data *d) 156 { 157 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 158 struct xlp_gpio_priv *priv = gpiochip_get_data(gc); 159 unsigned long flags; 160 161 spin_lock_irqsave(&priv->lock, flags); 162 xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x1); 163 __set_bit(d->hwirq, priv->gpio_enabled_mask); 164 spin_unlock_irqrestore(&priv->lock, flags); 165 } 166 167 static int xlp_gpio_set_irq_type(struct irq_data *d, unsigned int type) 168 { 169 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 170 struct xlp_gpio_priv *priv = gpiochip_get_data(gc); 171 int pol, irq_type; 172 173 switch (type) { 174 case IRQ_TYPE_EDGE_RISING: 175 irq_type = XLP_GPIO_IRQ_TYPE_EDGE; 176 pol = XLP_GPIO_IRQ_POL_HIGH; 177 break; 178 case IRQ_TYPE_EDGE_FALLING: 179 irq_type = XLP_GPIO_IRQ_TYPE_EDGE; 180 pol = XLP_GPIO_IRQ_POL_LOW; 181 break; 182 case IRQ_TYPE_LEVEL_HIGH: 183 irq_type = XLP_GPIO_IRQ_TYPE_LVL; 184 pol = XLP_GPIO_IRQ_POL_HIGH; 185 break; 186 case IRQ_TYPE_LEVEL_LOW: 187 irq_type = XLP_GPIO_IRQ_TYPE_LVL; 188 pol = XLP_GPIO_IRQ_POL_LOW; 189 break; 190 default: 191 return -EINVAL; 192 } 193 194 xlp_gpio_set_reg(priv->gpio_intr_type, d->hwirq, irq_type); 195 xlp_gpio_set_reg(priv->gpio_intr_pol, d->hwirq, pol); 196 197 return 0; 198 } 199 200 static struct irq_chip xlp_gpio_irq_chip = { 201 .name = "XLP-GPIO", 202 .irq_mask_ack = xlp_gpio_irq_mask_ack, 203 .irq_disable = xlp_gpio_irq_disable, 204 .irq_set_type = xlp_gpio_set_irq_type, 205 .irq_unmask = xlp_gpio_irq_unmask, 206 .flags = IRQCHIP_ONESHOT_SAFE, 207 }; 208 209 static void xlp_gpio_generic_handler(struct irq_desc *desc) 210 { 211 struct xlp_gpio_priv *priv = irq_desc_get_handler_data(desc); 212 struct irq_chip *irqchip = irq_desc_get_chip(desc); 213 int gpio, regoff; 214 u32 gpio_stat; 215 216 regoff = -1; 217 gpio_stat = 0; 218 219 chained_irq_enter(irqchip, desc); 220 for_each_set_bit(gpio, priv->gpio_enabled_mask, XLP_MAX_NR_GPIO) { 221 if (regoff != gpio / XLP_GPIO_REGSZ) { 222 regoff = gpio / XLP_GPIO_REGSZ; 223 gpio_stat = readl(priv->gpio_intr_stat + regoff * 4); 224 } 225 226 if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ)) 227 generic_handle_irq(irq_find_mapping( 228 priv->chip.irq.domain, gpio)); 229 } 230 chained_irq_exit(irqchip, desc); 231 } 232 233 static int xlp_gpio_dir_output(struct gpio_chip *gc, unsigned gpio, int state) 234 { 235 struct xlp_gpio_priv *priv = gpiochip_get_data(gc); 236 237 BUG_ON(gpio >= gc->ngpio); 238 xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x1); 239 240 return 0; 241 } 242 243 static int xlp_gpio_dir_input(struct gpio_chip *gc, unsigned gpio) 244 { 245 struct xlp_gpio_priv *priv = gpiochip_get_data(gc); 246 247 BUG_ON(gpio >= gc->ngpio); 248 xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x0); 249 250 return 0; 251 } 252 253 static int xlp_gpio_get(struct gpio_chip *gc, unsigned gpio) 254 { 255 struct xlp_gpio_priv *priv = gpiochip_get_data(gc); 256 257 BUG_ON(gpio >= gc->ngpio); 258 return xlp_gpio_get_reg(priv->gpio_paddrv, gpio); 259 } 260 261 static void xlp_gpio_set(struct gpio_chip *gc, unsigned gpio, int state) 262 { 263 struct xlp_gpio_priv *priv = gpiochip_get_data(gc); 264 265 BUG_ON(gpio >= gc->ngpio); 266 xlp_gpio_set_reg(priv->gpio_paddrv, gpio, state); 267 } 268 269 static const struct of_device_id xlp_gpio_of_ids[] = { 270 { 271 .compatible = "netlogic,xlp832-gpio", 272 .data = (void *)XLP_GPIO_VARIANT_XLP832, 273 }, 274 { 275 .compatible = "netlogic,xlp316-gpio", 276 .data = (void *)XLP_GPIO_VARIANT_XLP316, 277 }, 278 { 279 .compatible = "netlogic,xlp208-gpio", 280 .data = (void *)XLP_GPIO_VARIANT_XLP208, 281 }, 282 { 283 .compatible = "netlogic,xlp980-gpio", 284 .data = (void *)XLP_GPIO_VARIANT_XLP980, 285 }, 286 { 287 .compatible = "netlogic,xlp532-gpio", 288 .data = (void *)XLP_GPIO_VARIANT_XLP532, 289 }, 290 { 291 .compatible = "brcm,vulcan-gpio", 292 .data = (void *)GPIO_VARIANT_VULCAN, 293 }, 294 { /* sentinel */ }, 295 }; 296 MODULE_DEVICE_TABLE(of, xlp_gpio_of_ids); 297 298 static int xlp_gpio_probe(struct platform_device *pdev) 299 { 300 struct gpio_chip *gc; 301 struct resource *iores; 302 struct xlp_gpio_priv *priv; 303 void __iomem *gpio_base; 304 int irq_base, irq, err; 305 int ngpio; 306 u32 soc_type; 307 308 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 309 if (!iores) 310 return -ENODEV; 311 312 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 313 if (!priv) 314 return -ENOMEM; 315 316 gpio_base = devm_ioremap_resource(&pdev->dev, iores); 317 if (IS_ERR(gpio_base)) 318 return PTR_ERR(gpio_base); 319 320 irq = platform_get_irq(pdev, 0); 321 if (irq < 0) 322 return irq; 323 324 if (pdev->dev.of_node) { 325 soc_type = (uintptr_t)of_device_get_match_data(&pdev->dev); 326 } else { 327 const struct acpi_device_id *acpi_id; 328 329 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table, 330 &pdev->dev); 331 if (!acpi_id || !acpi_id->driver_data) { 332 dev_err(&pdev->dev, "Unable to match ACPI ID\n"); 333 return -ENODEV; 334 } 335 soc_type = (uintptr_t) acpi_id->driver_data; 336 } 337 338 switch (soc_type) { 339 case XLP_GPIO_VARIANT_XLP832: 340 priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN; 341 priv->gpio_paddrv = gpio_base + GPIO_PADDRV; 342 priv->gpio_intr_stat = gpio_base + GPIO_INT_STAT; 343 priv->gpio_intr_type = gpio_base + GPIO_INT_TYPE; 344 priv->gpio_intr_pol = gpio_base + GPIO_INT_POL; 345 priv->gpio_intr_en = gpio_base + GPIO_INT_EN00; 346 ngpio = 41; 347 break; 348 case XLP_GPIO_VARIANT_XLP208: 349 case XLP_GPIO_VARIANT_XLP316: 350 priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN; 351 priv->gpio_paddrv = gpio_base + GPIO_PADDRV; 352 priv->gpio_intr_stat = gpio_base + GPIO_3XX_INT_STAT; 353 priv->gpio_intr_type = gpio_base + GPIO_3XX_INT_TYPE; 354 priv->gpio_intr_pol = gpio_base + GPIO_3XX_INT_POL; 355 priv->gpio_intr_en = gpio_base + GPIO_3XX_INT_EN00; 356 357 ngpio = (soc_type == XLP_GPIO_VARIANT_XLP208) ? 42 : 57; 358 break; 359 case XLP_GPIO_VARIANT_XLP980: 360 case XLP_GPIO_VARIANT_XLP532: 361 case GPIO_VARIANT_VULCAN: 362 priv->gpio_out_en = gpio_base + GPIO_9XX_OUTPUT_EN; 363 priv->gpio_paddrv = gpio_base + GPIO_9XX_PADDRV; 364 priv->gpio_intr_stat = gpio_base + GPIO_9XX_INT_STAT; 365 priv->gpio_intr_type = gpio_base + GPIO_9XX_INT_TYPE; 366 priv->gpio_intr_pol = gpio_base + GPIO_9XX_INT_POL; 367 priv->gpio_intr_en = gpio_base + GPIO_9XX_INT_EN00; 368 369 if (soc_type == XLP_GPIO_VARIANT_XLP980) 370 ngpio = 66; 371 else if (soc_type == XLP_GPIO_VARIANT_XLP532) 372 ngpio = 67; 373 else 374 ngpio = 70; 375 break; 376 default: 377 dev_err(&pdev->dev, "Unknown Processor type!\n"); 378 return -ENODEV; 379 } 380 381 bitmap_zero(priv->gpio_enabled_mask, XLP_MAX_NR_GPIO); 382 383 gc = &priv->chip; 384 385 gc->owner = THIS_MODULE; 386 gc->label = dev_name(&pdev->dev); 387 gc->base = 0; 388 gc->parent = &pdev->dev; 389 gc->ngpio = ngpio; 390 gc->of_node = pdev->dev.of_node; 391 gc->direction_output = xlp_gpio_dir_output; 392 gc->direction_input = xlp_gpio_dir_input; 393 gc->set = xlp_gpio_set; 394 gc->get = xlp_gpio_get; 395 396 spin_lock_init(&priv->lock); 397 398 /* XLP(MIPS) has fixed range for GPIO IRQs, Vulcan(ARM64) does not */ 399 if (soc_type != GPIO_VARIANT_VULCAN) { 400 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 401 XLP_GPIO_IRQ_BASE, 402 gc->ngpio, 0); 403 if (irq_base < 0) { 404 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n"); 405 return irq_base; 406 } 407 } else { 408 irq_base = 0; 409 } 410 411 err = gpiochip_add_data(gc, priv); 412 if (err < 0) 413 return err; 414 415 err = gpiochip_irqchip_add(gc, &xlp_gpio_irq_chip, irq_base, 416 handle_level_irq, IRQ_TYPE_NONE); 417 if (err) { 418 dev_err(&pdev->dev, "Could not connect irqchip to gpiochip!\n"); 419 goto out_gpio_remove; 420 } 421 422 gpiochip_set_chained_irqchip(gc, &xlp_gpio_irq_chip, irq, 423 xlp_gpio_generic_handler); 424 425 dev_info(&pdev->dev, "registered %d GPIOs\n", gc->ngpio); 426 427 return 0; 428 429 out_gpio_remove: 430 gpiochip_remove(gc); 431 return err; 432 } 433 434 #ifdef CONFIG_ACPI 435 static const struct acpi_device_id xlp_gpio_acpi_match[] = { 436 { "BRCM9006", GPIO_VARIANT_VULCAN }, 437 { "CAV9006", GPIO_VARIANT_VULCAN }, 438 {}, 439 }; 440 MODULE_DEVICE_TABLE(acpi, xlp_gpio_acpi_match); 441 #endif 442 443 static struct platform_driver xlp_gpio_driver = { 444 .driver = { 445 .name = "xlp-gpio", 446 .of_match_table = xlp_gpio_of_ids, 447 .acpi_match_table = ACPI_PTR(xlp_gpio_acpi_match), 448 }, 449 .probe = xlp_gpio_probe, 450 }; 451 module_platform_driver(xlp_gpio_driver); 452 453 MODULE_AUTHOR("Kamlakant Patel <kamlakant.patel@broadcom.com>"); 454 MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>"); 455 MODULE_DESCRIPTION("Netlogic XLP GPIO Driver"); 456 MODULE_LICENSE("GPL v2"); 457