1ff718800SKamlakant Patel /* 2ff718800SKamlakant Patel * Copyright (C) 2003-2015 Broadcom Corporation 3ff718800SKamlakant Patel * All Rights Reserved 4ff718800SKamlakant Patel * 5ff718800SKamlakant Patel * This program is free software; you can redistribute it and/or modify 6ff718800SKamlakant Patel * it under the terms of the GNU General Public License version 2 as 7ff718800SKamlakant Patel * published by the Free Software Foundation. 8ff718800SKamlakant Patel * 9ff718800SKamlakant Patel * This program is distributed in the hope that it will be useful, 10ff718800SKamlakant Patel * but WITHOUT ANY WARRANTY; without even the implied warranty of 11ff718800SKamlakant Patel * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12ff718800SKamlakant Patel * GNU General Public License for more details. 13ff718800SKamlakant Patel */ 14ff718800SKamlakant Patel 15ff718800SKamlakant Patel #include <linux/gpio.h> 16ff718800SKamlakant Patel #include <linux/platform_device.h> 17ff718800SKamlakant Patel #include <linux/of_device.h> 18ff718800SKamlakant Patel #include <linux/module.h> 19ff718800SKamlakant Patel #include <linux/irq.h> 20ff718800SKamlakant Patel #include <linux/interrupt.h> 21ff718800SKamlakant Patel 22ff718800SKamlakant Patel /* 23ff718800SKamlakant Patel * XLP GPIO has multiple 32 bit registers for each feature where each register 24ff718800SKamlakant Patel * controls 32 pins. So, pins up to 64 require 2 32-bit registers and up to 96 25ff718800SKamlakant Patel * require 3 32-bit registers for each feature. 26ff718800SKamlakant Patel * Here we only define offset of the first register for each feature. Offset of 27ff718800SKamlakant Patel * the registers for pins greater than 32 can be calculated as following(Use 28ff718800SKamlakant Patel * GPIO_INT_STAT as example): 29ff718800SKamlakant Patel * 30ff718800SKamlakant Patel * offset = (gpio / XLP_GPIO_REGSZ) * 4; 31ff718800SKamlakant Patel * reg_addr = addr + offset; 32ff718800SKamlakant Patel * 33ff718800SKamlakant Patel * where addr is base address of the that feature register and gpio is the pin. 34ff718800SKamlakant Patel */ 35ff718800SKamlakant Patel #define GPIO_OUTPUT_EN 0x00 36ff718800SKamlakant Patel #define GPIO_PADDRV 0x08 37ff718800SKamlakant Patel #define GPIO_INT_EN00 0x18 38ff718800SKamlakant Patel #define GPIO_INT_EN10 0x20 39ff718800SKamlakant Patel #define GPIO_INT_EN20 0x28 40ff718800SKamlakant Patel #define GPIO_INT_EN30 0x30 41ff718800SKamlakant Patel #define GPIO_INT_POL 0x38 42ff718800SKamlakant Patel #define GPIO_INT_TYPE 0x40 43ff718800SKamlakant Patel #define GPIO_INT_STAT 0x48 44ff718800SKamlakant Patel 45ff718800SKamlakant Patel #define GPIO_9XX_BYTESWAP 0X00 46ff718800SKamlakant Patel #define GPIO_9XX_CTRL 0X04 47ff718800SKamlakant Patel #define GPIO_9XX_OUTPUT_EN 0x14 48ff718800SKamlakant Patel #define GPIO_9XX_PADDRV 0x24 49ff718800SKamlakant Patel /* 50ff718800SKamlakant Patel * Only for 4 interrupt enable reg are defined for now, 51ff718800SKamlakant Patel * total reg available are 12. 52ff718800SKamlakant Patel */ 53ff718800SKamlakant Patel #define GPIO_9XX_INT_EN00 0x44 54ff718800SKamlakant Patel #define GPIO_9XX_INT_EN10 0x54 55ff718800SKamlakant Patel #define GPIO_9XX_INT_EN20 0x64 56ff718800SKamlakant Patel #define GPIO_9XX_INT_EN30 0x74 57ff718800SKamlakant Patel #define GPIO_9XX_INT_POL 0x104 58ff718800SKamlakant Patel #define GPIO_9XX_INT_TYPE 0x114 59ff718800SKamlakant Patel #define GPIO_9XX_INT_STAT 0x124 60ff718800SKamlakant Patel 61ff718800SKamlakant Patel #define GPIO_3XX_INT_EN00 0x18 62ff718800SKamlakant Patel #define GPIO_3XX_INT_EN10 0x20 63ff718800SKamlakant Patel #define GPIO_3XX_INT_EN20 0x28 64ff718800SKamlakant Patel #define GPIO_3XX_INT_EN30 0x30 65ff718800SKamlakant Patel #define GPIO_3XX_INT_POL 0x78 66ff718800SKamlakant Patel #define GPIO_3XX_INT_TYPE 0x80 67ff718800SKamlakant Patel #define GPIO_3XX_INT_STAT 0x88 68ff718800SKamlakant Patel 69ff718800SKamlakant Patel /* Interrupt type register mask */ 70ff718800SKamlakant Patel #define XLP_GPIO_IRQ_TYPE_LVL 0x0 71ff718800SKamlakant Patel #define XLP_GPIO_IRQ_TYPE_EDGE 0x1 72ff718800SKamlakant Patel 73ff718800SKamlakant Patel /* Interrupt polarity register mask */ 74ff718800SKamlakant Patel #define XLP_GPIO_IRQ_POL_HIGH 0x0 75ff718800SKamlakant Patel #define XLP_GPIO_IRQ_POL_LOW 0x1 76ff718800SKamlakant Patel 77ff718800SKamlakant Patel #define XLP_GPIO_REGSZ 32 78ff718800SKamlakant Patel #define XLP_GPIO_IRQ_BASE 768 79ff718800SKamlakant Patel #define XLP_MAX_NR_GPIO 96 80ff718800SKamlakant Patel 81ff718800SKamlakant Patel /* XLP variants supported by this driver */ 82ff718800SKamlakant Patel enum { 83ff718800SKamlakant Patel XLP_GPIO_VARIANT_XLP832 = 1, 84ff718800SKamlakant Patel XLP_GPIO_VARIANT_XLP316, 85ff718800SKamlakant Patel XLP_GPIO_VARIANT_XLP208, 86ff718800SKamlakant Patel XLP_GPIO_VARIANT_XLP980, 87ff718800SKamlakant Patel XLP_GPIO_VARIANT_XLP532 88ff718800SKamlakant Patel }; 89ff718800SKamlakant Patel 90ff718800SKamlakant Patel struct xlp_gpio_priv { 91ff718800SKamlakant Patel struct gpio_chip chip; 92ff718800SKamlakant Patel DECLARE_BITMAP(gpio_enabled_mask, XLP_MAX_NR_GPIO); 93ff718800SKamlakant Patel void __iomem *gpio_intr_en; /* pointer to first intr enable reg */ 94ff718800SKamlakant Patel void __iomem *gpio_intr_stat; /* pointer to first intr status reg */ 95ff718800SKamlakant Patel void __iomem *gpio_intr_type; /* pointer to first intr type reg */ 96ff718800SKamlakant Patel void __iomem *gpio_intr_pol; /* pointer to first intr polarity reg */ 97ff718800SKamlakant Patel void __iomem *gpio_out_en; /* pointer to first output enable reg */ 98ff718800SKamlakant Patel void __iomem *gpio_paddrv; /* pointer to first pad drive reg */ 99ff718800SKamlakant Patel spinlock_t lock; 100ff718800SKamlakant Patel }; 101ff718800SKamlakant Patel 102ff718800SKamlakant Patel static struct xlp_gpio_priv *gpio_chip_to_xlp_priv(struct gpio_chip *gc) 103ff718800SKamlakant Patel { 104ff718800SKamlakant Patel return container_of(gc, struct xlp_gpio_priv, chip); 105ff718800SKamlakant Patel } 106ff718800SKamlakant Patel 107ff718800SKamlakant Patel static int xlp_gpio_get_reg(void __iomem *addr, unsigned gpio) 108ff718800SKamlakant Patel { 109ff718800SKamlakant Patel u32 pos, regset; 110ff718800SKamlakant Patel 111ff718800SKamlakant Patel pos = gpio % XLP_GPIO_REGSZ; 112ff718800SKamlakant Patel regset = (gpio / XLP_GPIO_REGSZ) * 4; 113ff718800SKamlakant Patel return !!(readl(addr + regset) & BIT(pos)); 114ff718800SKamlakant Patel } 115ff718800SKamlakant Patel 116ff718800SKamlakant Patel static void xlp_gpio_set_reg(void __iomem *addr, unsigned gpio, int state) 117ff718800SKamlakant Patel { 118ff718800SKamlakant Patel u32 value, pos, regset; 119ff718800SKamlakant Patel 120ff718800SKamlakant Patel pos = gpio % XLP_GPIO_REGSZ; 121ff718800SKamlakant Patel regset = (gpio / XLP_GPIO_REGSZ) * 4; 122ff718800SKamlakant Patel value = readl(addr + regset); 123ff718800SKamlakant Patel 124ff718800SKamlakant Patel if (state) 125ff718800SKamlakant Patel value |= BIT(pos); 126ff718800SKamlakant Patel else 127ff718800SKamlakant Patel value &= ~BIT(pos); 128ff718800SKamlakant Patel 129ff718800SKamlakant Patel writel(value, addr + regset); 130ff718800SKamlakant Patel } 131ff718800SKamlakant Patel 132ff718800SKamlakant Patel static void xlp_gpio_irq_disable(struct irq_data *d) 133ff718800SKamlakant Patel { 134ff718800SKamlakant Patel struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 135ff718800SKamlakant Patel struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc); 136ff718800SKamlakant Patel unsigned long flags; 137ff718800SKamlakant Patel 138ff718800SKamlakant Patel spin_lock_irqsave(&priv->lock, flags); 139ff718800SKamlakant Patel xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0); 140ff718800SKamlakant Patel __clear_bit(d->hwirq, priv->gpio_enabled_mask); 141ff718800SKamlakant Patel spin_unlock_irqrestore(&priv->lock, flags); 142ff718800SKamlakant Patel } 143ff718800SKamlakant Patel 144ff718800SKamlakant Patel static void xlp_gpio_irq_mask_ack(struct irq_data *d) 145ff718800SKamlakant Patel { 146ff718800SKamlakant Patel struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 147ff718800SKamlakant Patel struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc); 148ff718800SKamlakant Patel unsigned long flags; 149ff718800SKamlakant Patel 150ff718800SKamlakant Patel spin_lock_irqsave(&priv->lock, flags); 151ff718800SKamlakant Patel xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0); 152ff718800SKamlakant Patel xlp_gpio_set_reg(priv->gpio_intr_stat, d->hwirq, 0x1); 153ff718800SKamlakant Patel __clear_bit(d->hwirq, priv->gpio_enabled_mask); 154ff718800SKamlakant Patel spin_unlock_irqrestore(&priv->lock, flags); 155ff718800SKamlakant Patel } 156ff718800SKamlakant Patel 157ff718800SKamlakant Patel static void xlp_gpio_irq_unmask(struct irq_data *d) 158ff718800SKamlakant Patel { 159ff718800SKamlakant Patel struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 160ff718800SKamlakant Patel struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc); 161ff718800SKamlakant Patel unsigned long flags; 162ff718800SKamlakant Patel 163ff718800SKamlakant Patel spin_lock_irqsave(&priv->lock, flags); 164ff718800SKamlakant Patel xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x1); 165ff718800SKamlakant Patel __set_bit(d->hwirq, priv->gpio_enabled_mask); 166ff718800SKamlakant Patel spin_unlock_irqrestore(&priv->lock, flags); 167ff718800SKamlakant Patel } 168ff718800SKamlakant Patel 169ff718800SKamlakant Patel static int xlp_gpio_set_irq_type(struct irq_data *d, unsigned int type) 170ff718800SKamlakant Patel { 171ff718800SKamlakant Patel struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 172ff718800SKamlakant Patel struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc); 173ff718800SKamlakant Patel int pol, irq_type; 174ff718800SKamlakant Patel 175ff718800SKamlakant Patel switch (type) { 176ff718800SKamlakant Patel case IRQ_TYPE_EDGE_RISING: 177ff718800SKamlakant Patel irq_type = XLP_GPIO_IRQ_TYPE_EDGE; 178ff718800SKamlakant Patel pol = XLP_GPIO_IRQ_POL_HIGH; 179ff718800SKamlakant Patel break; 180ff718800SKamlakant Patel case IRQ_TYPE_EDGE_FALLING: 181ff718800SKamlakant Patel irq_type = XLP_GPIO_IRQ_TYPE_EDGE; 182ff718800SKamlakant Patel pol = XLP_GPIO_IRQ_POL_LOW; 183ff718800SKamlakant Patel break; 184ff718800SKamlakant Patel case IRQ_TYPE_LEVEL_HIGH: 185ff718800SKamlakant Patel irq_type = XLP_GPIO_IRQ_TYPE_LVL; 186ff718800SKamlakant Patel pol = XLP_GPIO_IRQ_POL_HIGH; 187ff718800SKamlakant Patel break; 188ff718800SKamlakant Patel case IRQ_TYPE_LEVEL_LOW: 189ff718800SKamlakant Patel irq_type = XLP_GPIO_IRQ_TYPE_LVL; 190ff718800SKamlakant Patel pol = XLP_GPIO_IRQ_POL_LOW; 191ff718800SKamlakant Patel break; 192ff718800SKamlakant Patel default: 193ff718800SKamlakant Patel return -EINVAL; 194ff718800SKamlakant Patel } 195ff718800SKamlakant Patel 196ff718800SKamlakant Patel xlp_gpio_set_reg(priv->gpio_intr_type, d->hwirq, irq_type); 197ff718800SKamlakant Patel xlp_gpio_set_reg(priv->gpio_intr_pol, d->hwirq, pol); 198ff718800SKamlakant Patel 199ff718800SKamlakant Patel return 0; 200ff718800SKamlakant Patel } 201ff718800SKamlakant Patel 202ff718800SKamlakant Patel static struct irq_chip xlp_gpio_irq_chip = { 203ff718800SKamlakant Patel .name = "XLP-GPIO", 204ff718800SKamlakant Patel .irq_mask_ack = xlp_gpio_irq_mask_ack, 205ff718800SKamlakant Patel .irq_disable = xlp_gpio_irq_disable, 206ff718800SKamlakant Patel .irq_set_type = xlp_gpio_set_irq_type, 207ff718800SKamlakant Patel .irq_unmask = xlp_gpio_irq_unmask, 208ff718800SKamlakant Patel .flags = IRQCHIP_ONESHOT_SAFE, 209ff718800SKamlakant Patel }; 210ff718800SKamlakant Patel 211ff718800SKamlakant Patel static irqreturn_t xlp_gpio_generic_handler(int irq, void *data) 212ff718800SKamlakant Patel { 213ff718800SKamlakant Patel struct xlp_gpio_priv *priv = data; 214ff718800SKamlakant Patel int gpio, regoff; 215ff718800SKamlakant Patel u32 gpio_stat; 216ff718800SKamlakant Patel 217ff718800SKamlakant Patel regoff = -1; 218ff718800SKamlakant Patel gpio_stat = 0; 219ff718800SKamlakant Patel for_each_set_bit(gpio, priv->gpio_enabled_mask, XLP_MAX_NR_GPIO) { 220ff718800SKamlakant Patel if (regoff != gpio / XLP_GPIO_REGSZ) { 221ff718800SKamlakant Patel regoff = gpio / XLP_GPIO_REGSZ; 222ff718800SKamlakant Patel gpio_stat = readl(priv->gpio_intr_stat + regoff * 4); 223ff718800SKamlakant Patel } 224ff718800SKamlakant Patel if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ)) 225ff718800SKamlakant Patel generic_handle_irq(irq_find_mapping( 226ff718800SKamlakant Patel priv->chip.irqdomain, gpio)); 227ff718800SKamlakant Patel } 228ff718800SKamlakant Patel 229ff718800SKamlakant Patel return IRQ_HANDLED; 230ff718800SKamlakant Patel } 231ff718800SKamlakant Patel 232ff718800SKamlakant Patel static int xlp_gpio_dir_output(struct gpio_chip *gc, unsigned gpio, int state) 233ff718800SKamlakant Patel { 234ff718800SKamlakant Patel struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc); 235ff718800SKamlakant Patel 236ff718800SKamlakant Patel BUG_ON(gpio >= gc->ngpio); 237ff718800SKamlakant Patel xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x1); 238ff718800SKamlakant Patel 239ff718800SKamlakant Patel return 0; 240ff718800SKamlakant Patel } 241ff718800SKamlakant Patel 242ff718800SKamlakant Patel static int xlp_gpio_dir_input(struct gpio_chip *gc, unsigned gpio) 243ff718800SKamlakant Patel { 244ff718800SKamlakant Patel struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc); 245ff718800SKamlakant Patel 246ff718800SKamlakant Patel BUG_ON(gpio >= gc->ngpio); 247ff718800SKamlakant Patel xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x0); 248ff718800SKamlakant Patel 249ff718800SKamlakant Patel return 0; 250ff718800SKamlakant Patel } 251ff718800SKamlakant Patel 252ff718800SKamlakant Patel static int xlp_gpio_get(struct gpio_chip *gc, unsigned gpio) 253ff718800SKamlakant Patel { 254ff718800SKamlakant Patel struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc); 255ff718800SKamlakant Patel 256ff718800SKamlakant Patel BUG_ON(gpio >= gc->ngpio); 257ff718800SKamlakant Patel return xlp_gpio_get_reg(priv->gpio_paddrv, gpio); 258ff718800SKamlakant Patel } 259ff718800SKamlakant Patel 260ff718800SKamlakant Patel static void xlp_gpio_set(struct gpio_chip *gc, unsigned gpio, int state) 261ff718800SKamlakant Patel { 262ff718800SKamlakant Patel struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc); 263ff718800SKamlakant Patel 264ff718800SKamlakant Patel BUG_ON(gpio >= gc->ngpio); 265ff718800SKamlakant Patel xlp_gpio_set_reg(priv->gpio_paddrv, gpio, state); 266ff718800SKamlakant Patel } 267ff718800SKamlakant Patel 268ff718800SKamlakant Patel static const struct of_device_id xlp_gpio_of_ids[] = { 269ff718800SKamlakant Patel { 270ff718800SKamlakant Patel .compatible = "netlogic,xlp832-gpio", 271ff718800SKamlakant Patel .data = (void *)XLP_GPIO_VARIANT_XLP832, 272ff718800SKamlakant Patel }, 273ff718800SKamlakant Patel { 274ff718800SKamlakant Patel .compatible = "netlogic,xlp316-gpio", 275ff718800SKamlakant Patel .data = (void *)XLP_GPIO_VARIANT_XLP316, 276ff718800SKamlakant Patel }, 277ff718800SKamlakant Patel { 278ff718800SKamlakant Patel .compatible = "netlogic,xlp208-gpio", 279ff718800SKamlakant Patel .data = (void *)XLP_GPIO_VARIANT_XLP208, 280ff718800SKamlakant Patel }, 281ff718800SKamlakant Patel { 282ff718800SKamlakant Patel .compatible = "netlogic,xlp980-gpio", 283ff718800SKamlakant Patel .data = (void *)XLP_GPIO_VARIANT_XLP980, 284ff718800SKamlakant Patel }, 285ff718800SKamlakant Patel { 286ff718800SKamlakant Patel .compatible = "netlogic,xlp532-gpio", 287ff718800SKamlakant Patel .data = (void *)XLP_GPIO_VARIANT_XLP532, 288ff718800SKamlakant Patel }, 289ff718800SKamlakant Patel { /* sentinel */ }, 290ff718800SKamlakant Patel }; 291ff718800SKamlakant Patel MODULE_DEVICE_TABLE(of, xlp_gpio_of_ids); 292ff718800SKamlakant Patel 293ff718800SKamlakant Patel static int xlp_gpio_probe(struct platform_device *pdev) 294ff718800SKamlakant Patel { 295ff718800SKamlakant Patel struct gpio_chip *gc; 296ff718800SKamlakant Patel struct resource *iores; 297ff718800SKamlakant Patel struct xlp_gpio_priv *priv; 298ff718800SKamlakant Patel const struct of_device_id *of_id; 299ff718800SKamlakant Patel void __iomem *gpio_base; 300ff718800SKamlakant Patel int irq_base, irq, err; 301ff718800SKamlakant Patel int ngpio; 302ff718800SKamlakant Patel u32 soc_type; 303ff718800SKamlakant Patel 304ff718800SKamlakant Patel iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 305ff718800SKamlakant Patel if (!iores) 306ff718800SKamlakant Patel return -ENODEV; 307ff718800SKamlakant Patel 308ff718800SKamlakant Patel priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 309ff718800SKamlakant Patel if (!priv) 310ff718800SKamlakant Patel return -ENOMEM; 311ff718800SKamlakant Patel 312ff718800SKamlakant Patel gpio_base = devm_ioremap_resource(&pdev->dev, iores); 313ff718800SKamlakant Patel if (IS_ERR(gpio_base)) 314ff718800SKamlakant Patel return PTR_ERR(gpio_base); 315ff718800SKamlakant Patel 316ff718800SKamlakant Patel irq = platform_get_irq(pdev, 0); 317ff718800SKamlakant Patel if (irq < 0) 318ff718800SKamlakant Patel return irq; 319ff718800SKamlakant Patel 320ff718800SKamlakant Patel of_id = of_match_device(xlp_gpio_of_ids, &pdev->dev); 321ff718800SKamlakant Patel if (!of_id) { 322ff718800SKamlakant Patel dev_err(&pdev->dev, "Failed to get soc type!\n"); 323ff718800SKamlakant Patel return -ENODEV; 324ff718800SKamlakant Patel } 325ff718800SKamlakant Patel 326ff718800SKamlakant Patel soc_type = (uintptr_t) of_id->data; 327ff718800SKamlakant Patel 328ff718800SKamlakant Patel switch (soc_type) { 329ff718800SKamlakant Patel case XLP_GPIO_VARIANT_XLP832: 330ff718800SKamlakant Patel priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN; 331ff718800SKamlakant Patel priv->gpio_paddrv = gpio_base + GPIO_PADDRV; 332ff718800SKamlakant Patel priv->gpio_intr_stat = gpio_base + GPIO_INT_STAT; 333ff718800SKamlakant Patel priv->gpio_intr_type = gpio_base + GPIO_INT_TYPE; 334ff718800SKamlakant Patel priv->gpio_intr_pol = gpio_base + GPIO_INT_POL; 335ff718800SKamlakant Patel priv->gpio_intr_en = gpio_base + GPIO_INT_EN00; 336ff718800SKamlakant Patel ngpio = 41; 337ff718800SKamlakant Patel break; 338ff718800SKamlakant Patel case XLP_GPIO_VARIANT_XLP208: 339ff718800SKamlakant Patel case XLP_GPIO_VARIANT_XLP316: 340ff718800SKamlakant Patel priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN; 341ff718800SKamlakant Patel priv->gpio_paddrv = gpio_base + GPIO_PADDRV; 342ff718800SKamlakant Patel priv->gpio_intr_stat = gpio_base + GPIO_3XX_INT_STAT; 343ff718800SKamlakant Patel priv->gpio_intr_type = gpio_base + GPIO_3XX_INT_TYPE; 344ff718800SKamlakant Patel priv->gpio_intr_pol = gpio_base + GPIO_3XX_INT_POL; 345ff718800SKamlakant Patel priv->gpio_intr_en = gpio_base + GPIO_3XX_INT_EN00; 346ff718800SKamlakant Patel 347ff718800SKamlakant Patel ngpio = (soc_type == XLP_GPIO_VARIANT_XLP208) ? 42 : 57; 348ff718800SKamlakant Patel break; 349ff718800SKamlakant Patel case XLP_GPIO_VARIANT_XLP980: 350ff718800SKamlakant Patel case XLP_GPIO_VARIANT_XLP532: 351ff718800SKamlakant Patel priv->gpio_out_en = gpio_base + GPIO_9XX_OUTPUT_EN; 352ff718800SKamlakant Patel priv->gpio_paddrv = gpio_base + GPIO_9XX_PADDRV; 353ff718800SKamlakant Patel priv->gpio_intr_stat = gpio_base + GPIO_9XX_INT_STAT; 354ff718800SKamlakant Patel priv->gpio_intr_type = gpio_base + GPIO_9XX_INT_TYPE; 355ff718800SKamlakant Patel priv->gpio_intr_pol = gpio_base + GPIO_9XX_INT_POL; 356ff718800SKamlakant Patel priv->gpio_intr_en = gpio_base + GPIO_9XX_INT_EN00; 357ff718800SKamlakant Patel 358ff718800SKamlakant Patel ngpio = (soc_type == XLP_GPIO_VARIANT_XLP980) ? 66 : 67; 359ff718800SKamlakant Patel break; 360ff718800SKamlakant Patel default: 361ff718800SKamlakant Patel dev_err(&pdev->dev, "Unknown Processor type!\n"); 362ff718800SKamlakant Patel return -ENODEV; 363ff718800SKamlakant Patel } 364ff718800SKamlakant Patel 365ff718800SKamlakant Patel bitmap_zero(priv->gpio_enabled_mask, XLP_MAX_NR_GPIO); 366ff718800SKamlakant Patel 367ff718800SKamlakant Patel gc = &priv->chip; 368ff718800SKamlakant Patel 369ff718800SKamlakant Patel gc->base = 0; 370ff718800SKamlakant Patel gc->dev = &pdev->dev; 371ff718800SKamlakant Patel gc->ngpio = ngpio; 372ff718800SKamlakant Patel gc->of_node = pdev->dev.of_node; 373ff718800SKamlakant Patel gc->direction_output = xlp_gpio_dir_output; 374ff718800SKamlakant Patel gc->direction_input = xlp_gpio_dir_input; 375ff718800SKamlakant Patel gc->set = xlp_gpio_set; 376ff718800SKamlakant Patel gc->get = xlp_gpio_get; 377ff718800SKamlakant Patel 378ff718800SKamlakant Patel spin_lock_init(&priv->lock); 379ff718800SKamlakant Patel 380ff718800SKamlakant Patel err = devm_request_irq(&pdev->dev, irq, xlp_gpio_generic_handler, 381ff718800SKamlakant Patel IRQ_TYPE_NONE, pdev->name, priv); 382ff718800SKamlakant Patel if (err) 383ff718800SKamlakant Patel return err; 384ff718800SKamlakant Patel 385ff718800SKamlakant Patel irq_base = irq_alloc_descs(-1, XLP_GPIO_IRQ_BASE, gc->ngpio, 0); 386ff718800SKamlakant Patel if (irq_base < 0) { 387ff718800SKamlakant Patel dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n"); 388ff718800SKamlakant Patel return err; 389ff718800SKamlakant Patel } 390ff718800SKamlakant Patel 391ff718800SKamlakant Patel err = gpiochip_add(gc); 392ff718800SKamlakant Patel if (err < 0) 393ff718800SKamlakant Patel goto out_free_desc; 394ff718800SKamlakant Patel 395ff718800SKamlakant Patel err = gpiochip_irqchip_add(gc, &xlp_gpio_irq_chip, irq_base, 396ff718800SKamlakant Patel handle_level_irq, IRQ_TYPE_NONE); 397ff718800SKamlakant Patel if (err) { 398ff718800SKamlakant Patel dev_err(&pdev->dev, "Could not connect irqchip to gpiochip!\n"); 399ff718800SKamlakant Patel goto out_gpio_remove; 400ff718800SKamlakant Patel } 401ff718800SKamlakant Patel 402ff718800SKamlakant Patel dev_info(&pdev->dev, "registered %d GPIOs\n", gc->ngpio); 403ff718800SKamlakant Patel 404ff718800SKamlakant Patel return 0; 405ff718800SKamlakant Patel 406ff718800SKamlakant Patel out_gpio_remove: 407ff718800SKamlakant Patel gpiochip_remove(gc); 408ff718800SKamlakant Patel out_free_desc: 409ff718800SKamlakant Patel irq_free_descs(irq_base, gc->ngpio); 410ff718800SKamlakant Patel return err; 411ff718800SKamlakant Patel } 412ff718800SKamlakant Patel 413ff718800SKamlakant Patel static struct platform_driver xlp_gpio_driver = { 414ff718800SKamlakant Patel .driver = { 415ff718800SKamlakant Patel .name = "xlp-gpio", 416ff718800SKamlakant Patel .of_match_table = xlp_gpio_of_ids, 417ff718800SKamlakant Patel }, 418ff718800SKamlakant Patel .probe = xlp_gpio_probe, 419ff718800SKamlakant Patel }; 420ff718800SKamlakant Patel module_platform_driver(xlp_gpio_driver); 421ff718800SKamlakant Patel 422ff718800SKamlakant Patel MODULE_AUTHOR("Kamlakant Patel <kamlakant.patel@broadcom.com>"); 423ff718800SKamlakant Patel MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>"); 424ff718800SKamlakant Patel MODULE_DESCRIPTION("Netlogic XLP GPIO Driver"); 425ff718800SKamlakant Patel MODULE_LICENSE("GPL v2"); 426