1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Xilinx gpio driver for xps/axi_gpio IP. 4 * 5 * Copyright 2008 - 2013 Xilinx, Inc. 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/errno.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/irq.h> 16 #include <linux/module.h> 17 #include <linux/of_device.h> 18 #include <linux/of_platform.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/slab.h> 21 22 /* Register Offset Definitions */ 23 #define XGPIO_DATA_OFFSET (0x0) /* Data register */ 24 #define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */ 25 26 #define XGPIO_CHANNEL_OFFSET 0x8 27 28 #define XGPIO_GIER_OFFSET 0x11c /* Global Interrupt Enable */ 29 #define XGPIO_GIER_IE BIT(31) 30 #define XGPIO_IPISR_OFFSET 0x120 /* IP Interrupt Status */ 31 #define XGPIO_IPIER_OFFSET 0x128 /* IP Interrupt Enable */ 32 33 /* Read/Write access to the GPIO registers */ 34 #if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_X86) 35 # define xgpio_readreg(offset) readl(offset) 36 # define xgpio_writereg(offset, val) writel(val, offset) 37 #else 38 # define xgpio_readreg(offset) __raw_readl(offset) 39 # define xgpio_writereg(offset, val) __raw_writel(val, offset) 40 #endif 41 42 /** 43 * struct xgpio_instance - Stores information about GPIO device 44 * @gc: GPIO chip 45 * @regs: register block 46 * @gpio_width: GPIO width for every channel 47 * @gpio_state: GPIO write state shadow register 48 * @gpio_last_irq_read: GPIO read state register from last interrupt 49 * @gpio_dir: GPIO direction shadow register 50 * @gpio_lock: Lock used for synchronization 51 * @irq: IRQ used by GPIO device 52 * @irqchip: IRQ chip 53 * @irq_enable: GPIO IRQ enable/disable bitfield 54 * @irq_rising_edge: GPIO IRQ rising edge enable/disable bitfield 55 * @irq_falling_edge: GPIO IRQ falling edge enable/disable bitfield 56 * @clk: clock resource for this driver 57 */ 58 struct xgpio_instance { 59 struct gpio_chip gc; 60 void __iomem *regs; 61 unsigned int gpio_width[2]; 62 u32 gpio_state[2]; 63 u32 gpio_last_irq_read[2]; 64 u32 gpio_dir[2]; 65 spinlock_t gpio_lock; /* For serializing operations */ 66 int irq; 67 struct irq_chip irqchip; 68 u32 irq_enable[2]; 69 u32 irq_rising_edge[2]; 70 u32 irq_falling_edge[2]; 71 struct clk *clk; 72 }; 73 74 static inline int xgpio_index(struct xgpio_instance *chip, int gpio) 75 { 76 if (gpio >= chip->gpio_width[0]) 77 return 1; 78 79 return 0; 80 } 81 82 static inline int xgpio_regoffset(struct xgpio_instance *chip, int gpio) 83 { 84 if (xgpio_index(chip, gpio)) 85 return XGPIO_CHANNEL_OFFSET; 86 87 return 0; 88 } 89 90 static inline int xgpio_offset(struct xgpio_instance *chip, int gpio) 91 { 92 if (xgpio_index(chip, gpio)) 93 return gpio - chip->gpio_width[0]; 94 95 return gpio; 96 } 97 98 /** 99 * xgpio_get - Read the specified signal of the GPIO device. 100 * @gc: Pointer to gpio_chip device structure. 101 * @gpio: GPIO signal number. 102 * 103 * This function reads the specified signal of the GPIO device. 104 * 105 * Return: 106 * 0 if direction of GPIO signals is set as input otherwise it 107 * returns negative error value. 108 */ 109 static int xgpio_get(struct gpio_chip *gc, unsigned int gpio) 110 { 111 struct xgpio_instance *chip = gpiochip_get_data(gc); 112 u32 val; 113 114 val = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET + 115 xgpio_regoffset(chip, gpio)); 116 117 return !!(val & BIT(xgpio_offset(chip, gpio))); 118 } 119 120 /** 121 * xgpio_set - Write the specified signal of the GPIO device. 122 * @gc: Pointer to gpio_chip device structure. 123 * @gpio: GPIO signal number. 124 * @val: Value to be written to specified signal. 125 * 126 * This function writes the specified value in to the specified signal of the 127 * GPIO device. 128 */ 129 static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 130 { 131 unsigned long flags; 132 struct xgpio_instance *chip = gpiochip_get_data(gc); 133 int index = xgpio_index(chip, gpio); 134 int offset = xgpio_offset(chip, gpio); 135 136 spin_lock_irqsave(&chip->gpio_lock, flags); 137 138 /* Write to GPIO signal and set its direction to output */ 139 if (val) 140 chip->gpio_state[index] |= BIT(offset); 141 else 142 chip->gpio_state[index] &= ~BIT(offset); 143 144 xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + 145 xgpio_regoffset(chip, gpio), chip->gpio_state[index]); 146 147 spin_unlock_irqrestore(&chip->gpio_lock, flags); 148 } 149 150 /** 151 * xgpio_set_multiple - Write the specified signals of the GPIO device. 152 * @gc: Pointer to gpio_chip device structure. 153 * @mask: Mask of the GPIOS to modify. 154 * @bits: Value to be wrote on each GPIO 155 * 156 * This function writes the specified values into the specified signals of the 157 * GPIO devices. 158 */ 159 static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, 160 unsigned long *bits) 161 { 162 unsigned long flags; 163 struct xgpio_instance *chip = gpiochip_get_data(gc); 164 int index = xgpio_index(chip, 0); 165 int offset, i; 166 167 spin_lock_irqsave(&chip->gpio_lock, flags); 168 169 /* Write to GPIO signals */ 170 for (i = 0; i < gc->ngpio; i++) { 171 if (*mask == 0) 172 break; 173 /* Once finished with an index write it out to the register */ 174 if (index != xgpio_index(chip, i)) { 175 xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + 176 index * XGPIO_CHANNEL_OFFSET, 177 chip->gpio_state[index]); 178 spin_unlock_irqrestore(&chip->gpio_lock, flags); 179 index = xgpio_index(chip, i); 180 spin_lock_irqsave(&chip->gpio_lock, flags); 181 } 182 if (__test_and_clear_bit(i, mask)) { 183 offset = xgpio_offset(chip, i); 184 if (test_bit(i, bits)) 185 chip->gpio_state[index] |= BIT(offset); 186 else 187 chip->gpio_state[index] &= ~BIT(offset); 188 } 189 } 190 191 xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + 192 index * XGPIO_CHANNEL_OFFSET, chip->gpio_state[index]); 193 194 spin_unlock_irqrestore(&chip->gpio_lock, flags); 195 } 196 197 /** 198 * xgpio_dir_in - Set the direction of the specified GPIO signal as input. 199 * @gc: Pointer to gpio_chip device structure. 200 * @gpio: GPIO signal number. 201 * 202 * Return: 203 * 0 - if direction of GPIO signals is set as input 204 * otherwise it returns negative error value. 205 */ 206 static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) 207 { 208 unsigned long flags; 209 struct xgpio_instance *chip = gpiochip_get_data(gc); 210 int index = xgpio_index(chip, gpio); 211 int offset = xgpio_offset(chip, gpio); 212 213 spin_lock_irqsave(&chip->gpio_lock, flags); 214 215 /* Set the GPIO bit in shadow register and set direction as input */ 216 chip->gpio_dir[index] |= BIT(offset); 217 xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + 218 xgpio_regoffset(chip, gpio), chip->gpio_dir[index]); 219 220 spin_unlock_irqrestore(&chip->gpio_lock, flags); 221 222 return 0; 223 } 224 225 /** 226 * xgpio_dir_out - Set the direction of the specified GPIO signal as output. 227 * @gc: Pointer to gpio_chip device structure. 228 * @gpio: GPIO signal number. 229 * @val: Value to be written to specified signal. 230 * 231 * This function sets the direction of specified GPIO signal as output. 232 * 233 * Return: 234 * If all GPIO signals of GPIO chip is configured as input then it returns 235 * error otherwise it returns 0. 236 */ 237 static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 238 { 239 unsigned long flags; 240 struct xgpio_instance *chip = gpiochip_get_data(gc); 241 int index = xgpio_index(chip, gpio); 242 int offset = xgpio_offset(chip, gpio); 243 244 spin_lock_irqsave(&chip->gpio_lock, flags); 245 246 /* Write state of GPIO signal */ 247 if (val) 248 chip->gpio_state[index] |= BIT(offset); 249 else 250 chip->gpio_state[index] &= ~BIT(offset); 251 xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + 252 xgpio_regoffset(chip, gpio), chip->gpio_state[index]); 253 254 /* Clear the GPIO bit in shadow register and set direction as output */ 255 chip->gpio_dir[index] &= ~BIT(offset); 256 xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + 257 xgpio_regoffset(chip, gpio), chip->gpio_dir[index]); 258 259 spin_unlock_irqrestore(&chip->gpio_lock, flags); 260 261 return 0; 262 } 263 264 /** 265 * xgpio_save_regs - Set initial values of GPIO pins 266 * @chip: Pointer to GPIO instance 267 */ 268 static void xgpio_save_regs(struct xgpio_instance *chip) 269 { 270 xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET, chip->gpio_state[0]); 271 xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET, chip->gpio_dir[0]); 272 273 if (!chip->gpio_width[1]) 274 return; 275 276 xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + XGPIO_CHANNEL_OFFSET, 277 chip->gpio_state[1]); 278 xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + XGPIO_CHANNEL_OFFSET, 279 chip->gpio_dir[1]); 280 } 281 282 static int xgpio_request(struct gpio_chip *chip, unsigned int offset) 283 { 284 int ret; 285 286 ret = pm_runtime_get_sync(chip->parent); 287 /* 288 * If the device is already active pm_runtime_get() will return 1 on 289 * success, but gpio_request still needs to return 0. 290 */ 291 return ret < 0 ? ret : 0; 292 } 293 294 static void xgpio_free(struct gpio_chip *chip, unsigned int offset) 295 { 296 pm_runtime_put(chip->parent); 297 } 298 299 static int __maybe_unused xgpio_suspend(struct device *dev) 300 { 301 struct xgpio_instance *gpio = dev_get_drvdata(dev); 302 struct irq_data *data = irq_get_irq_data(gpio->irq); 303 304 if (!data) { 305 dev_err(dev, "irq_get_irq_data() failed\n"); 306 return -EINVAL; 307 } 308 309 if (!irqd_is_wakeup_set(data)) 310 return pm_runtime_force_suspend(dev); 311 312 return 0; 313 } 314 315 /** 316 * xgpio_remove - Remove method for the GPIO device. 317 * @pdev: pointer to the platform device 318 * 319 * This function remove gpiochips and frees all the allocated resources. 320 * 321 * Return: 0 always 322 */ 323 static int xgpio_remove(struct platform_device *pdev) 324 { 325 struct xgpio_instance *gpio = platform_get_drvdata(pdev); 326 327 pm_runtime_get_sync(&pdev->dev); 328 pm_runtime_put_noidle(&pdev->dev); 329 pm_runtime_disable(&pdev->dev); 330 clk_disable_unprepare(gpio->clk); 331 332 return 0; 333 } 334 335 /** 336 * xgpio_irq_ack - Acknowledge a child GPIO interrupt. 337 * @irq_data: per IRQ and chip data passed down to chip functions 338 * This currently does nothing, but irq_ack is unconditionally called by 339 * handle_edge_irq and therefore must be defined. 340 */ 341 static void xgpio_irq_ack(struct irq_data *irq_data) 342 { 343 } 344 345 static int __maybe_unused xgpio_resume(struct device *dev) 346 { 347 struct xgpio_instance *gpio = dev_get_drvdata(dev); 348 struct irq_data *data = irq_get_irq_data(gpio->irq); 349 350 if (!data) { 351 dev_err(dev, "irq_get_irq_data() failed\n"); 352 return -EINVAL; 353 } 354 355 if (!irqd_is_wakeup_set(data)) 356 return pm_runtime_force_resume(dev); 357 358 return 0; 359 } 360 361 static int __maybe_unused xgpio_runtime_suspend(struct device *dev) 362 { 363 struct platform_device *pdev = to_platform_device(dev); 364 struct xgpio_instance *gpio = platform_get_drvdata(pdev); 365 366 clk_disable(gpio->clk); 367 368 return 0; 369 } 370 371 static int __maybe_unused xgpio_runtime_resume(struct device *dev) 372 { 373 struct platform_device *pdev = to_platform_device(dev); 374 struct xgpio_instance *gpio = platform_get_drvdata(pdev); 375 376 return clk_enable(gpio->clk); 377 } 378 379 static const struct dev_pm_ops xgpio_dev_pm_ops = { 380 SET_SYSTEM_SLEEP_PM_OPS(xgpio_suspend, xgpio_resume) 381 SET_RUNTIME_PM_OPS(xgpio_runtime_suspend, 382 xgpio_runtime_resume, NULL) 383 }; 384 385 /** 386 * xgpio_irq_mask - Write the specified signal of the GPIO device. 387 * @irq_data: per IRQ and chip data passed down to chip functions 388 */ 389 static void xgpio_irq_mask(struct irq_data *irq_data) 390 { 391 unsigned long flags; 392 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); 393 int irq_offset = irqd_to_hwirq(irq_data); 394 int index = xgpio_index(chip, irq_offset); 395 int offset = xgpio_offset(chip, irq_offset); 396 397 spin_lock_irqsave(&chip->gpio_lock, flags); 398 399 chip->irq_enable[index] &= ~BIT(offset); 400 401 if (!chip->irq_enable[index]) { 402 /* Disable per channel interrupt */ 403 u32 temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); 404 405 temp &= ~BIT(index); 406 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp); 407 } 408 spin_unlock_irqrestore(&chip->gpio_lock, flags); 409 } 410 411 /** 412 * xgpio_irq_unmask - Write the specified signal of the GPIO device. 413 * @irq_data: per IRQ and chip data passed down to chip functions 414 */ 415 static void xgpio_irq_unmask(struct irq_data *irq_data) 416 { 417 unsigned long flags; 418 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); 419 int irq_offset = irqd_to_hwirq(irq_data); 420 int index = xgpio_index(chip, irq_offset); 421 int offset = xgpio_offset(chip, irq_offset); 422 u32 old_enable = chip->irq_enable[index]; 423 424 spin_lock_irqsave(&chip->gpio_lock, flags); 425 426 chip->irq_enable[index] |= BIT(offset); 427 428 if (!old_enable) { 429 /* Clear any existing per-channel interrupts */ 430 u32 val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET) & 431 BIT(index); 432 433 if (val) 434 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val); 435 436 /* Update GPIO IRQ read data before enabling interrupt*/ 437 val = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET + 438 index * XGPIO_CHANNEL_OFFSET); 439 chip->gpio_last_irq_read[index] = val; 440 441 /* Enable per channel interrupt */ 442 val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); 443 val |= BIT(index); 444 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val); 445 } 446 447 spin_unlock_irqrestore(&chip->gpio_lock, flags); 448 } 449 450 /** 451 * xgpio_set_irq_type - Write the specified signal of the GPIO device. 452 * @irq_data: Per IRQ and chip data passed down to chip functions 453 * @type: Interrupt type that is to be set for the gpio pin 454 * 455 * Return: 456 * 0 if interrupt type is supported otherwise -EINVAL 457 */ 458 static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type) 459 { 460 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); 461 int irq_offset = irqd_to_hwirq(irq_data); 462 int index = xgpio_index(chip, irq_offset); 463 int offset = xgpio_offset(chip, irq_offset); 464 465 /* 466 * The Xilinx GPIO hardware provides a single interrupt status 467 * indication for any state change in a given GPIO channel (bank). 468 * Therefore, only rising edge or falling edge triggers are 469 * supported. 470 */ 471 switch (type & IRQ_TYPE_SENSE_MASK) { 472 case IRQ_TYPE_EDGE_BOTH: 473 chip->irq_rising_edge[index] |= BIT(offset); 474 chip->irq_falling_edge[index] |= BIT(offset); 475 break; 476 case IRQ_TYPE_EDGE_RISING: 477 chip->irq_rising_edge[index] |= BIT(offset); 478 chip->irq_falling_edge[index] &= ~BIT(offset); 479 break; 480 case IRQ_TYPE_EDGE_FALLING: 481 chip->irq_rising_edge[index] &= ~BIT(offset); 482 chip->irq_falling_edge[index] |= BIT(offset); 483 break; 484 default: 485 return -EINVAL; 486 } 487 488 irq_set_handler_locked(irq_data, handle_edge_irq); 489 return 0; 490 } 491 492 /** 493 * xgpio_irqhandler - Gpio interrupt service routine 494 * @desc: Pointer to interrupt description 495 */ 496 static void xgpio_irqhandler(struct irq_desc *desc) 497 { 498 struct xgpio_instance *chip = irq_desc_get_handler_data(desc); 499 struct irq_chip *irqchip = irq_desc_get_chip(desc); 500 u32 num_channels = chip->gpio_width[1] ? 2 : 1; 501 u32 offset = 0, index; 502 u32 status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); 503 504 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status); 505 506 chained_irq_enter(irqchip, desc); 507 for (index = 0; index < num_channels; index++) { 508 if ((status & BIT(index))) { 509 unsigned long rising_events, falling_events, all_events; 510 unsigned long flags; 511 u32 data, bit; 512 unsigned int irq; 513 514 spin_lock_irqsave(&chip->gpio_lock, flags); 515 data = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET + 516 index * XGPIO_CHANNEL_OFFSET); 517 rising_events = data & 518 ~chip->gpio_last_irq_read[index] & 519 chip->irq_enable[index] & 520 chip->irq_rising_edge[index]; 521 falling_events = ~data & 522 chip->gpio_last_irq_read[index] & 523 chip->irq_enable[index] & 524 chip->irq_falling_edge[index]; 525 dev_dbg(chip->gc.parent, 526 "IRQ chan %u rising 0x%lx falling 0x%lx\n", 527 index, rising_events, falling_events); 528 all_events = rising_events | falling_events; 529 chip->gpio_last_irq_read[index] = data; 530 spin_unlock_irqrestore(&chip->gpio_lock, flags); 531 532 for_each_set_bit(bit, &all_events, 32) { 533 irq = irq_find_mapping(chip->gc.irq.domain, 534 offset + bit); 535 generic_handle_irq(irq); 536 } 537 } 538 offset += chip->gpio_width[index]; 539 } 540 541 chained_irq_exit(irqchip, desc); 542 } 543 544 /** 545 * xgpio_probe - Probe method for the GPIO device. 546 * @pdev: pointer to the platform device 547 * 548 * Return: 549 * It returns 0, if the driver is bound to the GPIO device, or 550 * a negative value if there is an error. 551 */ 552 static int xgpio_probe(struct platform_device *pdev) 553 { 554 struct xgpio_instance *chip; 555 int status = 0; 556 struct device_node *np = pdev->dev.of_node; 557 u32 is_dual = 0; 558 u32 cells = 2; 559 struct gpio_irq_chip *girq; 560 u32 temp; 561 562 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 563 if (!chip) 564 return -ENOMEM; 565 566 platform_set_drvdata(pdev, chip); 567 568 /* Update GPIO state shadow register with default value */ 569 if (of_property_read_u32(np, "xlnx,dout-default", &chip->gpio_state[0])) 570 chip->gpio_state[0] = 0x0; 571 572 /* Update GPIO direction shadow register with default value */ 573 if (of_property_read_u32(np, "xlnx,tri-default", &chip->gpio_dir[0])) 574 chip->gpio_dir[0] = 0xFFFFFFFF; 575 576 /* Update cells with gpio-cells value */ 577 if (of_property_read_u32(np, "#gpio-cells", &cells)) 578 dev_dbg(&pdev->dev, "Missing gpio-cells property\n"); 579 580 if (cells != 2) { 581 dev_err(&pdev->dev, "#gpio-cells mismatch\n"); 582 return -EINVAL; 583 } 584 585 /* 586 * Check device node and parent device node for device width 587 * and assume default width of 32 588 */ 589 if (of_property_read_u32(np, "xlnx,gpio-width", &chip->gpio_width[0])) 590 chip->gpio_width[0] = 32; 591 592 if (chip->gpio_width[0] > 32) 593 return -EINVAL; 594 595 spin_lock_init(&chip->gpio_lock); 596 597 if (of_property_read_u32(np, "xlnx,is-dual", &is_dual)) 598 is_dual = 0; 599 600 if (is_dual) { 601 /* Update GPIO state shadow register with default value */ 602 if (of_property_read_u32(np, "xlnx,dout-default-2", 603 &chip->gpio_state[1])) 604 chip->gpio_state[1] = 0x0; 605 606 /* Update GPIO direction shadow register with default value */ 607 if (of_property_read_u32(np, "xlnx,tri-default-2", 608 &chip->gpio_dir[1])) 609 chip->gpio_dir[1] = 0xFFFFFFFF; 610 611 /* 612 * Check device node and parent device node for device width 613 * and assume default width of 32 614 */ 615 if (of_property_read_u32(np, "xlnx,gpio2-width", 616 &chip->gpio_width[1])) 617 chip->gpio_width[1] = 32; 618 619 if (chip->gpio_width[1] > 32) 620 return -EINVAL; 621 } 622 623 chip->gc.base = -1; 624 chip->gc.ngpio = chip->gpio_width[0] + chip->gpio_width[1]; 625 chip->gc.parent = &pdev->dev; 626 chip->gc.direction_input = xgpio_dir_in; 627 chip->gc.direction_output = xgpio_dir_out; 628 chip->gc.of_gpio_n_cells = cells; 629 chip->gc.get = xgpio_get; 630 chip->gc.set = xgpio_set; 631 chip->gc.request = xgpio_request; 632 chip->gc.free = xgpio_free; 633 chip->gc.set_multiple = xgpio_set_multiple; 634 635 chip->gc.label = dev_name(&pdev->dev); 636 637 chip->regs = devm_platform_ioremap_resource(pdev, 0); 638 if (IS_ERR(chip->regs)) { 639 dev_err(&pdev->dev, "failed to ioremap memory resource\n"); 640 return PTR_ERR(chip->regs); 641 } 642 643 chip->clk = devm_clk_get_optional(&pdev->dev, NULL); 644 if (IS_ERR(chip->clk)) 645 return dev_err_probe(&pdev->dev, PTR_ERR(chip->clk), "input clock not found.\n"); 646 647 status = clk_prepare_enable(chip->clk); 648 if (status < 0) { 649 dev_err(&pdev->dev, "Failed to prepare clk\n"); 650 return status; 651 } 652 pm_runtime_get_noresume(&pdev->dev); 653 pm_runtime_set_active(&pdev->dev); 654 pm_runtime_enable(&pdev->dev); 655 656 xgpio_save_regs(chip); 657 658 chip->irq = platform_get_irq_optional(pdev, 0); 659 if (chip->irq <= 0) 660 goto skip_irq; 661 662 chip->irqchip.name = "gpio-xilinx"; 663 chip->irqchip.irq_ack = xgpio_irq_ack; 664 chip->irqchip.irq_mask = xgpio_irq_mask; 665 chip->irqchip.irq_unmask = xgpio_irq_unmask; 666 chip->irqchip.irq_set_type = xgpio_set_irq_type; 667 668 /* Disable per-channel interrupts */ 669 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, 0); 670 /* Clear any existing per-channel interrupts */ 671 temp = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); 672 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, temp); 673 /* Enable global interrupts */ 674 xgpio_writereg(chip->regs + XGPIO_GIER_OFFSET, XGPIO_GIER_IE); 675 676 girq = &chip->gc.irq; 677 girq->chip = &chip->irqchip; 678 girq->parent_handler = xgpio_irqhandler; 679 girq->num_parents = 1; 680 girq->parents = devm_kcalloc(&pdev->dev, 1, 681 sizeof(*girq->parents), 682 GFP_KERNEL); 683 if (!girq->parents) { 684 status = -ENOMEM; 685 goto err_pm_put; 686 } 687 girq->parents[0] = chip->irq; 688 girq->default_type = IRQ_TYPE_NONE; 689 girq->handler = handle_bad_irq; 690 691 skip_irq: 692 status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip); 693 if (status) { 694 dev_err(&pdev->dev, "failed to add GPIO chip\n"); 695 goto err_pm_put; 696 } 697 698 pm_runtime_put(&pdev->dev); 699 return 0; 700 701 err_pm_put: 702 pm_runtime_disable(&pdev->dev); 703 pm_runtime_put_noidle(&pdev->dev); 704 clk_disable_unprepare(chip->clk); 705 return status; 706 } 707 708 static const struct of_device_id xgpio_of_match[] = { 709 { .compatible = "xlnx,xps-gpio-1.00.a", }, 710 { /* end of list */ }, 711 }; 712 713 MODULE_DEVICE_TABLE(of, xgpio_of_match); 714 715 static struct platform_driver xgpio_plat_driver = { 716 .probe = xgpio_probe, 717 .remove = xgpio_remove, 718 .driver = { 719 .name = "gpio-xilinx", 720 .of_match_table = xgpio_of_match, 721 .pm = &xgpio_dev_pm_ops, 722 }, 723 }; 724 725 static int __init xgpio_init(void) 726 { 727 return platform_driver_register(&xgpio_plat_driver); 728 } 729 730 subsys_initcall(xgpio_init); 731 732 static void __exit xgpio_exit(void) 733 { 734 platform_driver_unregister(&xgpio_plat_driver); 735 } 736 module_exit(xgpio_exit); 737 738 MODULE_AUTHOR("Xilinx, Inc."); 739 MODULE_DESCRIPTION("Xilinx GPIO driver"); 740 MODULE_LICENSE("GPL"); 741