1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO driver for the WinSystems WS16C48 4 * Copyright (C) 2016 William Breathitt Gray 5 */ 6 #include <linux/bitmap.h> 7 #include <linux/device.h> 8 #include <linux/errno.h> 9 #include <linux/gpio/driver.h> 10 #include <linux/io.h> 11 #include <linux/ioport.h> 12 #include <linux/interrupt.h> 13 #include <linux/irqdesc.h> 14 #include <linux/isa.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/moduleparam.h> 18 #include <linux/spinlock.h> 19 #include <linux/types.h> 20 21 #define WS16C48_EXTENT 10 22 #define MAX_NUM_WS16C48 max_num_isa_dev(WS16C48_EXTENT) 23 24 static unsigned int base[MAX_NUM_WS16C48]; 25 static unsigned int num_ws16c48; 26 module_param_hw_array(base, uint, ioport, &num_ws16c48, 0); 27 MODULE_PARM_DESC(base, "WinSystems WS16C48 base addresses"); 28 29 static unsigned int irq[MAX_NUM_WS16C48]; 30 static unsigned int num_irq; 31 module_param_hw_array(irq, uint, irq, &num_irq, 0); 32 MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers"); 33 34 /** 35 * struct ws16c48_reg - device register structure 36 * @port: Port 0 through 5 I/O 37 * @int_pending: Interrupt Pending 38 * @page_lock: Register page (Bits 7-6) and I/O port lock (Bits 5-0) 39 * @pol_enab_int_id: Interrupt polarity, enable, and ID 40 */ 41 struct ws16c48_reg { 42 u8 port[6]; 43 u8 int_pending; 44 u8 page_lock; 45 u8 pol_enab_int_id[3]; 46 }; 47 48 /** 49 * struct ws16c48_gpio - GPIO device private data structure 50 * @chip: instance of the gpio_chip 51 * @io_state: bit I/O state (whether bit is set to input or output) 52 * @out_state: output bits state 53 * @lock: synchronization lock to prevent I/O race conditions 54 * @irq_mask: I/O bits affected by interrupts 55 * @flow_mask: IRQ flow type mask for the respective I/O bits 56 * @reg: I/O address offset for the device registers 57 */ 58 struct ws16c48_gpio { 59 struct gpio_chip chip; 60 unsigned char io_state[6]; 61 unsigned char out_state[6]; 62 raw_spinlock_t lock; 63 unsigned long irq_mask; 64 unsigned long flow_mask; 65 struct ws16c48_reg __iomem *reg; 66 }; 67 68 static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 69 { 70 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 71 const unsigned port = offset / 8; 72 const unsigned mask = BIT(offset % 8); 73 74 if (ws16c48gpio->io_state[port] & mask) 75 return GPIO_LINE_DIRECTION_IN; 76 77 return GPIO_LINE_DIRECTION_OUT; 78 } 79 80 static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 81 { 82 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 83 const unsigned port = offset / 8; 84 const unsigned mask = BIT(offset % 8); 85 unsigned long flags; 86 87 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 88 89 ws16c48gpio->io_state[port] |= mask; 90 ws16c48gpio->out_state[port] &= ~mask; 91 iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port); 92 93 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 94 95 return 0; 96 } 97 98 static int ws16c48_gpio_direction_output(struct gpio_chip *chip, 99 unsigned offset, int value) 100 { 101 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 102 const unsigned port = offset / 8; 103 const unsigned mask = BIT(offset % 8); 104 unsigned long flags; 105 106 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 107 108 ws16c48gpio->io_state[port] &= ~mask; 109 if (value) 110 ws16c48gpio->out_state[port] |= mask; 111 else 112 ws16c48gpio->out_state[port] &= ~mask; 113 iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port); 114 115 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 116 117 return 0; 118 } 119 120 static int ws16c48_gpio_get(struct gpio_chip *chip, unsigned offset) 121 { 122 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 123 const unsigned port = offset / 8; 124 const unsigned mask = BIT(offset % 8); 125 unsigned long flags; 126 unsigned port_state; 127 128 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 129 130 /* ensure that GPIO is set for input */ 131 if (!(ws16c48gpio->io_state[port] & mask)) { 132 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 133 return -EINVAL; 134 } 135 136 port_state = ioread8(ws16c48gpio->reg->port + port); 137 138 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 139 140 return !!(port_state & mask); 141 } 142 143 static int ws16c48_gpio_get_multiple(struct gpio_chip *chip, 144 unsigned long *mask, unsigned long *bits) 145 { 146 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 147 unsigned long offset; 148 unsigned long gpio_mask; 149 size_t index; 150 u8 __iomem *port_addr; 151 unsigned long port_state; 152 153 /* clear bits array to a clean slate */ 154 bitmap_zero(bits, chip->ngpio); 155 156 for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) { 157 index = offset / 8; 158 port_addr = ws16c48gpio->reg->port + index; 159 port_state = ioread8(port_addr) & gpio_mask; 160 161 bitmap_set_value8(bits, port_state, offset); 162 } 163 164 return 0; 165 } 166 167 static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 168 { 169 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 170 const unsigned port = offset / 8; 171 const unsigned mask = BIT(offset % 8); 172 unsigned long flags; 173 174 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 175 176 /* ensure that GPIO is set for output */ 177 if (ws16c48gpio->io_state[port] & mask) { 178 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 179 return; 180 } 181 182 if (value) 183 ws16c48gpio->out_state[port] |= mask; 184 else 185 ws16c48gpio->out_state[port] &= ~mask; 186 iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port); 187 188 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 189 } 190 191 static void ws16c48_gpio_set_multiple(struct gpio_chip *chip, 192 unsigned long *mask, unsigned long *bits) 193 { 194 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 195 unsigned long offset; 196 unsigned long gpio_mask; 197 size_t index; 198 u8 __iomem *port_addr; 199 unsigned long bitmask; 200 unsigned long flags; 201 202 for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) { 203 index = offset / 8; 204 port_addr = ws16c48gpio->reg->port + index; 205 206 /* mask out GPIO configured for input */ 207 gpio_mask &= ~ws16c48gpio->io_state[index]; 208 bitmask = bitmap_get_value8(bits, offset) & gpio_mask; 209 210 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 211 212 /* update output state data and set device gpio register */ 213 ws16c48gpio->out_state[index] &= ~gpio_mask; 214 ws16c48gpio->out_state[index] |= bitmask; 215 iowrite8(ws16c48gpio->out_state[index], port_addr); 216 217 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 218 } 219 } 220 221 static void ws16c48_irq_ack(struct irq_data *data) 222 { 223 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 224 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 225 const unsigned long offset = irqd_to_hwirq(data); 226 const unsigned port = offset / 8; 227 const unsigned mask = BIT(offset % 8); 228 unsigned long flags; 229 unsigned port_state; 230 231 /* only the first 3 ports support interrupts */ 232 if (port > 2) 233 return; 234 235 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 236 237 port_state = ws16c48gpio->irq_mask >> (8*port); 238 239 /* Select Register Page 2; Unlock all I/O ports */ 240 iowrite8(0x80, &ws16c48gpio->reg->page_lock); 241 242 /* Clear pending interrupt */ 243 iowrite8(port_state & ~mask, ws16c48gpio->reg->pol_enab_int_id + port); 244 iowrite8(port_state | mask, ws16c48gpio->reg->pol_enab_int_id + port); 245 246 /* Select Register Page 3; Unlock all I/O ports */ 247 iowrite8(0xC0, &ws16c48gpio->reg->page_lock); 248 249 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 250 } 251 252 static void ws16c48_irq_mask(struct irq_data *data) 253 { 254 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 255 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 256 const unsigned long offset = irqd_to_hwirq(data); 257 const unsigned long mask = BIT(offset); 258 const unsigned port = offset / 8; 259 unsigned long flags; 260 unsigned long port_state; 261 262 /* only the first 3 ports support interrupts */ 263 if (port > 2) 264 return; 265 266 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 267 268 ws16c48gpio->irq_mask &= ~mask; 269 gpiochip_disable_irq(chip, offset); 270 port_state = ws16c48gpio->irq_mask >> (8 * port); 271 272 /* Select Register Page 2; Unlock all I/O ports */ 273 iowrite8(0x80, &ws16c48gpio->reg->page_lock); 274 275 /* Disable interrupt */ 276 iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port); 277 278 /* Select Register Page 3; Unlock all I/O ports */ 279 iowrite8(0xC0, &ws16c48gpio->reg->page_lock); 280 281 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 282 } 283 284 static void ws16c48_irq_unmask(struct irq_data *data) 285 { 286 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 287 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 288 const unsigned long offset = irqd_to_hwirq(data); 289 const unsigned long mask = BIT(offset); 290 const unsigned port = offset / 8; 291 unsigned long flags; 292 unsigned long port_state; 293 294 /* only the first 3 ports support interrupts */ 295 if (port > 2) 296 return; 297 298 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 299 300 gpiochip_enable_irq(chip, offset); 301 ws16c48gpio->irq_mask |= mask; 302 port_state = ws16c48gpio->irq_mask >> (8 * port); 303 304 /* Select Register Page 2; Unlock all I/O ports */ 305 iowrite8(0x80, &ws16c48gpio->reg->page_lock); 306 307 /* Enable interrupt */ 308 iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port); 309 310 /* Select Register Page 3; Unlock all I/O ports */ 311 iowrite8(0xC0, &ws16c48gpio->reg->page_lock); 312 313 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 314 } 315 316 static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type) 317 { 318 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 319 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 320 const unsigned long offset = irqd_to_hwirq(data); 321 const unsigned long mask = BIT(offset); 322 const unsigned port = offset / 8; 323 unsigned long flags; 324 unsigned long port_state; 325 326 /* only the first 3 ports support interrupts */ 327 if (port > 2) 328 return -EINVAL; 329 330 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 331 332 switch (flow_type) { 333 case IRQ_TYPE_NONE: 334 break; 335 case IRQ_TYPE_EDGE_RISING: 336 ws16c48gpio->flow_mask |= mask; 337 break; 338 case IRQ_TYPE_EDGE_FALLING: 339 ws16c48gpio->flow_mask &= ~mask; 340 break; 341 default: 342 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 343 return -EINVAL; 344 } 345 346 port_state = ws16c48gpio->flow_mask >> (8 * port); 347 348 /* Select Register Page 1; Unlock all I/O ports */ 349 iowrite8(0x40, &ws16c48gpio->reg->page_lock); 350 351 /* Set interrupt polarity */ 352 iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port); 353 354 /* Select Register Page 3; Unlock all I/O ports */ 355 iowrite8(0xC0, &ws16c48gpio->reg->page_lock); 356 357 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 358 359 return 0; 360 } 361 362 static const struct irq_chip ws16c48_irqchip = { 363 .name = "ws16c48", 364 .irq_ack = ws16c48_irq_ack, 365 .irq_mask = ws16c48_irq_mask, 366 .irq_unmask = ws16c48_irq_unmask, 367 .irq_set_type = ws16c48_irq_set_type, 368 .flags = IRQCHIP_IMMUTABLE, 369 GPIOCHIP_IRQ_RESOURCE_HELPERS, 370 }; 371 372 static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id) 373 { 374 struct ws16c48_gpio *const ws16c48gpio = dev_id; 375 struct gpio_chip *const chip = &ws16c48gpio->chip; 376 struct ws16c48_reg __iomem *const reg = ws16c48gpio->reg; 377 unsigned long int_pending; 378 unsigned long port; 379 unsigned long int_id; 380 unsigned long gpio; 381 382 int_pending = ioread8(®->int_pending) & 0x7; 383 if (!int_pending) 384 return IRQ_NONE; 385 386 /* loop until all pending interrupts are handled */ 387 do { 388 for_each_set_bit(port, &int_pending, 3) { 389 int_id = ioread8(reg->pol_enab_int_id + port); 390 for_each_set_bit(gpio, &int_id, 8) 391 generic_handle_domain_irq(chip->irq.domain, 392 gpio + 8*port); 393 } 394 395 int_pending = ioread8(®->int_pending) & 0x7; 396 } while (int_pending); 397 398 return IRQ_HANDLED; 399 } 400 401 #define WS16C48_NGPIO 48 402 static const char *ws16c48_names[WS16C48_NGPIO] = { 403 "Port 0 Bit 0", "Port 0 Bit 1", "Port 0 Bit 2", "Port 0 Bit 3", 404 "Port 0 Bit 4", "Port 0 Bit 5", "Port 0 Bit 6", "Port 0 Bit 7", 405 "Port 1 Bit 0", "Port 1 Bit 1", "Port 1 Bit 2", "Port 1 Bit 3", 406 "Port 1 Bit 4", "Port 1 Bit 5", "Port 1 Bit 6", "Port 1 Bit 7", 407 "Port 2 Bit 0", "Port 2 Bit 1", "Port 2 Bit 2", "Port 2 Bit 3", 408 "Port 2 Bit 4", "Port 2 Bit 5", "Port 2 Bit 6", "Port 2 Bit 7", 409 "Port 3 Bit 0", "Port 3 Bit 1", "Port 3 Bit 2", "Port 3 Bit 3", 410 "Port 3 Bit 4", "Port 3 Bit 5", "Port 3 Bit 6", "Port 3 Bit 7", 411 "Port 4 Bit 0", "Port 4 Bit 1", "Port 4 Bit 2", "Port 4 Bit 3", 412 "Port 4 Bit 4", "Port 4 Bit 5", "Port 4 Bit 6", "Port 4 Bit 7", 413 "Port 5 Bit 0", "Port 5 Bit 1", "Port 5 Bit 2", "Port 5 Bit 3", 414 "Port 5 Bit 4", "Port 5 Bit 5", "Port 5 Bit 6", "Port 5 Bit 7" 415 }; 416 417 static int ws16c48_irq_init_hw(struct gpio_chip *gc) 418 { 419 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(gc); 420 421 /* Select Register Page 2; Unlock all I/O ports */ 422 iowrite8(0x80, &ws16c48gpio->reg->page_lock); 423 424 /* Disable interrupts for all lines */ 425 iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[0]); 426 iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[1]); 427 iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[2]); 428 429 /* Select Register Page 3; Unlock all I/O ports */ 430 iowrite8(0xC0, &ws16c48gpio->reg->page_lock); 431 432 return 0; 433 } 434 435 static int ws16c48_probe(struct device *dev, unsigned int id) 436 { 437 struct ws16c48_gpio *ws16c48gpio; 438 const char *const name = dev_name(dev); 439 struct gpio_irq_chip *girq; 440 int err; 441 442 ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL); 443 if (!ws16c48gpio) 444 return -ENOMEM; 445 446 if (!devm_request_region(dev, base[id], WS16C48_EXTENT, name)) { 447 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n", 448 base[id], base[id] + WS16C48_EXTENT); 449 return -EBUSY; 450 } 451 452 ws16c48gpio->reg = devm_ioport_map(dev, base[id], WS16C48_EXTENT); 453 if (!ws16c48gpio->reg) 454 return -ENOMEM; 455 456 ws16c48gpio->chip.label = name; 457 ws16c48gpio->chip.parent = dev; 458 ws16c48gpio->chip.owner = THIS_MODULE; 459 ws16c48gpio->chip.base = -1; 460 ws16c48gpio->chip.ngpio = WS16C48_NGPIO; 461 ws16c48gpio->chip.names = ws16c48_names; 462 ws16c48gpio->chip.get_direction = ws16c48_gpio_get_direction; 463 ws16c48gpio->chip.direction_input = ws16c48_gpio_direction_input; 464 ws16c48gpio->chip.direction_output = ws16c48_gpio_direction_output; 465 ws16c48gpio->chip.get = ws16c48_gpio_get; 466 ws16c48gpio->chip.get_multiple = ws16c48_gpio_get_multiple; 467 ws16c48gpio->chip.set = ws16c48_gpio_set; 468 ws16c48gpio->chip.set_multiple = ws16c48_gpio_set_multiple; 469 470 girq = &ws16c48gpio->chip.irq; 471 gpio_irq_chip_set_chip(girq, &ws16c48_irqchip); 472 /* This will let us handle the parent IRQ in the driver */ 473 girq->parent_handler = NULL; 474 girq->num_parents = 0; 475 girq->parents = NULL; 476 girq->default_type = IRQ_TYPE_NONE; 477 girq->handler = handle_edge_irq; 478 girq->init_hw = ws16c48_irq_init_hw; 479 480 raw_spin_lock_init(&ws16c48gpio->lock); 481 482 err = devm_gpiochip_add_data(dev, &ws16c48gpio->chip, ws16c48gpio); 483 if (err) { 484 dev_err(dev, "GPIO registering failed (%d)\n", err); 485 return err; 486 } 487 488 err = devm_request_irq(dev, irq[id], ws16c48_irq_handler, IRQF_SHARED, 489 name, ws16c48gpio); 490 if (err) { 491 dev_err(dev, "IRQ handler registering failed (%d)\n", err); 492 return err; 493 } 494 495 return 0; 496 } 497 498 static struct isa_driver ws16c48_driver = { 499 .probe = ws16c48_probe, 500 .driver = { 501 .name = "ws16c48" 502 }, 503 }; 504 505 module_isa_driver_with_irq(ws16c48_driver, num_ws16c48, num_irq); 506 507 MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>"); 508 MODULE_DESCRIPTION("WinSystems WS16C48 GPIO driver"); 509 MODULE_LICENSE("GPL v2"); 510