1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO driver for the WinSystems WS16C48 4 * Copyright (C) 2016 William Breathitt Gray 5 */ 6 #include <linux/bitmap.h> 7 #include <linux/device.h> 8 #include <linux/errno.h> 9 #include <linux/gpio/driver.h> 10 #include <linux/io.h> 11 #include <linux/ioport.h> 12 #include <linux/interrupt.h> 13 #include <linux/irqdesc.h> 14 #include <linux/isa.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/moduleparam.h> 18 #include <linux/spinlock.h> 19 #include <linux/types.h> 20 21 #define WS16C48_EXTENT 10 22 #define MAX_NUM_WS16C48 max_num_isa_dev(WS16C48_EXTENT) 23 24 static unsigned int base[MAX_NUM_WS16C48]; 25 static unsigned int num_ws16c48; 26 module_param_hw_array(base, uint, ioport, &num_ws16c48, 0); 27 MODULE_PARM_DESC(base, "WinSystems WS16C48 base addresses"); 28 29 static unsigned int irq[MAX_NUM_WS16C48]; 30 module_param_hw_array(irq, uint, irq, NULL, 0); 31 MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers"); 32 33 /** 34 * struct ws16c48_reg - device register structure 35 * @port: Port 0 through 5 I/O 36 * @int_pending: Interrupt Pending 37 * @page_lock: Register page (Bits 7-6) and I/O port lock (Bits 5-0) 38 * @pol_enab_int_id: Interrupt polarity, enable, and ID 39 */ 40 struct ws16c48_reg { 41 u8 port[6]; 42 u8 int_pending; 43 u8 page_lock; 44 u8 pol_enab_int_id[3]; 45 }; 46 47 /** 48 * struct ws16c48_gpio - GPIO device private data structure 49 * @chip: instance of the gpio_chip 50 * @io_state: bit I/O state (whether bit is set to input or output) 51 * @out_state: output bits state 52 * @lock: synchronization lock to prevent I/O race conditions 53 * @irq_mask: I/O bits affected by interrupts 54 * @flow_mask: IRQ flow type mask for the respective I/O bits 55 * @reg: I/O address offset for the device registers 56 */ 57 struct ws16c48_gpio { 58 struct gpio_chip chip; 59 unsigned char io_state[6]; 60 unsigned char out_state[6]; 61 raw_spinlock_t lock; 62 unsigned long irq_mask; 63 unsigned long flow_mask; 64 struct ws16c48_reg __iomem *reg; 65 }; 66 67 static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 68 { 69 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 70 const unsigned port = offset / 8; 71 const unsigned mask = BIT(offset % 8); 72 73 if (ws16c48gpio->io_state[port] & mask) 74 return GPIO_LINE_DIRECTION_IN; 75 76 return GPIO_LINE_DIRECTION_OUT; 77 } 78 79 static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 80 { 81 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 82 const unsigned port = offset / 8; 83 const unsigned mask = BIT(offset % 8); 84 unsigned long flags; 85 86 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 87 88 ws16c48gpio->io_state[port] |= mask; 89 ws16c48gpio->out_state[port] &= ~mask; 90 iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port); 91 92 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 93 94 return 0; 95 } 96 97 static int ws16c48_gpio_direction_output(struct gpio_chip *chip, 98 unsigned offset, int value) 99 { 100 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 101 const unsigned port = offset / 8; 102 const unsigned mask = BIT(offset % 8); 103 unsigned long flags; 104 105 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 106 107 ws16c48gpio->io_state[port] &= ~mask; 108 if (value) 109 ws16c48gpio->out_state[port] |= mask; 110 else 111 ws16c48gpio->out_state[port] &= ~mask; 112 iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port); 113 114 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 115 116 return 0; 117 } 118 119 static int ws16c48_gpio_get(struct gpio_chip *chip, unsigned offset) 120 { 121 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 122 const unsigned port = offset / 8; 123 const unsigned mask = BIT(offset % 8); 124 unsigned long flags; 125 unsigned port_state; 126 127 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 128 129 /* ensure that GPIO is set for input */ 130 if (!(ws16c48gpio->io_state[port] & mask)) { 131 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 132 return -EINVAL; 133 } 134 135 port_state = ioread8(ws16c48gpio->reg->port + port); 136 137 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 138 139 return !!(port_state & mask); 140 } 141 142 static int ws16c48_gpio_get_multiple(struct gpio_chip *chip, 143 unsigned long *mask, unsigned long *bits) 144 { 145 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 146 unsigned long offset; 147 unsigned long gpio_mask; 148 size_t index; 149 u8 __iomem *port_addr; 150 unsigned long port_state; 151 152 /* clear bits array to a clean slate */ 153 bitmap_zero(bits, chip->ngpio); 154 155 for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) { 156 index = offset / 8; 157 port_addr = ws16c48gpio->reg->port + index; 158 port_state = ioread8(port_addr) & gpio_mask; 159 160 bitmap_set_value8(bits, port_state, offset); 161 } 162 163 return 0; 164 } 165 166 static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 167 { 168 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 169 const unsigned port = offset / 8; 170 const unsigned mask = BIT(offset % 8); 171 unsigned long flags; 172 173 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 174 175 /* ensure that GPIO is set for output */ 176 if (ws16c48gpio->io_state[port] & mask) { 177 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 178 return; 179 } 180 181 if (value) 182 ws16c48gpio->out_state[port] |= mask; 183 else 184 ws16c48gpio->out_state[port] &= ~mask; 185 iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port); 186 187 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 188 } 189 190 static void ws16c48_gpio_set_multiple(struct gpio_chip *chip, 191 unsigned long *mask, unsigned long *bits) 192 { 193 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 194 unsigned long offset; 195 unsigned long gpio_mask; 196 size_t index; 197 u8 __iomem *port_addr; 198 unsigned long bitmask; 199 unsigned long flags; 200 201 for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) { 202 index = offset / 8; 203 port_addr = ws16c48gpio->reg->port + index; 204 205 /* mask out GPIO configured for input */ 206 gpio_mask &= ~ws16c48gpio->io_state[index]; 207 bitmask = bitmap_get_value8(bits, offset) & gpio_mask; 208 209 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 210 211 /* update output state data and set device gpio register */ 212 ws16c48gpio->out_state[index] &= ~gpio_mask; 213 ws16c48gpio->out_state[index] |= bitmask; 214 iowrite8(ws16c48gpio->out_state[index], port_addr); 215 216 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 217 } 218 } 219 220 static void ws16c48_irq_ack(struct irq_data *data) 221 { 222 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 223 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 224 const unsigned long offset = irqd_to_hwirq(data); 225 const unsigned port = offset / 8; 226 const unsigned mask = BIT(offset % 8); 227 unsigned long flags; 228 unsigned port_state; 229 230 /* only the first 3 ports support interrupts */ 231 if (port > 2) 232 return; 233 234 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 235 236 port_state = ws16c48gpio->irq_mask >> (8*port); 237 238 /* Select Register Page 2; Unlock all I/O ports */ 239 iowrite8(0x80, &ws16c48gpio->reg->page_lock); 240 241 /* Clear pending interrupt */ 242 iowrite8(port_state & ~mask, ws16c48gpio->reg->pol_enab_int_id + port); 243 iowrite8(port_state | mask, ws16c48gpio->reg->pol_enab_int_id + port); 244 245 /* Select Register Page 3; Unlock all I/O ports */ 246 iowrite8(0xC0, &ws16c48gpio->reg->page_lock); 247 248 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 249 } 250 251 static void ws16c48_irq_mask(struct irq_data *data) 252 { 253 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 254 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 255 const unsigned long offset = irqd_to_hwirq(data); 256 const unsigned long mask = BIT(offset); 257 const unsigned port = offset / 8; 258 unsigned long flags; 259 unsigned long port_state; 260 261 /* only the first 3 ports support interrupts */ 262 if (port > 2) 263 return; 264 265 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 266 267 ws16c48gpio->irq_mask &= ~mask; 268 port_state = ws16c48gpio->irq_mask >> (8 * port); 269 270 /* Select Register Page 2; Unlock all I/O ports */ 271 iowrite8(0x80, &ws16c48gpio->reg->page_lock); 272 273 /* Disable interrupt */ 274 iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port); 275 276 /* Select Register Page 3; Unlock all I/O ports */ 277 iowrite8(0xC0, &ws16c48gpio->reg->page_lock); 278 279 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 280 } 281 282 static void ws16c48_irq_unmask(struct irq_data *data) 283 { 284 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 285 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 286 const unsigned long offset = irqd_to_hwirq(data); 287 const unsigned long mask = BIT(offset); 288 const unsigned port = offset / 8; 289 unsigned long flags; 290 unsigned long port_state; 291 292 /* only the first 3 ports support interrupts */ 293 if (port > 2) 294 return; 295 296 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 297 298 ws16c48gpio->irq_mask |= mask; 299 port_state = ws16c48gpio->irq_mask >> (8 * port); 300 301 /* Select Register Page 2; Unlock all I/O ports */ 302 iowrite8(0x80, &ws16c48gpio->reg->page_lock); 303 304 /* Enable interrupt */ 305 iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port); 306 307 /* Select Register Page 3; Unlock all I/O ports */ 308 iowrite8(0xC0, &ws16c48gpio->reg->page_lock); 309 310 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 311 } 312 313 static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type) 314 { 315 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 316 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 317 const unsigned long offset = irqd_to_hwirq(data); 318 const unsigned long mask = BIT(offset); 319 const unsigned port = offset / 8; 320 unsigned long flags; 321 unsigned long port_state; 322 323 /* only the first 3 ports support interrupts */ 324 if (port > 2) 325 return -EINVAL; 326 327 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 328 329 switch (flow_type) { 330 case IRQ_TYPE_NONE: 331 break; 332 case IRQ_TYPE_EDGE_RISING: 333 ws16c48gpio->flow_mask |= mask; 334 break; 335 case IRQ_TYPE_EDGE_FALLING: 336 ws16c48gpio->flow_mask &= ~mask; 337 break; 338 default: 339 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 340 return -EINVAL; 341 } 342 343 port_state = ws16c48gpio->flow_mask >> (8 * port); 344 345 /* Select Register Page 1; Unlock all I/O ports */ 346 iowrite8(0x40, &ws16c48gpio->reg->page_lock); 347 348 /* Set interrupt polarity */ 349 iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port); 350 351 /* Select Register Page 3; Unlock all I/O ports */ 352 iowrite8(0xC0, &ws16c48gpio->reg->page_lock); 353 354 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 355 356 return 0; 357 } 358 359 static struct irq_chip ws16c48_irqchip = { 360 .name = "ws16c48", 361 .irq_ack = ws16c48_irq_ack, 362 .irq_mask = ws16c48_irq_mask, 363 .irq_unmask = ws16c48_irq_unmask, 364 .irq_set_type = ws16c48_irq_set_type 365 }; 366 367 static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id) 368 { 369 struct ws16c48_gpio *const ws16c48gpio = dev_id; 370 struct gpio_chip *const chip = &ws16c48gpio->chip; 371 struct ws16c48_reg __iomem *const reg = ws16c48gpio->reg; 372 unsigned long int_pending; 373 unsigned long port; 374 unsigned long int_id; 375 unsigned long gpio; 376 377 int_pending = ioread8(®->int_pending) & 0x7; 378 if (!int_pending) 379 return IRQ_NONE; 380 381 /* loop until all pending interrupts are handled */ 382 do { 383 for_each_set_bit(port, &int_pending, 3) { 384 int_id = ioread8(reg->pol_enab_int_id + port); 385 for_each_set_bit(gpio, &int_id, 8) 386 generic_handle_domain_irq(chip->irq.domain, 387 gpio + 8*port); 388 } 389 390 int_pending = ioread8(®->int_pending) & 0x7; 391 } while (int_pending); 392 393 return IRQ_HANDLED; 394 } 395 396 #define WS16C48_NGPIO 48 397 static const char *ws16c48_names[WS16C48_NGPIO] = { 398 "Port 0 Bit 0", "Port 0 Bit 1", "Port 0 Bit 2", "Port 0 Bit 3", 399 "Port 0 Bit 4", "Port 0 Bit 5", "Port 0 Bit 6", "Port 0 Bit 7", 400 "Port 1 Bit 0", "Port 1 Bit 1", "Port 1 Bit 2", "Port 1 Bit 3", 401 "Port 1 Bit 4", "Port 1 Bit 5", "Port 1 Bit 6", "Port 1 Bit 7", 402 "Port 2 Bit 0", "Port 2 Bit 1", "Port 2 Bit 2", "Port 2 Bit 3", 403 "Port 2 Bit 4", "Port 2 Bit 5", "Port 2 Bit 6", "Port 2 Bit 7", 404 "Port 3 Bit 0", "Port 3 Bit 1", "Port 3 Bit 2", "Port 3 Bit 3", 405 "Port 3 Bit 4", "Port 3 Bit 5", "Port 3 Bit 6", "Port 3 Bit 7", 406 "Port 4 Bit 0", "Port 4 Bit 1", "Port 4 Bit 2", "Port 4 Bit 3", 407 "Port 4 Bit 4", "Port 4 Bit 5", "Port 4 Bit 6", "Port 4 Bit 7", 408 "Port 5 Bit 0", "Port 5 Bit 1", "Port 5 Bit 2", "Port 5 Bit 3", 409 "Port 5 Bit 4", "Port 5 Bit 5", "Port 5 Bit 6", "Port 5 Bit 7" 410 }; 411 412 static int ws16c48_irq_init_hw(struct gpio_chip *gc) 413 { 414 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(gc); 415 416 /* Select Register Page 2; Unlock all I/O ports */ 417 iowrite8(0x80, &ws16c48gpio->reg->page_lock); 418 419 /* Disable interrupts for all lines */ 420 iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[0]); 421 iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[1]); 422 iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[2]); 423 424 /* Select Register Page 3; Unlock all I/O ports */ 425 iowrite8(0xC0, &ws16c48gpio->reg->page_lock); 426 427 return 0; 428 } 429 430 static int ws16c48_probe(struct device *dev, unsigned int id) 431 { 432 struct ws16c48_gpio *ws16c48gpio; 433 const char *const name = dev_name(dev); 434 struct gpio_irq_chip *girq; 435 int err; 436 437 ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL); 438 if (!ws16c48gpio) 439 return -ENOMEM; 440 441 if (!devm_request_region(dev, base[id], WS16C48_EXTENT, name)) { 442 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n", 443 base[id], base[id] + WS16C48_EXTENT); 444 return -EBUSY; 445 } 446 447 ws16c48gpio->reg = devm_ioport_map(dev, base[id], WS16C48_EXTENT); 448 if (!ws16c48gpio->reg) 449 return -ENOMEM; 450 451 ws16c48gpio->chip.label = name; 452 ws16c48gpio->chip.parent = dev; 453 ws16c48gpio->chip.owner = THIS_MODULE; 454 ws16c48gpio->chip.base = -1; 455 ws16c48gpio->chip.ngpio = WS16C48_NGPIO; 456 ws16c48gpio->chip.names = ws16c48_names; 457 ws16c48gpio->chip.get_direction = ws16c48_gpio_get_direction; 458 ws16c48gpio->chip.direction_input = ws16c48_gpio_direction_input; 459 ws16c48gpio->chip.direction_output = ws16c48_gpio_direction_output; 460 ws16c48gpio->chip.get = ws16c48_gpio_get; 461 ws16c48gpio->chip.get_multiple = ws16c48_gpio_get_multiple; 462 ws16c48gpio->chip.set = ws16c48_gpio_set; 463 ws16c48gpio->chip.set_multiple = ws16c48_gpio_set_multiple; 464 465 girq = &ws16c48gpio->chip.irq; 466 girq->chip = &ws16c48_irqchip; 467 /* This will let us handle the parent IRQ in the driver */ 468 girq->parent_handler = NULL; 469 girq->num_parents = 0; 470 girq->parents = NULL; 471 girq->default_type = IRQ_TYPE_NONE; 472 girq->handler = handle_edge_irq; 473 girq->init_hw = ws16c48_irq_init_hw; 474 475 raw_spin_lock_init(&ws16c48gpio->lock); 476 477 err = devm_gpiochip_add_data(dev, &ws16c48gpio->chip, ws16c48gpio); 478 if (err) { 479 dev_err(dev, "GPIO registering failed (%d)\n", err); 480 return err; 481 } 482 483 err = devm_request_irq(dev, irq[id], ws16c48_irq_handler, IRQF_SHARED, 484 name, ws16c48gpio); 485 if (err) { 486 dev_err(dev, "IRQ handler registering failed (%d)\n", err); 487 return err; 488 } 489 490 return 0; 491 } 492 493 static struct isa_driver ws16c48_driver = { 494 .probe = ws16c48_probe, 495 .driver = { 496 .name = "ws16c48" 497 }, 498 }; 499 500 module_isa_driver(ws16c48_driver, num_ws16c48); 501 502 MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>"); 503 MODULE_DESCRIPTION("WinSystems WS16C48 GPIO driver"); 504 MODULE_LICENSE("GPL v2"); 505