1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO driver for the WinSystems WS16C48 4 * Copyright (C) 2016 William Breathitt Gray 5 */ 6 #include <linux/bitmap.h> 7 #include <linux/bitops.h> 8 #include <linux/device.h> 9 #include <linux/errno.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/io.h> 12 #include <linux/ioport.h> 13 #include <linux/interrupt.h> 14 #include <linux/irqdesc.h> 15 #include <linux/isa.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/moduleparam.h> 19 #include <linux/spinlock.h> 20 21 #define WS16C48_EXTENT 16 22 #define MAX_NUM_WS16C48 max_num_isa_dev(WS16C48_EXTENT) 23 24 static unsigned int base[MAX_NUM_WS16C48]; 25 static unsigned int num_ws16c48; 26 module_param_hw_array(base, uint, ioport, &num_ws16c48, 0); 27 MODULE_PARM_DESC(base, "WinSystems WS16C48 base addresses"); 28 29 static unsigned int irq[MAX_NUM_WS16C48]; 30 module_param_hw_array(irq, uint, irq, NULL, 0); 31 MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers"); 32 33 /** 34 * struct ws16c48_gpio - GPIO device private data structure 35 * @chip: instance of the gpio_chip 36 * @io_state: bit I/O state (whether bit is set to input or output) 37 * @out_state: output bits state 38 * @lock: synchronization lock to prevent I/O race conditions 39 * @irq_mask: I/O bits affected by interrupts 40 * @flow_mask: IRQ flow type mask for the respective I/O bits 41 * @base: base port address of the GPIO device 42 */ 43 struct ws16c48_gpio { 44 struct gpio_chip chip; 45 unsigned char io_state[6]; 46 unsigned char out_state[6]; 47 raw_spinlock_t lock; 48 unsigned long irq_mask; 49 unsigned long flow_mask; 50 unsigned base; 51 }; 52 53 static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 54 { 55 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 56 const unsigned port = offset / 8; 57 const unsigned mask = BIT(offset % 8); 58 59 if (ws16c48gpio->io_state[port] & mask) 60 return GPIO_LINE_DIRECTION_IN; 61 62 return GPIO_LINE_DIRECTION_OUT; 63 } 64 65 static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 66 { 67 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 68 const unsigned port = offset / 8; 69 const unsigned mask = BIT(offset % 8); 70 unsigned long flags; 71 72 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 73 74 ws16c48gpio->io_state[port] |= mask; 75 ws16c48gpio->out_state[port] &= ~mask; 76 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port); 77 78 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 79 80 return 0; 81 } 82 83 static int ws16c48_gpio_direction_output(struct gpio_chip *chip, 84 unsigned offset, int value) 85 { 86 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 87 const unsigned port = offset / 8; 88 const unsigned mask = BIT(offset % 8); 89 unsigned long flags; 90 91 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 92 93 ws16c48gpio->io_state[port] &= ~mask; 94 if (value) 95 ws16c48gpio->out_state[port] |= mask; 96 else 97 ws16c48gpio->out_state[port] &= ~mask; 98 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port); 99 100 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 101 102 return 0; 103 } 104 105 static int ws16c48_gpio_get(struct gpio_chip *chip, unsigned offset) 106 { 107 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 108 const unsigned port = offset / 8; 109 const unsigned mask = BIT(offset % 8); 110 unsigned long flags; 111 unsigned port_state; 112 113 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 114 115 /* ensure that GPIO is set for input */ 116 if (!(ws16c48gpio->io_state[port] & mask)) { 117 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 118 return -EINVAL; 119 } 120 121 port_state = inb(ws16c48gpio->base + port); 122 123 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 124 125 return !!(port_state & mask); 126 } 127 128 static int ws16c48_gpio_get_multiple(struct gpio_chip *chip, 129 unsigned long *mask, unsigned long *bits) 130 { 131 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 132 const unsigned int gpio_reg_size = 8; 133 size_t i; 134 const size_t num_ports = chip->ngpio / gpio_reg_size; 135 unsigned int bits_offset; 136 size_t word_index; 137 unsigned int word_offset; 138 unsigned long word_mask; 139 const unsigned long port_mask = GENMASK(gpio_reg_size - 1, 0); 140 unsigned long port_state; 141 142 /* clear bits array to a clean slate */ 143 bitmap_zero(bits, chip->ngpio); 144 145 /* get bits are evaluated a gpio port register at a time */ 146 for (i = 0; i < num_ports; i++) { 147 /* gpio offset in bits array */ 148 bits_offset = i * gpio_reg_size; 149 150 /* word index for bits array */ 151 word_index = BIT_WORD(bits_offset); 152 153 /* gpio offset within current word of bits array */ 154 word_offset = bits_offset % BITS_PER_LONG; 155 156 /* mask of get bits for current gpio within current word */ 157 word_mask = mask[word_index] & (port_mask << word_offset); 158 if (!word_mask) { 159 /* no get bits in this port so skip to next one */ 160 continue; 161 } 162 163 /* read bits from current gpio port */ 164 port_state = inb(ws16c48gpio->base + i); 165 166 /* store acquired bits at respective bits array offset */ 167 bits[word_index] |= (port_state << word_offset) & word_mask; 168 } 169 170 return 0; 171 } 172 173 static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 174 { 175 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 176 const unsigned port = offset / 8; 177 const unsigned mask = BIT(offset % 8); 178 unsigned long flags; 179 180 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 181 182 /* ensure that GPIO is set for output */ 183 if (ws16c48gpio->io_state[port] & mask) { 184 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 185 return; 186 } 187 188 if (value) 189 ws16c48gpio->out_state[port] |= mask; 190 else 191 ws16c48gpio->out_state[port] &= ~mask; 192 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port); 193 194 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 195 } 196 197 static void ws16c48_gpio_set_multiple(struct gpio_chip *chip, 198 unsigned long *mask, unsigned long *bits) 199 { 200 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 201 unsigned int i; 202 const unsigned int gpio_reg_size = 8; 203 unsigned int port; 204 unsigned int iomask; 205 unsigned int bitmask; 206 unsigned long flags; 207 208 /* set bits are evaluated a gpio register size at a time */ 209 for (i = 0; i < chip->ngpio; i += gpio_reg_size) { 210 /* no more set bits in this mask word; skip to the next word */ 211 if (!mask[BIT_WORD(i)]) { 212 i = (BIT_WORD(i) + 1) * BITS_PER_LONG - gpio_reg_size; 213 continue; 214 } 215 216 port = i / gpio_reg_size; 217 218 /* mask out GPIO configured for input */ 219 iomask = mask[BIT_WORD(i)] & ~ws16c48gpio->io_state[port]; 220 bitmask = iomask & bits[BIT_WORD(i)]; 221 222 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 223 224 /* update output state data and set device gpio register */ 225 ws16c48gpio->out_state[port] &= ~iomask; 226 ws16c48gpio->out_state[port] |= bitmask; 227 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port); 228 229 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 230 231 /* prepare for next gpio register set */ 232 mask[BIT_WORD(i)] >>= gpio_reg_size; 233 bits[BIT_WORD(i)] >>= gpio_reg_size; 234 } 235 } 236 237 static void ws16c48_irq_ack(struct irq_data *data) 238 { 239 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 240 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 241 const unsigned long offset = irqd_to_hwirq(data); 242 const unsigned port = offset / 8; 243 const unsigned mask = BIT(offset % 8); 244 unsigned long flags; 245 unsigned port_state; 246 247 /* only the first 3 ports support interrupts */ 248 if (port > 2) 249 return; 250 251 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 252 253 port_state = ws16c48gpio->irq_mask >> (8*port); 254 255 outb(0x80, ws16c48gpio->base + 7); 256 outb(port_state & ~mask, ws16c48gpio->base + 8 + port); 257 outb(port_state | mask, ws16c48gpio->base + 8 + port); 258 outb(0xC0, ws16c48gpio->base + 7); 259 260 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 261 } 262 263 static void ws16c48_irq_mask(struct irq_data *data) 264 { 265 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 266 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 267 const unsigned long offset = irqd_to_hwirq(data); 268 const unsigned long mask = BIT(offset); 269 const unsigned port = offset / 8; 270 unsigned long flags; 271 272 /* only the first 3 ports support interrupts */ 273 if (port > 2) 274 return; 275 276 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 277 278 ws16c48gpio->irq_mask &= ~mask; 279 280 outb(0x80, ws16c48gpio->base + 7); 281 outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port); 282 outb(0xC0, ws16c48gpio->base + 7); 283 284 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 285 } 286 287 static void ws16c48_irq_unmask(struct irq_data *data) 288 { 289 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 290 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 291 const unsigned long offset = irqd_to_hwirq(data); 292 const unsigned long mask = BIT(offset); 293 const unsigned port = offset / 8; 294 unsigned long flags; 295 296 /* only the first 3 ports support interrupts */ 297 if (port > 2) 298 return; 299 300 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 301 302 ws16c48gpio->irq_mask |= mask; 303 304 outb(0x80, ws16c48gpio->base + 7); 305 outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port); 306 outb(0xC0, ws16c48gpio->base + 7); 307 308 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 309 } 310 311 static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type) 312 { 313 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 314 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); 315 const unsigned long offset = irqd_to_hwirq(data); 316 const unsigned long mask = BIT(offset); 317 const unsigned port = offset / 8; 318 unsigned long flags; 319 320 /* only the first 3 ports support interrupts */ 321 if (port > 2) 322 return -EINVAL; 323 324 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); 325 326 switch (flow_type) { 327 case IRQ_TYPE_NONE: 328 break; 329 case IRQ_TYPE_EDGE_RISING: 330 ws16c48gpio->flow_mask |= mask; 331 break; 332 case IRQ_TYPE_EDGE_FALLING: 333 ws16c48gpio->flow_mask &= ~mask; 334 break; 335 default: 336 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 337 return -EINVAL; 338 } 339 340 outb(0x40, ws16c48gpio->base + 7); 341 outb(ws16c48gpio->flow_mask >> (8*port), ws16c48gpio->base + 8 + port); 342 outb(0xC0, ws16c48gpio->base + 7); 343 344 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); 345 346 return 0; 347 } 348 349 static struct irq_chip ws16c48_irqchip = { 350 .name = "ws16c48", 351 .irq_ack = ws16c48_irq_ack, 352 .irq_mask = ws16c48_irq_mask, 353 .irq_unmask = ws16c48_irq_unmask, 354 .irq_set_type = ws16c48_irq_set_type 355 }; 356 357 static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id) 358 { 359 struct ws16c48_gpio *const ws16c48gpio = dev_id; 360 struct gpio_chip *const chip = &ws16c48gpio->chip; 361 unsigned long int_pending; 362 unsigned long port; 363 unsigned long int_id; 364 unsigned long gpio; 365 366 int_pending = inb(ws16c48gpio->base + 6) & 0x7; 367 if (!int_pending) 368 return IRQ_NONE; 369 370 /* loop until all pending interrupts are handled */ 371 do { 372 for_each_set_bit(port, &int_pending, 3) { 373 int_id = inb(ws16c48gpio->base + 8 + port); 374 for_each_set_bit(gpio, &int_id, 8) 375 generic_handle_irq(irq_find_mapping( 376 chip->irq.domain, gpio + 8*port)); 377 } 378 379 int_pending = inb(ws16c48gpio->base + 6) & 0x7; 380 } while (int_pending); 381 382 return IRQ_HANDLED; 383 } 384 385 #define WS16C48_NGPIO 48 386 static const char *ws16c48_names[WS16C48_NGPIO] = { 387 "Port 0 Bit 0", "Port 0 Bit 1", "Port 0 Bit 2", "Port 0 Bit 3", 388 "Port 0 Bit 4", "Port 0 Bit 5", "Port 0 Bit 6", "Port 0 Bit 7", 389 "Port 1 Bit 0", "Port 1 Bit 1", "Port 1 Bit 2", "Port 1 Bit 3", 390 "Port 1 Bit 4", "Port 1 Bit 5", "Port 1 Bit 6", "Port 1 Bit 7", 391 "Port 2 Bit 0", "Port 2 Bit 1", "Port 2 Bit 2", "Port 2 Bit 3", 392 "Port 2 Bit 4", "Port 2 Bit 5", "Port 2 Bit 6", "Port 2 Bit 7", 393 "Port 3 Bit 0", "Port 3 Bit 1", "Port 3 Bit 2", "Port 3 Bit 3", 394 "Port 3 Bit 4", "Port 3 Bit 5", "Port 3 Bit 6", "Port 3 Bit 7", 395 "Port 4 Bit 0", "Port 4 Bit 1", "Port 4 Bit 2", "Port 4 Bit 3", 396 "Port 4 Bit 4", "Port 4 Bit 5", "Port 4 Bit 6", "Port 4 Bit 7", 397 "Port 5 Bit 0", "Port 5 Bit 1", "Port 5 Bit 2", "Port 5 Bit 3", 398 "Port 5 Bit 4", "Port 5 Bit 5", "Port 5 Bit 6", "Port 5 Bit 7" 399 }; 400 401 static int ws16c48_probe(struct device *dev, unsigned int id) 402 { 403 struct ws16c48_gpio *ws16c48gpio; 404 const char *const name = dev_name(dev); 405 int err; 406 407 ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL); 408 if (!ws16c48gpio) 409 return -ENOMEM; 410 411 if (!devm_request_region(dev, base[id], WS16C48_EXTENT, name)) { 412 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n", 413 base[id], base[id] + WS16C48_EXTENT); 414 return -EBUSY; 415 } 416 417 ws16c48gpio->chip.label = name; 418 ws16c48gpio->chip.parent = dev; 419 ws16c48gpio->chip.owner = THIS_MODULE; 420 ws16c48gpio->chip.base = -1; 421 ws16c48gpio->chip.ngpio = WS16C48_NGPIO; 422 ws16c48gpio->chip.names = ws16c48_names; 423 ws16c48gpio->chip.get_direction = ws16c48_gpio_get_direction; 424 ws16c48gpio->chip.direction_input = ws16c48_gpio_direction_input; 425 ws16c48gpio->chip.direction_output = ws16c48_gpio_direction_output; 426 ws16c48gpio->chip.get = ws16c48_gpio_get; 427 ws16c48gpio->chip.get_multiple = ws16c48_gpio_get_multiple; 428 ws16c48gpio->chip.set = ws16c48_gpio_set; 429 ws16c48gpio->chip.set_multiple = ws16c48_gpio_set_multiple; 430 ws16c48gpio->base = base[id]; 431 432 raw_spin_lock_init(&ws16c48gpio->lock); 433 434 err = devm_gpiochip_add_data(dev, &ws16c48gpio->chip, ws16c48gpio); 435 if (err) { 436 dev_err(dev, "GPIO registering failed (%d)\n", err); 437 return err; 438 } 439 440 /* Disable IRQ by default */ 441 outb(0x80, base[id] + 7); 442 outb(0, base[id] + 8); 443 outb(0, base[id] + 9); 444 outb(0, base[id] + 10); 445 outb(0xC0, base[id] + 7); 446 447 err = gpiochip_irqchip_add(&ws16c48gpio->chip, &ws16c48_irqchip, 0, 448 handle_edge_irq, IRQ_TYPE_NONE); 449 if (err) { 450 dev_err(dev, "Could not add irqchip (%d)\n", err); 451 return err; 452 } 453 454 err = devm_request_irq(dev, irq[id], ws16c48_irq_handler, IRQF_SHARED, 455 name, ws16c48gpio); 456 if (err) { 457 dev_err(dev, "IRQ handler registering failed (%d)\n", err); 458 return err; 459 } 460 461 return 0; 462 } 463 464 static struct isa_driver ws16c48_driver = { 465 .probe = ws16c48_probe, 466 .driver = { 467 .name = "ws16c48" 468 }, 469 }; 470 471 module_isa_driver(ws16c48_driver, num_ws16c48); 472 473 MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>"); 474 MODULE_DESCRIPTION("WinSystems WS16C48 GPIO driver"); 475 MODULE_LICENSE("GPL v2"); 476