1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * GPIO interface for Winbond Super I/O chips 4 * Currently, only W83627UHG (Nuvoton NCT6627UD) is supported. 5 * 6 * Author: Maciej S. Szmigiero <mail@maciej.szmigiero.name> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/gpio/driver.h> 12 #include <linux/ioport.h> 13 #include <linux/isa.h> 14 #include <linux/module.h> 15 16 #define WB_GPIO_DRIVER_NAME KBUILD_MODNAME 17 18 #define WB_SIO_BASE 0x2e 19 #define WB_SIO_BASE_HIGH 0x4e 20 21 #define WB_SIO_EXT_ENTER_KEY 0x87 22 #define WB_SIO_EXT_EXIT_KEY 0xaa 23 24 /* global chip registers */ 25 26 #define WB_SIO_REG_LOGICAL 0x07 27 28 #define WB_SIO_REG_CHIP_MSB 0x20 29 #define WB_SIO_REG_CHIP_LSB 0x21 30 31 #define WB_SIO_CHIP_ID_W83627UHG 0xa230 32 #define WB_SIO_CHIP_ID_W83627UHG_MASK GENMASK(15, 4) 33 34 #define WB_SIO_REG_DPD 0x22 35 #define WB_SIO_REG_DPD_UARTA 4 36 #define WB_SIO_REG_DPD_UARTB 5 37 38 #define WB_SIO_REG_IDPD 0x23 39 #define WB_SIO_REG_IDPD_UARTC 4 40 #define WB_SIO_REG_IDPD_UARTD 5 41 #define WB_SIO_REG_IDPD_UARTE 6 42 #define WB_SIO_REG_IDPD_UARTF 7 43 44 #define WB_SIO_REG_GLOBAL_OPT 0x24 45 #define WB_SIO_REG_GO_ENFDC 1 46 47 #define WB_SIO_REG_OVTGPIO3456 0x29 48 #define WB_SIO_REG_OG3456_G3PP 3 49 #define WB_SIO_REG_OG3456_G4PP 4 50 #define WB_SIO_REG_OG3456_G5PP 5 51 #define WB_SIO_REG_OG3456_G6PP 7 52 53 #define WB_SIO_REG_I2C_PS 0x2a 54 #define WB_SIO_REG_I2CPS_I2CFS 1 55 56 #define WB_SIO_REG_GPIO1_MF 0x2c 57 #define WB_SIO_REG_G1MF_G1PP 6 58 #define WB_SIO_REG_G1MF_G2PP 7 59 #define WB_SIO_REG_G1MF_FS_MASK GENMASK(1, 0) 60 #define WB_SIO_REG_G1MF_FS_IR_OFF 0 61 #define WB_SIO_REG_G1MF_FS_IR 1 62 #define WB_SIO_REG_G1MF_FS_GPIO1 2 63 #define WB_SIO_REG_G1MF_FS_UARTB 3 64 65 /* not an actual device number, just a value meaning 'no device' */ 66 #define WB_SIO_DEV_NONE 0xff 67 68 /* registers with offsets >= 0x30 are specific for a particular device */ 69 70 /* UART B logical device */ 71 #define WB_SIO_DEV_UARTB 0x03 72 #define WB_SIO_UARTB_REG_ENABLE 0x30 73 #define WB_SIO_UARTB_ENABLE_ON 0 74 75 /* UART C logical device */ 76 #define WB_SIO_DEV_UARTC 0x06 77 #define WB_SIO_UARTC_REG_ENABLE 0x30 78 #define WB_SIO_UARTC_ENABLE_ON 0 79 80 /* GPIO3, GPIO4 logical device */ 81 #define WB_SIO_DEV_GPIO34 0x07 82 #define WB_SIO_GPIO34_REG_ENABLE 0x30 83 #define WB_SIO_GPIO34_ENABLE_3 0 84 #define WB_SIO_GPIO34_ENABLE_4 1 85 #define WB_SIO_GPIO34_REG_IO3 0xe0 86 #define WB_SIO_GPIO34_REG_DATA3 0xe1 87 #define WB_SIO_GPIO34_REG_INV3 0xe2 88 #define WB_SIO_GPIO34_REG_IO4 0xe4 89 #define WB_SIO_GPIO34_REG_DATA4 0xe5 90 #define WB_SIO_GPIO34_REG_INV4 0xe6 91 92 /* WDTO, PLED, GPIO5, GPIO6 logical device */ 93 #define WB_SIO_DEV_WDGPIO56 0x08 94 #define WB_SIO_WDGPIO56_REG_ENABLE 0x30 95 #define WB_SIO_WDGPIO56_ENABLE_5 1 96 #define WB_SIO_WDGPIO56_ENABLE_6 2 97 #define WB_SIO_WDGPIO56_REG_IO5 0xe0 98 #define WB_SIO_WDGPIO56_REG_DATA5 0xe1 99 #define WB_SIO_WDGPIO56_REG_INV5 0xe2 100 #define WB_SIO_WDGPIO56_REG_IO6 0xe4 101 #define WB_SIO_WDGPIO56_REG_DATA6 0xe5 102 #define WB_SIO_WDGPIO56_REG_INV6 0xe6 103 104 /* GPIO1, GPIO2, SUSLED logical device */ 105 #define WB_SIO_DEV_GPIO12 0x09 106 #define WB_SIO_GPIO12_REG_ENABLE 0x30 107 #define WB_SIO_GPIO12_ENABLE_1 0 108 #define WB_SIO_GPIO12_ENABLE_2 1 109 #define WB_SIO_GPIO12_REG_IO1 0xe0 110 #define WB_SIO_GPIO12_REG_DATA1 0xe1 111 #define WB_SIO_GPIO12_REG_INV1 0xe2 112 #define WB_SIO_GPIO12_REG_IO2 0xe4 113 #define WB_SIO_GPIO12_REG_DATA2 0xe5 114 #define WB_SIO_GPIO12_REG_INV2 0xe6 115 116 /* UART D logical device */ 117 #define WB_SIO_DEV_UARTD 0x0d 118 #define WB_SIO_UARTD_REG_ENABLE 0x30 119 #define WB_SIO_UARTD_ENABLE_ON 0 120 121 /* UART E logical device */ 122 #define WB_SIO_DEV_UARTE 0x0e 123 #define WB_SIO_UARTE_REG_ENABLE 0x30 124 #define WB_SIO_UARTE_ENABLE_ON 0 125 126 /* 127 * for a description what a particular field of this struct means please see 128 * a description of the relevant module parameter at the bottom of this file 129 */ 130 struct winbond_gpio_params { 131 unsigned long base; 132 unsigned long gpios; 133 unsigned long ppgpios; 134 unsigned long odgpios; 135 bool pledgpio; 136 bool beepgpio; 137 bool i2cgpio; 138 }; 139 140 static struct winbond_gpio_params params; 141 142 static int winbond_sio_enter(unsigned long base) 143 { 144 if (!request_muxed_region(base, 2, WB_GPIO_DRIVER_NAME)) 145 return -EBUSY; 146 147 /* 148 * datasheet says two successive writes of the "key" value are needed 149 * in order for chip to enter the "Extended Function Mode" 150 */ 151 outb(WB_SIO_EXT_ENTER_KEY, base); 152 outb(WB_SIO_EXT_ENTER_KEY, base); 153 154 return 0; 155 } 156 157 static void winbond_sio_select_logical(unsigned long base, u8 dev) 158 { 159 outb(WB_SIO_REG_LOGICAL, base); 160 outb(dev, base + 1); 161 } 162 163 static void winbond_sio_leave(unsigned long base) 164 { 165 outb(WB_SIO_EXT_EXIT_KEY, base); 166 167 release_region(base, 2); 168 } 169 170 static void winbond_sio_reg_write(unsigned long base, u8 reg, u8 data) 171 { 172 outb(reg, base); 173 outb(data, base + 1); 174 } 175 176 static u8 winbond_sio_reg_read(unsigned long base, u8 reg) 177 { 178 outb(reg, base); 179 return inb(base + 1); 180 } 181 182 static void winbond_sio_reg_bset(unsigned long base, u8 reg, u8 bit) 183 { 184 u8 val; 185 186 val = winbond_sio_reg_read(base, reg); 187 val |= BIT(bit); 188 winbond_sio_reg_write(base, reg, val); 189 } 190 191 static void winbond_sio_reg_bclear(unsigned long base, u8 reg, u8 bit) 192 { 193 u8 val; 194 195 val = winbond_sio_reg_read(base, reg); 196 val &= ~BIT(bit); 197 winbond_sio_reg_write(base, reg, val); 198 } 199 200 static bool winbond_sio_reg_btest(unsigned long base, u8 reg, u8 bit) 201 { 202 return winbond_sio_reg_read(base, reg) & BIT(bit); 203 } 204 205 /** 206 * struct winbond_gpio_port_conflict - possibly conflicting device information 207 * @name: device name (NULL means no conflicting device defined) 208 * @dev: Super I/O logical device number where the testreg register 209 * is located (or WB_SIO_DEV_NONE - don't select any 210 * logical device) 211 * @testreg: register number where the testbit bit is located 212 * @testbit: index of a bit to check whether an actual conflict exists 213 * @warnonly: if set then a conflict isn't fatal (just warn about it), 214 * otherwise disable the particular GPIO port if a conflict 215 * is detected 216 */ 217 struct winbond_gpio_port_conflict { 218 const char *name; 219 u8 dev; 220 u8 testreg; 221 u8 testbit; 222 bool warnonly; 223 }; 224 225 /** 226 * struct winbond_gpio_info - information about a particular GPIO port (device) 227 * @dev: Super I/O logical device number of the registers 228 * specified below 229 * @enablereg: port enable bit register number 230 * @enablebit: index of a port enable bit 231 * @outputreg: output driver mode bit register number 232 * @outputppbit: index of a push-pull output driver mode bit 233 * @ioreg: data direction register number 234 * @invreg: pin data inversion register number 235 * @datareg: pin data register number 236 * @conflict: description of a device that possibly conflicts with 237 * this port 238 */ 239 struct winbond_gpio_info { 240 u8 dev; 241 u8 enablereg; 242 u8 enablebit; 243 u8 outputreg; 244 u8 outputppbit; 245 u8 ioreg; 246 u8 invreg; 247 u8 datareg; 248 struct winbond_gpio_port_conflict conflict; 249 }; 250 251 static const struct winbond_gpio_info winbond_gpio_infos[6] = { 252 { /* 0 */ 253 .dev = WB_SIO_DEV_GPIO12, 254 .enablereg = WB_SIO_GPIO12_REG_ENABLE, 255 .enablebit = WB_SIO_GPIO12_ENABLE_1, 256 .outputreg = WB_SIO_REG_GPIO1_MF, 257 .outputppbit = WB_SIO_REG_G1MF_G1PP, 258 .ioreg = WB_SIO_GPIO12_REG_IO1, 259 .invreg = WB_SIO_GPIO12_REG_INV1, 260 .datareg = WB_SIO_GPIO12_REG_DATA1, 261 .conflict = { 262 .name = "UARTB", 263 .dev = WB_SIO_DEV_UARTB, 264 .testreg = WB_SIO_UARTB_REG_ENABLE, 265 .testbit = WB_SIO_UARTB_ENABLE_ON, 266 .warnonly = true 267 } 268 }, 269 { /* 1 */ 270 .dev = WB_SIO_DEV_GPIO12, 271 .enablereg = WB_SIO_GPIO12_REG_ENABLE, 272 .enablebit = WB_SIO_GPIO12_ENABLE_2, 273 .outputreg = WB_SIO_REG_GPIO1_MF, 274 .outputppbit = WB_SIO_REG_G1MF_G2PP, 275 .ioreg = WB_SIO_GPIO12_REG_IO2, 276 .invreg = WB_SIO_GPIO12_REG_INV2, 277 .datareg = WB_SIO_GPIO12_REG_DATA2 278 /* special conflict handling so doesn't use conflict data */ 279 }, 280 { /* 2 */ 281 .dev = WB_SIO_DEV_GPIO34, 282 .enablereg = WB_SIO_GPIO34_REG_ENABLE, 283 .enablebit = WB_SIO_GPIO34_ENABLE_3, 284 .outputreg = WB_SIO_REG_OVTGPIO3456, 285 .outputppbit = WB_SIO_REG_OG3456_G3PP, 286 .ioreg = WB_SIO_GPIO34_REG_IO3, 287 .invreg = WB_SIO_GPIO34_REG_INV3, 288 .datareg = WB_SIO_GPIO34_REG_DATA3, 289 .conflict = { 290 .name = "UARTC", 291 .dev = WB_SIO_DEV_UARTC, 292 .testreg = WB_SIO_UARTC_REG_ENABLE, 293 .testbit = WB_SIO_UARTC_ENABLE_ON, 294 .warnonly = true 295 } 296 }, 297 { /* 3 */ 298 .dev = WB_SIO_DEV_GPIO34, 299 .enablereg = WB_SIO_GPIO34_REG_ENABLE, 300 .enablebit = WB_SIO_GPIO34_ENABLE_4, 301 .outputreg = WB_SIO_REG_OVTGPIO3456, 302 .outputppbit = WB_SIO_REG_OG3456_G4PP, 303 .ioreg = WB_SIO_GPIO34_REG_IO4, 304 .invreg = WB_SIO_GPIO34_REG_INV4, 305 .datareg = WB_SIO_GPIO34_REG_DATA4, 306 .conflict = { 307 .name = "UARTD", 308 .dev = WB_SIO_DEV_UARTD, 309 .testreg = WB_SIO_UARTD_REG_ENABLE, 310 .testbit = WB_SIO_UARTD_ENABLE_ON, 311 .warnonly = true 312 } 313 }, 314 { /* 4 */ 315 .dev = WB_SIO_DEV_WDGPIO56, 316 .enablereg = WB_SIO_WDGPIO56_REG_ENABLE, 317 .enablebit = WB_SIO_WDGPIO56_ENABLE_5, 318 .outputreg = WB_SIO_REG_OVTGPIO3456, 319 .outputppbit = WB_SIO_REG_OG3456_G5PP, 320 .ioreg = WB_SIO_WDGPIO56_REG_IO5, 321 .invreg = WB_SIO_WDGPIO56_REG_INV5, 322 .datareg = WB_SIO_WDGPIO56_REG_DATA5, 323 .conflict = { 324 .name = "UARTE", 325 .dev = WB_SIO_DEV_UARTE, 326 .testreg = WB_SIO_UARTE_REG_ENABLE, 327 .testbit = WB_SIO_UARTE_ENABLE_ON, 328 .warnonly = true 329 } 330 }, 331 { /* 5 */ 332 .dev = WB_SIO_DEV_WDGPIO56, 333 .enablereg = WB_SIO_WDGPIO56_REG_ENABLE, 334 .enablebit = WB_SIO_WDGPIO56_ENABLE_6, 335 .outputreg = WB_SIO_REG_OVTGPIO3456, 336 .outputppbit = WB_SIO_REG_OG3456_G6PP, 337 .ioreg = WB_SIO_WDGPIO56_REG_IO6, 338 .invreg = WB_SIO_WDGPIO56_REG_INV6, 339 .datareg = WB_SIO_WDGPIO56_REG_DATA6, 340 .conflict = { 341 .name = "FDC", 342 .dev = WB_SIO_DEV_NONE, 343 .testreg = WB_SIO_REG_GLOBAL_OPT, 344 .testbit = WB_SIO_REG_GO_ENFDC, 345 .warnonly = false 346 } 347 } 348 }; 349 350 /* returns whether changing a pin is allowed */ 351 static bool winbond_gpio_get_info(unsigned int *gpio_num, 352 const struct winbond_gpio_info **info) 353 { 354 bool allow_changing = true; 355 unsigned long i; 356 357 for_each_set_bit(i, ¶ms.gpios, BITS_PER_LONG) { 358 if (*gpio_num < 8) 359 break; 360 361 *gpio_num -= 8; 362 } 363 364 *info = &winbond_gpio_infos[i]; 365 366 /* 367 * GPIO2 (the second port) shares some pins with a basic PC 368 * functionality, which is very likely controlled by the firmware. 369 * Don't allow changing these pins by default. 370 */ 371 if (i == 1) { 372 if (*gpio_num == 0 && !params.pledgpio) 373 allow_changing = false; 374 else if (*gpio_num == 1 && !params.beepgpio) 375 allow_changing = false; 376 else if ((*gpio_num == 5 || *gpio_num == 6) && !params.i2cgpio) 377 allow_changing = false; 378 } 379 380 return allow_changing; 381 } 382 383 static int winbond_gpio_get(struct gpio_chip *gc, unsigned int offset) 384 { 385 unsigned long *base = gpiochip_get_data(gc); 386 const struct winbond_gpio_info *info; 387 bool val; 388 389 winbond_gpio_get_info(&offset, &info); 390 391 val = winbond_sio_enter(*base); 392 if (val) 393 return val; 394 395 winbond_sio_select_logical(*base, info->dev); 396 397 val = winbond_sio_reg_btest(*base, info->datareg, offset); 398 if (winbond_sio_reg_btest(*base, info->invreg, offset)) 399 val = !val; 400 401 winbond_sio_leave(*base); 402 403 return val; 404 } 405 406 static int winbond_gpio_direction_in(struct gpio_chip *gc, unsigned int offset) 407 { 408 unsigned long *base = gpiochip_get_data(gc); 409 const struct winbond_gpio_info *info; 410 int ret; 411 412 if (!winbond_gpio_get_info(&offset, &info)) 413 return -EACCES; 414 415 ret = winbond_sio_enter(*base); 416 if (ret) 417 return ret; 418 419 winbond_sio_select_logical(*base, info->dev); 420 421 winbond_sio_reg_bset(*base, info->ioreg, offset); 422 423 winbond_sio_leave(*base); 424 425 return 0; 426 } 427 428 static int winbond_gpio_direction_out(struct gpio_chip *gc, 429 unsigned int offset, 430 int val) 431 { 432 unsigned long *base = gpiochip_get_data(gc); 433 const struct winbond_gpio_info *info; 434 int ret; 435 436 if (!winbond_gpio_get_info(&offset, &info)) 437 return -EACCES; 438 439 ret = winbond_sio_enter(*base); 440 if (ret) 441 return ret; 442 443 winbond_sio_select_logical(*base, info->dev); 444 445 winbond_sio_reg_bclear(*base, info->ioreg, offset); 446 447 if (winbond_sio_reg_btest(*base, info->invreg, offset)) 448 val = !val; 449 450 if (val) 451 winbond_sio_reg_bset(*base, info->datareg, offset); 452 else 453 winbond_sio_reg_bclear(*base, info->datareg, offset); 454 455 winbond_sio_leave(*base); 456 457 return 0; 458 } 459 460 static void winbond_gpio_set(struct gpio_chip *gc, unsigned int offset, 461 int val) 462 { 463 unsigned long *base = gpiochip_get_data(gc); 464 const struct winbond_gpio_info *info; 465 466 if (!winbond_gpio_get_info(&offset, &info)) 467 return; 468 469 if (winbond_sio_enter(*base) != 0) 470 return; 471 472 winbond_sio_select_logical(*base, info->dev); 473 474 if (winbond_sio_reg_btest(*base, info->invreg, offset)) 475 val = !val; 476 477 if (val) 478 winbond_sio_reg_bset(*base, info->datareg, offset); 479 else 480 winbond_sio_reg_bclear(*base, info->datareg, offset); 481 482 winbond_sio_leave(*base); 483 } 484 485 static struct gpio_chip winbond_gpio_chip = { 486 .base = -1, 487 .label = WB_GPIO_DRIVER_NAME, 488 .owner = THIS_MODULE, 489 .can_sleep = true, 490 .get = winbond_gpio_get, 491 .direction_input = winbond_gpio_direction_in, 492 .set = winbond_gpio_set, 493 .direction_output = winbond_gpio_direction_out, 494 }; 495 496 static void winbond_gpio_configure_port0_pins(unsigned long base) 497 { 498 unsigned int val; 499 500 val = winbond_sio_reg_read(base, WB_SIO_REG_GPIO1_MF); 501 if ((val & WB_SIO_REG_G1MF_FS_MASK) == WB_SIO_REG_G1MF_FS_GPIO1) 502 return; 503 504 pr_warn("GPIO1 pins were connected to something else (%.2x), fixing\n", 505 val); 506 507 val &= ~WB_SIO_REG_G1MF_FS_MASK; 508 val |= WB_SIO_REG_G1MF_FS_GPIO1; 509 510 winbond_sio_reg_write(base, WB_SIO_REG_GPIO1_MF, val); 511 } 512 513 static void winbond_gpio_configure_port1_check_i2c(unsigned long base) 514 { 515 params.i2cgpio = !winbond_sio_reg_btest(base, WB_SIO_REG_I2C_PS, 516 WB_SIO_REG_I2CPS_I2CFS); 517 if (!params.i2cgpio) 518 pr_warn("disabling GPIO2.5 and GPIO2.6 as I2C is enabled\n"); 519 } 520 521 static bool winbond_gpio_configure_port(unsigned long base, unsigned int idx) 522 { 523 const struct winbond_gpio_info *info = &winbond_gpio_infos[idx]; 524 const struct winbond_gpio_port_conflict *conflict = &info->conflict; 525 526 /* is there a possible conflicting device defined? */ 527 if (conflict->name != NULL) { 528 if (conflict->dev != WB_SIO_DEV_NONE) 529 winbond_sio_select_logical(base, conflict->dev); 530 531 if (winbond_sio_reg_btest(base, conflict->testreg, 532 conflict->testbit)) { 533 if (conflict->warnonly) 534 pr_warn("enabled GPIO%u share pins with active %s\n", 535 idx + 1, conflict->name); 536 else { 537 pr_warn("disabling GPIO%u as %s is enabled\n", 538 idx + 1, conflict->name); 539 return false; 540 } 541 } 542 } 543 544 /* GPIO1 and GPIO2 need some (additional) special handling */ 545 if (idx == 0) 546 winbond_gpio_configure_port0_pins(base); 547 else if (idx == 1) 548 winbond_gpio_configure_port1_check_i2c(base); 549 550 winbond_sio_select_logical(base, info->dev); 551 552 winbond_sio_reg_bset(base, info->enablereg, info->enablebit); 553 554 if (params.ppgpios & BIT(idx)) 555 winbond_sio_reg_bset(base, info->outputreg, 556 info->outputppbit); 557 else if (params.odgpios & BIT(idx)) 558 winbond_sio_reg_bclear(base, info->outputreg, 559 info->outputppbit); 560 else 561 pr_notice("GPIO%u pins are %s\n", idx + 1, 562 winbond_sio_reg_btest(base, info->outputreg, 563 info->outputppbit) ? 564 "push-pull" : 565 "open drain"); 566 567 return true; 568 } 569 570 static int winbond_gpio_configure(unsigned long base) 571 { 572 unsigned long i; 573 574 for_each_set_bit(i, ¶ms.gpios, BITS_PER_LONG) 575 if (!winbond_gpio_configure_port(base, i)) 576 __clear_bit(i, ¶ms.gpios); 577 578 if (!params.gpios) { 579 pr_err("please use 'gpios' module parameter to select some active GPIO ports to enable\n"); 580 return -EINVAL; 581 } 582 583 return 0; 584 } 585 586 static int winbond_gpio_check_chip(unsigned long base) 587 { 588 int ret; 589 unsigned int chip; 590 591 ret = winbond_sio_enter(base); 592 if (ret) 593 return ret; 594 595 chip = winbond_sio_reg_read(base, WB_SIO_REG_CHIP_MSB) << 8; 596 chip |= winbond_sio_reg_read(base, WB_SIO_REG_CHIP_LSB); 597 598 pr_notice("chip ID at %lx is %.4x\n", base, chip); 599 600 if ((chip & WB_SIO_CHIP_ID_W83627UHG_MASK) != 601 WB_SIO_CHIP_ID_W83627UHG) { 602 pr_err("not an our chip\n"); 603 ret = -ENODEV; 604 } 605 606 winbond_sio_leave(base); 607 608 return ret; 609 } 610 611 static int winbond_gpio_imatch(struct device *dev, unsigned int id) 612 { 613 unsigned long gpios_rem; 614 int ret; 615 616 gpios_rem = params.gpios & ~GENMASK(ARRAY_SIZE(winbond_gpio_infos) - 1, 617 0); 618 if (gpios_rem) { 619 pr_warn("unknown ports (%lx) enabled in GPIO ports bitmask\n", 620 gpios_rem); 621 params.gpios &= ~gpios_rem; 622 } 623 624 if (params.ppgpios & params.odgpios) { 625 pr_err("some GPIO ports are set both to push-pull and open drain mode at the same time\n"); 626 return 0; 627 } 628 629 if (params.base != 0) 630 return winbond_gpio_check_chip(params.base) == 0; 631 632 /* 633 * if the 'base' module parameter is unset probe two chip default 634 * I/O port bases 635 */ 636 params.base = WB_SIO_BASE; 637 ret = winbond_gpio_check_chip(params.base); 638 if (ret == 0) 639 return 1; 640 if (ret != -ENODEV && ret != -EBUSY) 641 return 0; 642 643 params.base = WB_SIO_BASE_HIGH; 644 return winbond_gpio_check_chip(params.base) == 0; 645 } 646 647 static int winbond_gpio_iprobe(struct device *dev, unsigned int id) 648 { 649 int ret; 650 651 if (params.base == 0) 652 return -EINVAL; 653 654 ret = winbond_sio_enter(params.base); 655 if (ret) 656 return ret; 657 658 ret = winbond_gpio_configure(params.base); 659 660 winbond_sio_leave(params.base); 661 662 if (ret) 663 return ret; 664 665 /* 666 * Add 8 gpios for every GPIO port that was enabled in gpios 667 * module parameter (that wasn't disabled earlier in 668 * winbond_gpio_configure() & co. due to, for example, a pin conflict). 669 */ 670 winbond_gpio_chip.ngpio = hweight_long(params.gpios) * 8; 671 672 /* 673 * GPIO6 port has only 5 pins, so if it is enabled we have to adjust 674 * the total count appropriately 675 */ 676 if (params.gpios & BIT(5)) 677 winbond_gpio_chip.ngpio -= (8 - 5); 678 679 winbond_gpio_chip.parent = dev; 680 681 return devm_gpiochip_add_data(dev, &winbond_gpio_chip, ¶ms.base); 682 } 683 684 static struct isa_driver winbond_gpio_idriver = { 685 .driver = { 686 .name = WB_GPIO_DRIVER_NAME, 687 }, 688 .match = winbond_gpio_imatch, 689 .probe = winbond_gpio_iprobe, 690 }; 691 692 module_isa_driver(winbond_gpio_idriver, 1); 693 694 module_param_named(base, params.base, ulong, 0444); 695 MODULE_PARM_DESC(base, 696 "I/O port base (when unset - probe chip default ones)"); 697 698 /* This parameter sets which GPIO devices (ports) we enable */ 699 module_param_named(gpios, params.gpios, ulong, 0444); 700 MODULE_PARM_DESC(gpios, 701 "bitmask of GPIO ports to enable (bit 0 - GPIO1, bit 1 - GPIO2, etc."); 702 703 /* 704 * These two parameters below set how we configure GPIO ports output drivers. 705 * It can't be a one bitmask since we need three values per port: push-pull, 706 * open-drain and keep as-is (this is the default). 707 */ 708 module_param_named(ppgpios, params.ppgpios, ulong, 0444); 709 MODULE_PARM_DESC(ppgpios, 710 "bitmask of GPIO ports to set to push-pull mode (bit 0 - GPIO1, bit 1 - GPIO2, etc."); 711 712 module_param_named(odgpios, params.odgpios, ulong, 0444); 713 MODULE_PARM_DESC(odgpios, 714 "bitmask of GPIO ports to set to open drain mode (bit 0 - GPIO1, bit 1 - GPIO2, etc."); 715 716 /* 717 * GPIO2.0 and GPIO2.1 control a basic PC functionality that we 718 * don't allow tinkering with by default (it is very likely that the 719 * firmware owns these pins). 720 * These two parameters below allow overriding these prohibitions. 721 */ 722 module_param_named(pledgpio, params.pledgpio, bool, 0644); 723 MODULE_PARM_DESC(pledgpio, 724 "enable changing value of GPIO2.0 bit (Power LED), default no."); 725 726 module_param_named(beepgpio, params.beepgpio, bool, 0644); 727 MODULE_PARM_DESC(beepgpio, 728 "enable changing value of GPIO2.1 bit (BEEP), default no."); 729 730 MODULE_AUTHOR("Maciej S. Szmigiero <mail@maciej.szmigiero.name>"); 731 MODULE_DESCRIPTION("GPIO interface for Winbond Super I/O chips"); 732 MODULE_LICENSE("GPL"); 733