1 /* 2 * Intel Whiskey Cove PMIC GPIO Driver 3 * 4 * This driver is written based on gpio-crystalcove.c 5 * 6 * Copyright (C) 2016 Intel Corporation. All rights reserved. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License version 10 * 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/bitops.h> 19 #include <linux/gpio/driver.h> 20 #include <linux/interrupt.h> 21 #include <linux/mfd/intel_soc_pmic.h> 22 #include <linux/module.h> 23 #include <linux/platform_device.h> 24 #include <linux/regmap.h> 25 #include <linux/seq_file.h> 26 27 /* 28 * Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks: 29 * Bank 0: Pin 0 - 6 30 * Bank 1: Pin 7 - 10 31 * Bank 2: Pin 11 - 12 32 * Each pin has one output control register and one input control register. 33 */ 34 #define BANK0_NR_PINS 7 35 #define BANK1_NR_PINS 4 36 #define BANK2_NR_PINS 2 37 #define WCOVE_GPIO_NUM (BANK0_NR_PINS + BANK1_NR_PINS + BANK2_NR_PINS) 38 #define WCOVE_VGPIO_NUM 94 39 /* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */ 40 #define GPIO_OUT_CTRL_BASE 0x4e44 41 /* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */ 42 #define GPIO_IN_CTRL_BASE 0x4e51 43 44 /* 45 * GPIO interrupts are organized in two groups: 46 * Group 0: Bank 0 pins (Pin 0 - 6) 47 * Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12) 48 * Each group has two registers (one bit per pin): status and mask. 49 */ 50 #define GROUP0_NR_IRQS 7 51 #define GROUP1_NR_IRQS 6 52 #define IRQ_MASK_BASE 0x4e19 53 #define IRQ_STATUS_BASE 0x4e0b 54 #define GPIO_IRQ0_MASK GENMASK(6, 0) 55 #define GPIO_IRQ1_MASK GENMASK(5, 0) 56 #define UPDATE_IRQ_TYPE BIT(0) 57 #define UPDATE_IRQ_MASK BIT(1) 58 59 #define CTLI_INTCNT_DIS (0 << 1) 60 #define CTLI_INTCNT_NE (1 << 1) 61 #define CTLI_INTCNT_PE (2 << 1) 62 #define CTLI_INTCNT_BE (3 << 1) 63 64 #define CTLO_DIR_IN (0 << 5) 65 #define CTLO_DIR_OUT (1 << 5) 66 67 #define CTLO_DRV_MASK (1 << 4) 68 #define CTLO_DRV_OD (0 << 4) 69 #define CTLO_DRV_CMOS (1 << 4) 70 71 #define CTLO_DRV_REN (1 << 3) 72 73 #define CTLO_RVAL_2KDOWN (0 << 1) 74 #define CTLO_RVAL_2KUP (1 << 1) 75 #define CTLO_RVAL_50KDOWN (2 << 1) 76 #define CTLO_RVAL_50KUP (3 << 1) 77 78 #define CTLO_INPUT_SET (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP) 79 #define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET) 80 81 enum ctrl_register { 82 CTRL_IN, 83 CTRL_OUT, 84 }; 85 86 /* 87 * struct wcove_gpio - Whiskey Cove GPIO controller 88 * @buslock: for bus lock/sync and unlock. 89 * @chip: the abstract gpio_chip structure. 90 * @dev: the gpio device 91 * @regmap: the regmap from the parent device. 92 * @regmap_irq_chip: the regmap of the gpio irq chip. 93 * @update: pending IRQ setting update, to be written to the chip upon unlock. 94 * @intcnt: the Interrupt Detect value to be written. 95 * @set_irq_mask: true if the IRQ mask needs to be set, false to clear. 96 */ 97 struct wcove_gpio { 98 struct mutex buslock; 99 struct gpio_chip chip; 100 struct device *dev; 101 struct regmap *regmap; 102 struct regmap_irq_chip_data *regmap_irq_chip; 103 int update; 104 int intcnt; 105 bool set_irq_mask; 106 }; 107 108 static inline int to_reg(int gpio, enum ctrl_register reg_type) 109 { 110 unsigned int reg; 111 112 if (gpio >= WCOVE_GPIO_NUM) 113 return -EOPNOTSUPP; 114 115 if (reg_type == CTRL_IN) 116 reg = GPIO_IN_CTRL_BASE + gpio; 117 else 118 reg = GPIO_OUT_CTRL_BASE + gpio; 119 120 return reg; 121 } 122 123 static void wcove_update_irq_mask(struct wcove_gpio *wg, int gpio) 124 { 125 unsigned int reg, mask; 126 127 if (gpio < GROUP0_NR_IRQS) { 128 reg = IRQ_MASK_BASE; 129 mask = BIT(gpio % GROUP0_NR_IRQS); 130 } else { 131 reg = IRQ_MASK_BASE + 1; 132 mask = BIT((gpio - GROUP0_NR_IRQS) % GROUP1_NR_IRQS); 133 } 134 135 if (wg->set_irq_mask) 136 regmap_update_bits(wg->regmap, reg, mask, mask); 137 else 138 regmap_update_bits(wg->regmap, reg, mask, 0); 139 } 140 141 static void wcove_update_irq_ctrl(struct wcove_gpio *wg, int gpio) 142 { 143 int reg = to_reg(gpio, CTRL_IN); 144 145 if (reg < 0) 146 return; 147 148 regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt); 149 } 150 151 static int wcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio) 152 { 153 struct wcove_gpio *wg = gpiochip_get_data(chip); 154 int reg = to_reg(gpio, CTRL_OUT); 155 156 if (reg < 0) 157 return 0; 158 159 return regmap_write(wg->regmap, reg, CTLO_INPUT_SET); 160 } 161 162 static int wcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio, 163 int value) 164 { 165 struct wcove_gpio *wg = gpiochip_get_data(chip); 166 int reg = to_reg(gpio, CTRL_OUT); 167 168 if (reg < 0) 169 return 0; 170 171 return regmap_write(wg->regmap, reg, CTLO_OUTPUT_SET | value); 172 } 173 174 static int wcove_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) 175 { 176 struct wcove_gpio *wg = gpiochip_get_data(chip); 177 unsigned int val; 178 int ret, reg = to_reg(gpio, CTRL_OUT); 179 180 if (reg < 0) 181 return 0; 182 183 ret = regmap_read(wg->regmap, reg, &val); 184 if (ret) 185 return ret; 186 187 return !(val & CTLO_DIR_OUT); 188 } 189 190 static int wcove_gpio_get(struct gpio_chip *chip, unsigned int gpio) 191 { 192 struct wcove_gpio *wg = gpiochip_get_data(chip); 193 unsigned int val; 194 int ret, reg = to_reg(gpio, CTRL_IN); 195 196 if (reg < 0) 197 return 0; 198 199 ret = regmap_read(wg->regmap, reg, &val); 200 if (ret) 201 return ret; 202 203 return val & 0x1; 204 } 205 206 static void wcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) 207 { 208 struct wcove_gpio *wg = gpiochip_get_data(chip); 209 int reg = to_reg(gpio, CTRL_OUT); 210 211 if (reg < 0) 212 return; 213 214 if (value) 215 regmap_update_bits(wg->regmap, reg, 1, 1); 216 else 217 regmap_update_bits(wg->regmap, reg, 1, 0); 218 } 219 220 static int wcove_gpio_set_config(struct gpio_chip *chip, unsigned int gpio, 221 unsigned long config) 222 { 223 struct wcove_gpio *wg = gpiochip_get_data(chip); 224 int reg = to_reg(gpio, CTRL_OUT); 225 226 if (reg < 0) 227 return 0; 228 229 switch (pinconf_to_config_param(config)) { 230 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 231 return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK, 232 CTLO_DRV_OD); 233 case PIN_CONFIG_DRIVE_PUSH_PULL: 234 return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK, 235 CTLO_DRV_CMOS); 236 default: 237 break; 238 } 239 240 return -ENOTSUPP; 241 } 242 243 static int wcove_irq_type(struct irq_data *data, unsigned int type) 244 { 245 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 246 struct wcove_gpio *wg = gpiochip_get_data(chip); 247 248 if (data->hwirq >= WCOVE_GPIO_NUM) 249 return 0; 250 251 switch (type) { 252 case IRQ_TYPE_NONE: 253 wg->intcnt = CTLI_INTCNT_DIS; 254 break; 255 case IRQ_TYPE_EDGE_BOTH: 256 wg->intcnt = CTLI_INTCNT_BE; 257 break; 258 case IRQ_TYPE_EDGE_RISING: 259 wg->intcnt = CTLI_INTCNT_PE; 260 break; 261 case IRQ_TYPE_EDGE_FALLING: 262 wg->intcnt = CTLI_INTCNT_NE; 263 break; 264 default: 265 return -EINVAL; 266 } 267 268 wg->update |= UPDATE_IRQ_TYPE; 269 270 return 0; 271 } 272 273 static void wcove_bus_lock(struct irq_data *data) 274 { 275 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 276 struct wcove_gpio *wg = gpiochip_get_data(chip); 277 278 mutex_lock(&wg->buslock); 279 } 280 281 static void wcove_bus_sync_unlock(struct irq_data *data) 282 { 283 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 284 struct wcove_gpio *wg = gpiochip_get_data(chip); 285 int gpio = data->hwirq; 286 287 if (wg->update & UPDATE_IRQ_TYPE) 288 wcove_update_irq_ctrl(wg, gpio); 289 if (wg->update & UPDATE_IRQ_MASK) 290 wcove_update_irq_mask(wg, gpio); 291 wg->update = 0; 292 293 mutex_unlock(&wg->buslock); 294 } 295 296 static void wcove_irq_unmask(struct irq_data *data) 297 { 298 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 299 struct wcove_gpio *wg = gpiochip_get_data(chip); 300 301 if (data->hwirq >= WCOVE_GPIO_NUM) 302 return; 303 304 wg->set_irq_mask = false; 305 wg->update |= UPDATE_IRQ_MASK; 306 } 307 308 static void wcove_irq_mask(struct irq_data *data) 309 { 310 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 311 struct wcove_gpio *wg = gpiochip_get_data(chip); 312 313 if (data->hwirq >= WCOVE_GPIO_NUM) 314 return; 315 316 wg->set_irq_mask = true; 317 wg->update |= UPDATE_IRQ_MASK; 318 } 319 320 static struct irq_chip wcove_irqchip = { 321 .name = "Whiskey Cove", 322 .irq_mask = wcove_irq_mask, 323 .irq_unmask = wcove_irq_unmask, 324 .irq_set_type = wcove_irq_type, 325 .irq_bus_lock = wcove_bus_lock, 326 .irq_bus_sync_unlock = wcove_bus_sync_unlock, 327 }; 328 329 static irqreturn_t wcove_gpio_irq_handler(int irq, void *data) 330 { 331 struct wcove_gpio *wg = (struct wcove_gpio *)data; 332 unsigned int pending, virq, gpio, mask, offset; 333 u8 p[2]; 334 335 if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) { 336 dev_err(wg->dev, "Failed to read irq status register\n"); 337 return IRQ_NONE; 338 } 339 340 pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7); 341 if (!pending) 342 return IRQ_NONE; 343 344 /* Iterate until no interrupt is pending */ 345 while (pending) { 346 /* One iteration is for all pending bits */ 347 for_each_set_bit(gpio, (const unsigned long *)&pending, 348 WCOVE_GPIO_NUM) { 349 offset = (gpio > GROUP0_NR_IRQS) ? 1 : 0; 350 mask = (offset == 1) ? BIT(gpio - GROUP0_NR_IRQS) : 351 BIT(gpio); 352 virq = irq_find_mapping(wg->chip.irq.domain, gpio); 353 handle_nested_irq(virq); 354 regmap_update_bits(wg->regmap, IRQ_STATUS_BASE + offset, 355 mask, mask); 356 } 357 358 /* Next iteration */ 359 if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) { 360 dev_err(wg->dev, "Failed to read irq status\n"); 361 break; 362 } 363 364 pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7); 365 } 366 367 return IRQ_HANDLED; 368 } 369 370 static void wcove_gpio_dbg_show(struct seq_file *s, 371 struct gpio_chip *chip) 372 { 373 unsigned int ctlo, ctli, irq_mask, irq_status; 374 struct wcove_gpio *wg = gpiochip_get_data(chip); 375 int gpio, offset, group, ret = 0; 376 377 for (gpio = 0; gpio < WCOVE_GPIO_NUM; gpio++) { 378 group = gpio < GROUP0_NR_IRQS ? 0 : 1; 379 ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo); 380 ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli); 381 ret += regmap_read(wg->regmap, IRQ_MASK_BASE + group, 382 &irq_mask); 383 ret += regmap_read(wg->regmap, IRQ_STATUS_BASE + group, 384 &irq_status); 385 if (ret) { 386 pr_err("Failed to read registers: ctrl out/in or irq status/mask\n"); 387 break; 388 } 389 390 offset = gpio % 8; 391 seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s\n", 392 gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ", 393 ctli & 0x1 ? "hi" : "lo", 394 ctli & CTLI_INTCNT_NE ? "fall" : " ", 395 ctli & CTLI_INTCNT_PE ? "rise" : " ", 396 ctlo, 397 irq_mask & BIT(offset) ? "mask " : "unmask", 398 irq_status & BIT(offset) ? "pending" : " "); 399 } 400 } 401 402 static int wcove_gpio_probe(struct platform_device *pdev) 403 { 404 struct intel_soc_pmic *pmic; 405 struct wcove_gpio *wg; 406 int virq, ret, irq; 407 struct device *dev; 408 409 /* 410 * This gpio platform device is created by a mfd device (see 411 * drivers/mfd/intel_soc_pmic_bxtwc.c for details). Information 412 * shared by all sub-devices created by the mfd device, the regmap 413 * pointer for instance, is stored as driver data of the mfd device 414 * driver. 415 */ 416 pmic = dev_get_drvdata(pdev->dev.parent); 417 if (!pmic) 418 return -ENODEV; 419 420 irq = platform_get_irq(pdev, 0); 421 if (irq < 0) 422 return irq; 423 424 dev = &pdev->dev; 425 426 wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL); 427 if (!wg) 428 return -ENOMEM; 429 430 wg->regmap_irq_chip = pmic->irq_chip_data; 431 432 platform_set_drvdata(pdev, wg); 433 434 mutex_init(&wg->buslock); 435 wg->chip.label = KBUILD_MODNAME; 436 wg->chip.direction_input = wcove_gpio_dir_in; 437 wg->chip.direction_output = wcove_gpio_dir_out; 438 wg->chip.get_direction = wcove_gpio_get_direction; 439 wg->chip.get = wcove_gpio_get; 440 wg->chip.set = wcove_gpio_set; 441 wg->chip.set_config = wcove_gpio_set_config, 442 wg->chip.base = -1; 443 wg->chip.ngpio = WCOVE_VGPIO_NUM; 444 wg->chip.can_sleep = true; 445 wg->chip.parent = pdev->dev.parent; 446 wg->chip.dbg_show = wcove_gpio_dbg_show; 447 wg->dev = dev; 448 wg->regmap = pmic->regmap; 449 450 ret = devm_gpiochip_add_data(dev, &wg->chip, wg); 451 if (ret) { 452 dev_err(dev, "Failed to add gpiochip: %d\n", ret); 453 return ret; 454 } 455 456 ret = gpiochip_irqchip_add_nested(&wg->chip, &wcove_irqchip, 0, 457 handle_simple_irq, IRQ_TYPE_NONE); 458 if (ret) { 459 dev_err(dev, "Failed to add irqchip: %d\n", ret); 460 return ret; 461 } 462 463 virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq); 464 if (virq < 0) { 465 dev_err(dev, "Failed to get virq by irq %d\n", irq); 466 return virq; 467 } 468 469 ret = devm_request_threaded_irq(dev, virq, NULL, 470 wcove_gpio_irq_handler, IRQF_ONESHOT, pdev->name, wg); 471 if (ret) { 472 dev_err(dev, "Failed to request irq %d\n", virq); 473 return ret; 474 } 475 476 gpiochip_set_nested_irqchip(&wg->chip, &wcove_irqchip, virq); 477 478 /* Enable GPIO0 interrupts */ 479 ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE, GPIO_IRQ0_MASK, 480 0x00); 481 if (ret) 482 return ret; 483 484 /* Enable GPIO1 interrupts */ 485 ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK, 486 0x00); 487 if (ret) 488 return ret; 489 490 return 0; 491 } 492 493 /* 494 * Whiskey Cove PMIC itself is a analog device(but with digital control 495 * interface) providing power management support for other devices in 496 * the accompanied SoC, so we have no .pm for Whiskey Cove GPIO driver. 497 */ 498 static struct platform_driver wcove_gpio_driver = { 499 .driver = { 500 .name = "bxt_wcove_gpio", 501 }, 502 .probe = wcove_gpio_probe, 503 }; 504 505 module_platform_driver(wcove_gpio_driver); 506 507 MODULE_AUTHOR("Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>"); 508 MODULE_AUTHOR("Bin Gao <bin.gao@intel.com>"); 509 MODULE_DESCRIPTION("Intel Whiskey Cove GPIO Driver"); 510 MODULE_LICENSE("GPL v2"); 511 MODULE_ALIAS("platform:bxt_wcove_gpio"); 512