1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel Whiskey Cove PMIC GPIO Driver 4 * 5 * This driver is written based on gpio-crystalcove.c 6 * 7 * Copyright (C) 2016 Intel Corporation. All rights reserved. 8 */ 9 10 #include <linux/bitops.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/mfd/intel_soc_pmic.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/regmap.h> 17 #include <linux/seq_file.h> 18 19 /* 20 * Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks: 21 * Bank 0: Pin 0 - 6 22 * Bank 1: Pin 7 - 10 23 * Bank 2: Pin 11 - 12 24 * Each pin has one output control register and one input control register. 25 */ 26 #define BANK0_NR_PINS 7 27 #define BANK1_NR_PINS 4 28 #define BANK2_NR_PINS 2 29 #define WCOVE_GPIO_NUM (BANK0_NR_PINS + BANK1_NR_PINS + BANK2_NR_PINS) 30 #define WCOVE_VGPIO_NUM 94 31 /* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */ 32 #define GPIO_OUT_CTRL_BASE 0x4e44 33 /* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */ 34 #define GPIO_IN_CTRL_BASE 0x4e51 35 36 /* 37 * GPIO interrupts are organized in two groups: 38 * Group 0: Bank 0 pins (Pin 0 - 6) 39 * Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12) 40 * Each group has two registers (one bit per pin): status and mask. 41 */ 42 #define GROUP0_NR_IRQS 7 43 #define GROUP1_NR_IRQS 6 44 #define IRQ_MASK_BASE 0x4e19 45 #define IRQ_STATUS_BASE 0x4e0b 46 #define GPIO_IRQ0_MASK GENMASK(6, 0) 47 #define GPIO_IRQ1_MASK GENMASK(5, 0) 48 #define UPDATE_IRQ_TYPE BIT(0) 49 #define UPDATE_IRQ_MASK BIT(1) 50 51 #define CTLI_INTCNT_DIS (0 << 1) 52 #define CTLI_INTCNT_NE (1 << 1) 53 #define CTLI_INTCNT_PE (2 << 1) 54 #define CTLI_INTCNT_BE (3 << 1) 55 56 #define CTLO_DIR_IN (0 << 5) 57 #define CTLO_DIR_OUT (1 << 5) 58 59 #define CTLO_DRV_MASK (1 << 4) 60 #define CTLO_DRV_OD (0 << 4) 61 #define CTLO_DRV_CMOS (1 << 4) 62 63 #define CTLO_DRV_REN (1 << 3) 64 65 #define CTLO_RVAL_2KDOWN (0 << 1) 66 #define CTLO_RVAL_2KUP (1 << 1) 67 #define CTLO_RVAL_50KDOWN (2 << 1) 68 #define CTLO_RVAL_50KUP (3 << 1) 69 70 #define CTLO_INPUT_SET (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP) 71 #define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET) 72 73 enum ctrl_register { 74 CTRL_IN, 75 CTRL_OUT, 76 }; 77 78 /* 79 * struct wcove_gpio - Whiskey Cove GPIO controller 80 * @buslock: for bus lock/sync and unlock. 81 * @chip: the abstract gpio_chip structure. 82 * @dev: the gpio device 83 * @regmap: the regmap from the parent device. 84 * @regmap_irq_chip: the regmap of the gpio irq chip. 85 * @update: pending IRQ setting update, to be written to the chip upon unlock. 86 * @intcnt: the Interrupt Detect value to be written. 87 * @set_irq_mask: true if the IRQ mask needs to be set, false to clear. 88 */ 89 struct wcove_gpio { 90 struct mutex buslock; 91 struct gpio_chip chip; 92 struct device *dev; 93 struct regmap *regmap; 94 struct regmap_irq_chip_data *regmap_irq_chip; 95 int update; 96 int intcnt; 97 bool set_irq_mask; 98 }; 99 100 static inline int to_reg(int gpio, enum ctrl_register reg_type) 101 { 102 unsigned int reg; 103 104 if (gpio >= WCOVE_GPIO_NUM) 105 return -EOPNOTSUPP; 106 107 if (reg_type == CTRL_IN) 108 reg = GPIO_IN_CTRL_BASE + gpio; 109 else 110 reg = GPIO_OUT_CTRL_BASE + gpio; 111 112 return reg; 113 } 114 115 static void wcove_update_irq_mask(struct wcove_gpio *wg, int gpio) 116 { 117 unsigned int reg, mask; 118 119 if (gpio < GROUP0_NR_IRQS) { 120 reg = IRQ_MASK_BASE; 121 mask = BIT(gpio % GROUP0_NR_IRQS); 122 } else { 123 reg = IRQ_MASK_BASE + 1; 124 mask = BIT((gpio - GROUP0_NR_IRQS) % GROUP1_NR_IRQS); 125 } 126 127 if (wg->set_irq_mask) 128 regmap_update_bits(wg->regmap, reg, mask, mask); 129 else 130 regmap_update_bits(wg->regmap, reg, mask, 0); 131 } 132 133 static void wcove_update_irq_ctrl(struct wcove_gpio *wg, int gpio) 134 { 135 int reg = to_reg(gpio, CTRL_IN); 136 137 if (reg < 0) 138 return; 139 140 regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt); 141 } 142 143 static int wcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio) 144 { 145 struct wcove_gpio *wg = gpiochip_get_data(chip); 146 int reg = to_reg(gpio, CTRL_OUT); 147 148 if (reg < 0) 149 return 0; 150 151 return regmap_write(wg->regmap, reg, CTLO_INPUT_SET); 152 } 153 154 static int wcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio, 155 int value) 156 { 157 struct wcove_gpio *wg = gpiochip_get_data(chip); 158 int reg = to_reg(gpio, CTRL_OUT); 159 160 if (reg < 0) 161 return 0; 162 163 return regmap_write(wg->regmap, reg, CTLO_OUTPUT_SET | value); 164 } 165 166 static int wcove_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) 167 { 168 struct wcove_gpio *wg = gpiochip_get_data(chip); 169 unsigned int val; 170 int ret, reg = to_reg(gpio, CTRL_OUT); 171 172 if (reg < 0) 173 return 0; 174 175 ret = regmap_read(wg->regmap, reg, &val); 176 if (ret) 177 return ret; 178 179 return !(val & CTLO_DIR_OUT); 180 } 181 182 static int wcove_gpio_get(struct gpio_chip *chip, unsigned int gpio) 183 { 184 struct wcove_gpio *wg = gpiochip_get_data(chip); 185 unsigned int val; 186 int ret, reg = to_reg(gpio, CTRL_IN); 187 188 if (reg < 0) 189 return 0; 190 191 ret = regmap_read(wg->regmap, reg, &val); 192 if (ret) 193 return ret; 194 195 return val & 0x1; 196 } 197 198 static void wcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) 199 { 200 struct wcove_gpio *wg = gpiochip_get_data(chip); 201 int reg = to_reg(gpio, CTRL_OUT); 202 203 if (reg < 0) 204 return; 205 206 if (value) 207 regmap_update_bits(wg->regmap, reg, 1, 1); 208 else 209 regmap_update_bits(wg->regmap, reg, 1, 0); 210 } 211 212 static int wcove_gpio_set_config(struct gpio_chip *chip, unsigned int gpio, 213 unsigned long config) 214 { 215 struct wcove_gpio *wg = gpiochip_get_data(chip); 216 int reg = to_reg(gpio, CTRL_OUT); 217 218 if (reg < 0) 219 return 0; 220 221 switch (pinconf_to_config_param(config)) { 222 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 223 return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK, 224 CTLO_DRV_OD); 225 case PIN_CONFIG_DRIVE_PUSH_PULL: 226 return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK, 227 CTLO_DRV_CMOS); 228 default: 229 break; 230 } 231 232 return -ENOTSUPP; 233 } 234 235 static int wcove_irq_type(struct irq_data *data, unsigned int type) 236 { 237 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 238 struct wcove_gpio *wg = gpiochip_get_data(chip); 239 240 if (data->hwirq >= WCOVE_GPIO_NUM) 241 return 0; 242 243 switch (type) { 244 case IRQ_TYPE_NONE: 245 wg->intcnt = CTLI_INTCNT_DIS; 246 break; 247 case IRQ_TYPE_EDGE_BOTH: 248 wg->intcnt = CTLI_INTCNT_BE; 249 break; 250 case IRQ_TYPE_EDGE_RISING: 251 wg->intcnt = CTLI_INTCNT_PE; 252 break; 253 case IRQ_TYPE_EDGE_FALLING: 254 wg->intcnt = CTLI_INTCNT_NE; 255 break; 256 default: 257 return -EINVAL; 258 } 259 260 wg->update |= UPDATE_IRQ_TYPE; 261 262 return 0; 263 } 264 265 static void wcove_bus_lock(struct irq_data *data) 266 { 267 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 268 struct wcove_gpio *wg = gpiochip_get_data(chip); 269 270 mutex_lock(&wg->buslock); 271 } 272 273 static void wcove_bus_sync_unlock(struct irq_data *data) 274 { 275 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 276 struct wcove_gpio *wg = gpiochip_get_data(chip); 277 int gpio = data->hwirq; 278 279 if (wg->update & UPDATE_IRQ_TYPE) 280 wcove_update_irq_ctrl(wg, gpio); 281 if (wg->update & UPDATE_IRQ_MASK) 282 wcove_update_irq_mask(wg, gpio); 283 wg->update = 0; 284 285 mutex_unlock(&wg->buslock); 286 } 287 288 static void wcove_irq_unmask(struct irq_data *data) 289 { 290 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 291 struct wcove_gpio *wg = gpiochip_get_data(chip); 292 293 if (data->hwirq >= WCOVE_GPIO_NUM) 294 return; 295 296 wg->set_irq_mask = false; 297 wg->update |= UPDATE_IRQ_MASK; 298 } 299 300 static void wcove_irq_mask(struct irq_data *data) 301 { 302 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 303 struct wcove_gpio *wg = gpiochip_get_data(chip); 304 305 if (data->hwirq >= WCOVE_GPIO_NUM) 306 return; 307 308 wg->set_irq_mask = true; 309 wg->update |= UPDATE_IRQ_MASK; 310 } 311 312 static struct irq_chip wcove_irqchip = { 313 .name = "Whiskey Cove", 314 .irq_mask = wcove_irq_mask, 315 .irq_unmask = wcove_irq_unmask, 316 .irq_set_type = wcove_irq_type, 317 .irq_bus_lock = wcove_bus_lock, 318 .irq_bus_sync_unlock = wcove_bus_sync_unlock, 319 }; 320 321 static irqreturn_t wcove_gpio_irq_handler(int irq, void *data) 322 { 323 struct wcove_gpio *wg = (struct wcove_gpio *)data; 324 unsigned int pending, virq, gpio, mask, offset; 325 u8 p[2]; 326 327 if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) { 328 dev_err(wg->dev, "Failed to read irq status register\n"); 329 return IRQ_NONE; 330 } 331 332 pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7); 333 if (!pending) 334 return IRQ_NONE; 335 336 /* Iterate until no interrupt is pending */ 337 while (pending) { 338 /* One iteration is for all pending bits */ 339 for_each_set_bit(gpio, (const unsigned long *)&pending, 340 WCOVE_GPIO_NUM) { 341 offset = (gpio > GROUP0_NR_IRQS) ? 1 : 0; 342 mask = (offset == 1) ? BIT(gpio - GROUP0_NR_IRQS) : 343 BIT(gpio); 344 virq = irq_find_mapping(wg->chip.irq.domain, gpio); 345 handle_nested_irq(virq); 346 regmap_update_bits(wg->regmap, IRQ_STATUS_BASE + offset, 347 mask, mask); 348 } 349 350 /* Next iteration */ 351 if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) { 352 dev_err(wg->dev, "Failed to read irq status\n"); 353 break; 354 } 355 356 pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7); 357 } 358 359 return IRQ_HANDLED; 360 } 361 362 static void wcove_gpio_dbg_show(struct seq_file *s, 363 struct gpio_chip *chip) 364 { 365 unsigned int ctlo, ctli, irq_mask, irq_status; 366 struct wcove_gpio *wg = gpiochip_get_data(chip); 367 int gpio, offset, group, ret = 0; 368 369 for (gpio = 0; gpio < WCOVE_GPIO_NUM; gpio++) { 370 group = gpio < GROUP0_NR_IRQS ? 0 : 1; 371 ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo); 372 ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli); 373 ret += regmap_read(wg->regmap, IRQ_MASK_BASE + group, 374 &irq_mask); 375 ret += regmap_read(wg->regmap, IRQ_STATUS_BASE + group, 376 &irq_status); 377 if (ret) { 378 pr_err("Failed to read registers: ctrl out/in or irq status/mask\n"); 379 break; 380 } 381 382 offset = gpio % 8; 383 seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s\n", 384 gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ", 385 ctli & 0x1 ? "hi" : "lo", 386 ctli & CTLI_INTCNT_NE ? "fall" : " ", 387 ctli & CTLI_INTCNT_PE ? "rise" : " ", 388 ctlo, 389 irq_mask & BIT(offset) ? "mask " : "unmask", 390 irq_status & BIT(offset) ? "pending" : " "); 391 } 392 } 393 394 static int wcove_gpio_probe(struct platform_device *pdev) 395 { 396 struct intel_soc_pmic *pmic; 397 struct wcove_gpio *wg; 398 int virq, ret, irq; 399 struct device *dev; 400 401 /* 402 * This gpio platform device is created by a mfd device (see 403 * drivers/mfd/intel_soc_pmic_bxtwc.c for details). Information 404 * shared by all sub-devices created by the mfd device, the regmap 405 * pointer for instance, is stored as driver data of the mfd device 406 * driver. 407 */ 408 pmic = dev_get_drvdata(pdev->dev.parent); 409 if (!pmic) 410 return -ENODEV; 411 412 irq = platform_get_irq(pdev, 0); 413 if (irq < 0) 414 return irq; 415 416 dev = &pdev->dev; 417 418 wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL); 419 if (!wg) 420 return -ENOMEM; 421 422 wg->regmap_irq_chip = pmic->irq_chip_data; 423 424 platform_set_drvdata(pdev, wg); 425 426 mutex_init(&wg->buslock); 427 wg->chip.label = KBUILD_MODNAME; 428 wg->chip.direction_input = wcove_gpio_dir_in; 429 wg->chip.direction_output = wcove_gpio_dir_out; 430 wg->chip.get_direction = wcove_gpio_get_direction; 431 wg->chip.get = wcove_gpio_get; 432 wg->chip.set = wcove_gpio_set; 433 wg->chip.set_config = wcove_gpio_set_config, 434 wg->chip.base = -1; 435 wg->chip.ngpio = WCOVE_VGPIO_NUM; 436 wg->chip.can_sleep = true; 437 wg->chip.parent = pdev->dev.parent; 438 wg->chip.dbg_show = wcove_gpio_dbg_show; 439 wg->dev = dev; 440 wg->regmap = pmic->regmap; 441 442 ret = devm_gpiochip_add_data(dev, &wg->chip, wg); 443 if (ret) { 444 dev_err(dev, "Failed to add gpiochip: %d\n", ret); 445 return ret; 446 } 447 448 ret = gpiochip_irqchip_add_nested(&wg->chip, &wcove_irqchip, 0, 449 handle_simple_irq, IRQ_TYPE_NONE); 450 if (ret) { 451 dev_err(dev, "Failed to add irqchip: %d\n", ret); 452 return ret; 453 } 454 455 virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq); 456 if (virq < 0) { 457 dev_err(dev, "Failed to get virq by irq %d\n", irq); 458 return virq; 459 } 460 461 ret = devm_request_threaded_irq(dev, virq, NULL, 462 wcove_gpio_irq_handler, IRQF_ONESHOT, pdev->name, wg); 463 if (ret) { 464 dev_err(dev, "Failed to request irq %d\n", virq); 465 return ret; 466 } 467 468 gpiochip_set_nested_irqchip(&wg->chip, &wcove_irqchip, virq); 469 470 /* Enable GPIO0 interrupts */ 471 ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE, GPIO_IRQ0_MASK, 472 0x00); 473 if (ret) 474 return ret; 475 476 /* Enable GPIO1 interrupts */ 477 ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK, 478 0x00); 479 if (ret) 480 return ret; 481 482 return 0; 483 } 484 485 /* 486 * Whiskey Cove PMIC itself is a analog device(but with digital control 487 * interface) providing power management support for other devices in 488 * the accompanied SoC, so we have no .pm for Whiskey Cove GPIO driver. 489 */ 490 static struct platform_driver wcove_gpio_driver = { 491 .driver = { 492 .name = "bxt_wcove_gpio", 493 }, 494 .probe = wcove_gpio_probe, 495 }; 496 497 module_platform_driver(wcove_gpio_driver); 498 499 MODULE_AUTHOR("Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>"); 500 MODULE_AUTHOR("Bin Gao <bin.gao@intel.com>"); 501 MODULE_DESCRIPTION("Intel Whiskey Cove GPIO Driver"); 502 MODULE_LICENSE("GPL v2"); 503 MODULE_ALIAS("platform:bxt_wcove_gpio"); 504