1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel Whiskey Cove PMIC GPIO Driver 4 * 5 * This driver is written based on gpio-crystalcove.c 6 * 7 * Copyright (C) 2016 Intel Corporation. All rights reserved. 8 */ 9 10 #include <linux/bitops.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/mfd/intel_soc_pmic.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/regmap.h> 17 #include <linux/seq_file.h> 18 19 /* 20 * Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks: 21 * Bank 0: Pin 0 - 6 22 * Bank 1: Pin 7 - 10 23 * Bank 2: Pin 11 - 12 24 * Each pin has one output control register and one input control register. 25 */ 26 #define BANK0_NR_PINS 7 27 #define BANK1_NR_PINS 4 28 #define BANK2_NR_PINS 2 29 #define WCOVE_GPIO_NUM (BANK0_NR_PINS + BANK1_NR_PINS + BANK2_NR_PINS) 30 #define WCOVE_VGPIO_NUM 94 31 /* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */ 32 #define GPIO_OUT_CTRL_BASE 0x4e44 33 /* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */ 34 #define GPIO_IN_CTRL_BASE 0x4e51 35 36 /* 37 * GPIO interrupts are organized in two groups: 38 * Group 0: Bank 0 pins (Pin 0 - 6) 39 * Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12) 40 * Each group has two registers (one bit per pin): status and mask. 41 */ 42 #define GROUP0_NR_IRQS 7 43 #define GROUP1_NR_IRQS 6 44 #define IRQ_MASK_BASE 0x4e19 45 #define IRQ_STATUS_BASE 0x4e0b 46 #define GPIO_IRQ0_MASK GENMASK(6, 0) 47 #define GPIO_IRQ1_MASK GENMASK(5, 0) 48 #define UPDATE_IRQ_TYPE BIT(0) 49 #define UPDATE_IRQ_MASK BIT(1) 50 51 #define CTLI_INTCNT_DIS (0 << 1) 52 #define CTLI_INTCNT_NE (1 << 1) 53 #define CTLI_INTCNT_PE (2 << 1) 54 #define CTLI_INTCNT_BE (3 << 1) 55 56 #define CTLO_DIR_IN (0 << 5) 57 #define CTLO_DIR_OUT (1 << 5) 58 59 #define CTLO_DRV_MASK (1 << 4) 60 #define CTLO_DRV_OD (0 << 4) 61 #define CTLO_DRV_CMOS (1 << 4) 62 63 #define CTLO_DRV_REN (1 << 3) 64 65 #define CTLO_RVAL_2KDOWN (0 << 1) 66 #define CTLO_RVAL_2KUP (1 << 1) 67 #define CTLO_RVAL_50KDOWN (2 << 1) 68 #define CTLO_RVAL_50KUP (3 << 1) 69 70 #define CTLO_INPUT_SET (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP) 71 #define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET) 72 73 enum ctrl_register { 74 CTRL_IN, 75 CTRL_OUT, 76 }; 77 78 /* 79 * struct wcove_gpio - Whiskey Cove GPIO controller 80 * @buslock: for bus lock/sync and unlock. 81 * @chip: the abstract gpio_chip structure. 82 * @dev: the gpio device 83 * @regmap: the regmap from the parent device. 84 * @regmap_irq_chip: the regmap of the gpio irq chip. 85 * @update: pending IRQ setting update, to be written to the chip upon unlock. 86 * @intcnt: the Interrupt Detect value to be written. 87 * @set_irq_mask: true if the IRQ mask needs to be set, false to clear. 88 */ 89 struct wcove_gpio { 90 struct mutex buslock; 91 struct gpio_chip chip; 92 struct device *dev; 93 struct regmap *regmap; 94 struct regmap_irq_chip_data *regmap_irq_chip; 95 int update; 96 int intcnt; 97 bool set_irq_mask; 98 }; 99 100 static inline int to_reg(int gpio, enum ctrl_register reg_type) 101 { 102 unsigned int reg; 103 104 if (gpio >= WCOVE_GPIO_NUM) 105 return -EOPNOTSUPP; 106 107 if (reg_type == CTRL_IN) 108 reg = GPIO_IN_CTRL_BASE + gpio; 109 else 110 reg = GPIO_OUT_CTRL_BASE + gpio; 111 112 return reg; 113 } 114 115 static void wcove_update_irq_mask(struct wcove_gpio *wg, int gpio) 116 { 117 unsigned int reg, mask; 118 119 if (gpio < GROUP0_NR_IRQS) { 120 reg = IRQ_MASK_BASE; 121 mask = BIT(gpio % GROUP0_NR_IRQS); 122 } else { 123 reg = IRQ_MASK_BASE + 1; 124 mask = BIT((gpio - GROUP0_NR_IRQS) % GROUP1_NR_IRQS); 125 } 126 127 if (wg->set_irq_mask) 128 regmap_update_bits(wg->regmap, reg, mask, mask); 129 else 130 regmap_update_bits(wg->regmap, reg, mask, 0); 131 } 132 133 static void wcove_update_irq_ctrl(struct wcove_gpio *wg, int gpio) 134 { 135 int reg = to_reg(gpio, CTRL_IN); 136 137 if (reg < 0) 138 return; 139 140 regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt); 141 } 142 143 static int wcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio) 144 { 145 struct wcove_gpio *wg = gpiochip_get_data(chip); 146 int reg = to_reg(gpio, CTRL_OUT); 147 148 if (reg < 0) 149 return 0; 150 151 return regmap_write(wg->regmap, reg, CTLO_INPUT_SET); 152 } 153 154 static int wcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio, 155 int value) 156 { 157 struct wcove_gpio *wg = gpiochip_get_data(chip); 158 int reg = to_reg(gpio, CTRL_OUT); 159 160 if (reg < 0) 161 return 0; 162 163 return regmap_write(wg->regmap, reg, CTLO_OUTPUT_SET | value); 164 } 165 166 static int wcove_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) 167 { 168 struct wcove_gpio *wg = gpiochip_get_data(chip); 169 unsigned int val; 170 int ret, reg = to_reg(gpio, CTRL_OUT); 171 172 if (reg < 0) 173 return GPIO_LINE_DIRECTION_OUT; 174 175 ret = regmap_read(wg->regmap, reg, &val); 176 if (ret) 177 return ret; 178 179 if (val & CTLO_DIR_OUT) 180 return GPIO_LINE_DIRECTION_OUT; 181 182 return GPIO_LINE_DIRECTION_IN; 183 } 184 185 static int wcove_gpio_get(struct gpio_chip *chip, unsigned int gpio) 186 { 187 struct wcove_gpio *wg = gpiochip_get_data(chip); 188 unsigned int val; 189 int ret, reg = to_reg(gpio, CTRL_IN); 190 191 if (reg < 0) 192 return 0; 193 194 ret = regmap_read(wg->regmap, reg, &val); 195 if (ret) 196 return ret; 197 198 return val & 0x1; 199 } 200 201 static void wcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) 202 { 203 struct wcove_gpio *wg = gpiochip_get_data(chip); 204 int reg = to_reg(gpio, CTRL_OUT); 205 206 if (reg < 0) 207 return; 208 209 if (value) 210 regmap_update_bits(wg->regmap, reg, 1, 1); 211 else 212 regmap_update_bits(wg->regmap, reg, 1, 0); 213 } 214 215 static int wcove_gpio_set_config(struct gpio_chip *chip, unsigned int gpio, 216 unsigned long config) 217 { 218 struct wcove_gpio *wg = gpiochip_get_data(chip); 219 int reg = to_reg(gpio, CTRL_OUT); 220 221 if (reg < 0) 222 return 0; 223 224 switch (pinconf_to_config_param(config)) { 225 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 226 return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK, 227 CTLO_DRV_OD); 228 case PIN_CONFIG_DRIVE_PUSH_PULL: 229 return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK, 230 CTLO_DRV_CMOS); 231 default: 232 break; 233 } 234 235 return -ENOTSUPP; 236 } 237 238 static int wcove_irq_type(struct irq_data *data, unsigned int type) 239 { 240 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 241 struct wcove_gpio *wg = gpiochip_get_data(chip); 242 243 if (data->hwirq >= WCOVE_GPIO_NUM) 244 return 0; 245 246 switch (type) { 247 case IRQ_TYPE_NONE: 248 wg->intcnt = CTLI_INTCNT_DIS; 249 break; 250 case IRQ_TYPE_EDGE_BOTH: 251 wg->intcnt = CTLI_INTCNT_BE; 252 break; 253 case IRQ_TYPE_EDGE_RISING: 254 wg->intcnt = CTLI_INTCNT_PE; 255 break; 256 case IRQ_TYPE_EDGE_FALLING: 257 wg->intcnt = CTLI_INTCNT_NE; 258 break; 259 default: 260 return -EINVAL; 261 } 262 263 wg->update |= UPDATE_IRQ_TYPE; 264 265 return 0; 266 } 267 268 static void wcove_bus_lock(struct irq_data *data) 269 { 270 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 271 struct wcove_gpio *wg = gpiochip_get_data(chip); 272 273 mutex_lock(&wg->buslock); 274 } 275 276 static void wcove_bus_sync_unlock(struct irq_data *data) 277 { 278 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 279 struct wcove_gpio *wg = gpiochip_get_data(chip); 280 int gpio = data->hwirq; 281 282 if (wg->update & UPDATE_IRQ_TYPE) 283 wcove_update_irq_ctrl(wg, gpio); 284 if (wg->update & UPDATE_IRQ_MASK) 285 wcove_update_irq_mask(wg, gpio); 286 wg->update = 0; 287 288 mutex_unlock(&wg->buslock); 289 } 290 291 static void wcove_irq_unmask(struct irq_data *data) 292 { 293 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 294 struct wcove_gpio *wg = gpiochip_get_data(chip); 295 296 if (data->hwirq >= WCOVE_GPIO_NUM) 297 return; 298 299 wg->set_irq_mask = false; 300 wg->update |= UPDATE_IRQ_MASK; 301 } 302 303 static void wcove_irq_mask(struct irq_data *data) 304 { 305 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 306 struct wcove_gpio *wg = gpiochip_get_data(chip); 307 308 if (data->hwirq >= WCOVE_GPIO_NUM) 309 return; 310 311 wg->set_irq_mask = true; 312 wg->update |= UPDATE_IRQ_MASK; 313 } 314 315 static struct irq_chip wcove_irqchip = { 316 .name = "Whiskey Cove", 317 .irq_mask = wcove_irq_mask, 318 .irq_unmask = wcove_irq_unmask, 319 .irq_set_type = wcove_irq_type, 320 .irq_bus_lock = wcove_bus_lock, 321 .irq_bus_sync_unlock = wcove_bus_sync_unlock, 322 }; 323 324 static irqreturn_t wcove_gpio_irq_handler(int irq, void *data) 325 { 326 struct wcove_gpio *wg = (struct wcove_gpio *)data; 327 unsigned int virq, gpio, mask, offset; 328 unsigned long pending; 329 u8 p[2]; 330 331 if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) { 332 dev_err(wg->dev, "Failed to read irq status register\n"); 333 return IRQ_NONE; 334 } 335 336 pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7); 337 if (!pending) 338 return IRQ_NONE; 339 340 /* Iterate until no interrupt is pending */ 341 while (pending) { 342 /* One iteration is for all pending bits */ 343 for_each_set_bit(gpio, &pending, WCOVE_GPIO_NUM) { 344 offset = (gpio > GROUP0_NR_IRQS) ? 1 : 0; 345 mask = (offset == 1) ? BIT(gpio - GROUP0_NR_IRQS) : 346 BIT(gpio); 347 virq = irq_find_mapping(wg->chip.irq.domain, gpio); 348 handle_nested_irq(virq); 349 regmap_update_bits(wg->regmap, IRQ_STATUS_BASE + offset, 350 mask, mask); 351 } 352 353 /* Next iteration */ 354 if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) { 355 dev_err(wg->dev, "Failed to read irq status\n"); 356 break; 357 } 358 359 pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7); 360 } 361 362 return IRQ_HANDLED; 363 } 364 365 static void wcove_gpio_dbg_show(struct seq_file *s, 366 struct gpio_chip *chip) 367 { 368 unsigned int ctlo, ctli, irq_mask, irq_status; 369 struct wcove_gpio *wg = gpiochip_get_data(chip); 370 int gpio, offset, group, ret = 0; 371 372 for (gpio = 0; gpio < WCOVE_GPIO_NUM; gpio++) { 373 group = gpio < GROUP0_NR_IRQS ? 0 : 1; 374 ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo); 375 ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli); 376 ret += regmap_read(wg->regmap, IRQ_MASK_BASE + group, 377 &irq_mask); 378 ret += regmap_read(wg->regmap, IRQ_STATUS_BASE + group, 379 &irq_status); 380 if (ret) { 381 pr_err("Failed to read registers: ctrl out/in or irq status/mask\n"); 382 break; 383 } 384 385 offset = gpio % 8; 386 seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s\n", 387 gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ", 388 ctli & 0x1 ? "hi" : "lo", 389 ctli & CTLI_INTCNT_NE ? "fall" : " ", 390 ctli & CTLI_INTCNT_PE ? "rise" : " ", 391 ctlo, 392 irq_mask & BIT(offset) ? "mask " : "unmask", 393 irq_status & BIT(offset) ? "pending" : " "); 394 } 395 } 396 397 static int wcove_gpio_probe(struct platform_device *pdev) 398 { 399 struct intel_soc_pmic *pmic; 400 struct wcove_gpio *wg; 401 int virq, ret, irq; 402 struct device *dev; 403 struct gpio_irq_chip *girq; 404 405 /* 406 * This gpio platform device is created by a mfd device (see 407 * drivers/mfd/intel_soc_pmic_bxtwc.c for details). Information 408 * shared by all sub-devices created by the mfd device, the regmap 409 * pointer for instance, is stored as driver data of the mfd device 410 * driver. 411 */ 412 pmic = dev_get_drvdata(pdev->dev.parent); 413 if (!pmic) 414 return -ENODEV; 415 416 irq = platform_get_irq(pdev, 0); 417 if (irq < 0) 418 return irq; 419 420 dev = &pdev->dev; 421 422 wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL); 423 if (!wg) 424 return -ENOMEM; 425 426 wg->regmap_irq_chip = pmic->irq_chip_data; 427 428 platform_set_drvdata(pdev, wg); 429 430 mutex_init(&wg->buslock); 431 wg->chip.label = KBUILD_MODNAME; 432 wg->chip.direction_input = wcove_gpio_dir_in; 433 wg->chip.direction_output = wcove_gpio_dir_out; 434 wg->chip.get_direction = wcove_gpio_get_direction; 435 wg->chip.get = wcove_gpio_get; 436 wg->chip.set = wcove_gpio_set; 437 wg->chip.set_config = wcove_gpio_set_config; 438 wg->chip.base = -1; 439 wg->chip.ngpio = WCOVE_VGPIO_NUM; 440 wg->chip.can_sleep = true; 441 wg->chip.parent = pdev->dev.parent; 442 wg->chip.dbg_show = wcove_gpio_dbg_show; 443 wg->dev = dev; 444 wg->regmap = pmic->regmap; 445 446 virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq); 447 if (virq < 0) { 448 dev_err(dev, "Failed to get virq by irq %d\n", irq); 449 return virq; 450 } 451 452 girq = &wg->chip.irq; 453 girq->chip = &wcove_irqchip; 454 /* This will let us handle the parent IRQ in the driver */ 455 girq->parent_handler = NULL; 456 girq->num_parents = 0; 457 girq->parents = NULL; 458 girq->default_type = IRQ_TYPE_NONE; 459 girq->handler = handle_simple_irq; 460 girq->threaded = true; 461 462 ret = devm_request_threaded_irq(dev, virq, NULL, wcove_gpio_irq_handler, 463 IRQF_ONESHOT, pdev->name, wg); 464 if (ret) { 465 dev_err(dev, "Failed to request irq %d\n", virq); 466 return ret; 467 } 468 469 ret = devm_gpiochip_add_data(dev, &wg->chip, wg); 470 if (ret) { 471 dev_err(dev, "Failed to add gpiochip: %d\n", ret); 472 return ret; 473 } 474 475 /* Enable GPIO0 interrupts */ 476 ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE, GPIO_IRQ0_MASK, 477 0x00); 478 if (ret) 479 return ret; 480 481 /* Enable GPIO1 interrupts */ 482 ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK, 483 0x00); 484 if (ret) 485 return ret; 486 487 return 0; 488 } 489 490 /* 491 * Whiskey Cove PMIC itself is a analog device(but with digital control 492 * interface) providing power management support for other devices in 493 * the accompanied SoC, so we have no .pm for Whiskey Cove GPIO driver. 494 */ 495 static struct platform_driver wcove_gpio_driver = { 496 .driver = { 497 .name = "bxt_wcove_gpio", 498 }, 499 .probe = wcove_gpio_probe, 500 }; 501 502 module_platform_driver(wcove_gpio_driver); 503 504 MODULE_AUTHOR("Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>"); 505 MODULE_AUTHOR("Bin Gao <bin.gao@intel.com>"); 506 MODULE_DESCRIPTION("Intel Whiskey Cove GPIO Driver"); 507 MODULE_LICENSE("GPL v2"); 508 MODULE_ALIAS("platform:bxt_wcove_gpio"); 509