1 /* 2 * Freescale vf610 GPIO support through PORT and GPIO 3 * 4 * Copyright (c) 2014 Toradex AG. 5 * 6 * Author: Stefan Agner <stefan@agner.ch>. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 2 11 * of the License, or (at your option) any later version. 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/bitops.h> 19 #include <linux/err.h> 20 #include <linux/gpio.h> 21 #include <linux/init.h> 22 #include <linux/interrupt.h> 23 #include <linux/io.h> 24 #include <linux/ioport.h> 25 #include <linux/irq.h> 26 #include <linux/platform_device.h> 27 #include <linux/of.h> 28 #include <linux/of_device.h> 29 #include <linux/of_irq.h> 30 31 #define VF610_GPIO_PER_PORT 32 32 33 struct fsl_gpio_soc_data { 34 /* SoCs has a Port Data Direction Register (PDDR) */ 35 bool have_paddr; 36 }; 37 38 struct vf610_gpio_port { 39 struct gpio_chip gc; 40 void __iomem *base; 41 void __iomem *gpio_base; 42 const struct fsl_gpio_soc_data *sdata; 43 u8 irqc[VF610_GPIO_PER_PORT]; 44 int irq; 45 }; 46 47 #define GPIO_PDOR 0x00 48 #define GPIO_PSOR 0x04 49 #define GPIO_PCOR 0x08 50 #define GPIO_PTOR 0x0c 51 #define GPIO_PDIR 0x10 52 #define GPIO_PDDR 0x14 53 54 #define PORT_PCR(n) ((n) * 0x4) 55 #define PORT_PCR_IRQC_OFFSET 16 56 57 #define PORT_ISFR 0xa0 58 #define PORT_DFER 0xc0 59 #define PORT_DFCR 0xc4 60 #define PORT_DFWR 0xc8 61 62 #define PORT_INT_OFF 0x0 63 #define PORT_INT_LOGIC_ZERO 0x8 64 #define PORT_INT_RISING_EDGE 0x9 65 #define PORT_INT_FALLING_EDGE 0xa 66 #define PORT_INT_EITHER_EDGE 0xb 67 #define PORT_INT_LOGIC_ONE 0xc 68 69 static struct irq_chip vf610_gpio_irq_chip; 70 71 static const struct fsl_gpio_soc_data imx_data = { 72 .have_paddr = true, 73 }; 74 75 static const struct of_device_id vf610_gpio_dt_ids[] = { 76 { .compatible = "fsl,vf610-gpio", .data = NULL, }, 77 { .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, }, 78 { /* sentinel */ } 79 }; 80 81 static inline void vf610_gpio_writel(u32 val, void __iomem *reg) 82 { 83 writel_relaxed(val, reg); 84 } 85 86 static inline u32 vf610_gpio_readl(void __iomem *reg) 87 { 88 return readl_relaxed(reg); 89 } 90 91 static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio) 92 { 93 struct vf610_gpio_port *port = gpiochip_get_data(gc); 94 unsigned long mask = BIT(gpio); 95 void __iomem *addr; 96 97 if (port->sdata && port->sdata->have_paddr) { 98 mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR); 99 addr = mask ? port->gpio_base + GPIO_PDOR : 100 port->gpio_base + GPIO_PDIR; 101 return !!(vf610_gpio_readl(addr) & BIT(gpio)); 102 } else { 103 return !!(vf610_gpio_readl(port->gpio_base + GPIO_PDIR) 104 & BIT(gpio)); 105 } 106 } 107 108 static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 109 { 110 struct vf610_gpio_port *port = gpiochip_get_data(gc); 111 unsigned long mask = BIT(gpio); 112 113 if (val) 114 vf610_gpio_writel(mask, port->gpio_base + GPIO_PSOR); 115 else 116 vf610_gpio_writel(mask, port->gpio_base + GPIO_PCOR); 117 } 118 119 static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) 120 { 121 struct vf610_gpio_port *port = gpiochip_get_data(chip); 122 unsigned long mask = BIT(gpio); 123 u32 val; 124 125 if (port->sdata && port->sdata->have_paddr) { 126 val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR); 127 val &= ~mask; 128 vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR); 129 } 130 131 return pinctrl_gpio_direction_input(chip->base + gpio); 132 } 133 134 static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, 135 int value) 136 { 137 struct vf610_gpio_port *port = gpiochip_get_data(chip); 138 unsigned long mask = BIT(gpio); 139 140 if (port->sdata && port->sdata->have_paddr) 141 vf610_gpio_writel(mask, port->gpio_base + GPIO_PDDR); 142 143 vf610_gpio_set(chip, gpio, value); 144 145 return pinctrl_gpio_direction_output(chip->base + gpio); 146 } 147 148 static void vf610_gpio_irq_handler(struct irq_desc *desc) 149 { 150 struct vf610_gpio_port *port = 151 gpiochip_get_data(irq_desc_get_handler_data(desc)); 152 struct irq_chip *chip = irq_desc_get_chip(desc); 153 int pin; 154 unsigned long irq_isfr; 155 156 chained_irq_enter(chip, desc); 157 158 irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR); 159 160 for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) { 161 vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR); 162 163 generic_handle_irq(irq_find_mapping(port->gc.irq.domain, pin)); 164 } 165 166 chained_irq_exit(chip, desc); 167 } 168 169 static void vf610_gpio_irq_ack(struct irq_data *d) 170 { 171 struct vf610_gpio_port *port = 172 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 173 int gpio = d->hwirq; 174 175 vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR); 176 } 177 178 static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type) 179 { 180 struct vf610_gpio_port *port = 181 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 182 u8 irqc; 183 184 switch (type) { 185 case IRQ_TYPE_EDGE_RISING: 186 irqc = PORT_INT_RISING_EDGE; 187 break; 188 case IRQ_TYPE_EDGE_FALLING: 189 irqc = PORT_INT_FALLING_EDGE; 190 break; 191 case IRQ_TYPE_EDGE_BOTH: 192 irqc = PORT_INT_EITHER_EDGE; 193 break; 194 case IRQ_TYPE_LEVEL_LOW: 195 irqc = PORT_INT_LOGIC_ZERO; 196 break; 197 case IRQ_TYPE_LEVEL_HIGH: 198 irqc = PORT_INT_LOGIC_ONE; 199 break; 200 default: 201 return -EINVAL; 202 } 203 204 port->irqc[d->hwirq] = irqc; 205 206 if (type & IRQ_TYPE_LEVEL_MASK) 207 irq_set_handler_locked(d, handle_level_irq); 208 else 209 irq_set_handler_locked(d, handle_edge_irq); 210 211 return 0; 212 } 213 214 static void vf610_gpio_irq_mask(struct irq_data *d) 215 { 216 struct vf610_gpio_port *port = 217 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 218 void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq); 219 220 vf610_gpio_writel(0, pcr_base); 221 } 222 223 static void vf610_gpio_irq_unmask(struct irq_data *d) 224 { 225 struct vf610_gpio_port *port = 226 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 227 void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq); 228 229 vf610_gpio_writel(port->irqc[d->hwirq] << PORT_PCR_IRQC_OFFSET, 230 pcr_base); 231 } 232 233 static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable) 234 { 235 struct vf610_gpio_port *port = 236 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 237 238 if (enable) 239 enable_irq_wake(port->irq); 240 else 241 disable_irq_wake(port->irq); 242 243 return 0; 244 } 245 246 static struct irq_chip vf610_gpio_irq_chip = { 247 .name = "gpio-vf610", 248 .irq_ack = vf610_gpio_irq_ack, 249 .irq_mask = vf610_gpio_irq_mask, 250 .irq_unmask = vf610_gpio_irq_unmask, 251 .irq_set_type = vf610_gpio_irq_set_type, 252 .irq_set_wake = vf610_gpio_irq_set_wake, 253 }; 254 255 static int vf610_gpio_probe(struct platform_device *pdev) 256 { 257 struct device *dev = &pdev->dev; 258 struct device_node *np = dev->of_node; 259 struct vf610_gpio_port *port; 260 struct resource *iores; 261 struct gpio_chip *gc; 262 int ret; 263 264 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); 265 if (!port) 266 return -ENOMEM; 267 268 port->sdata = of_device_get_match_data(dev); 269 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 270 port->base = devm_ioremap_resource(dev, iores); 271 if (IS_ERR(port->base)) 272 return PTR_ERR(port->base); 273 274 iores = platform_get_resource(pdev, IORESOURCE_MEM, 1); 275 port->gpio_base = devm_ioremap_resource(dev, iores); 276 if (IS_ERR(port->gpio_base)) 277 return PTR_ERR(port->gpio_base); 278 279 port->irq = platform_get_irq(pdev, 0); 280 if (port->irq < 0) 281 return port->irq; 282 283 gc = &port->gc; 284 gc->of_node = np; 285 gc->parent = dev; 286 gc->label = "vf610-gpio"; 287 gc->ngpio = VF610_GPIO_PER_PORT; 288 gc->base = of_alias_get_id(np, "gpio") * VF610_GPIO_PER_PORT; 289 290 gc->request = gpiochip_generic_request; 291 gc->free = gpiochip_generic_free; 292 gc->direction_input = vf610_gpio_direction_input; 293 gc->get = vf610_gpio_get; 294 gc->direction_output = vf610_gpio_direction_output; 295 gc->set = vf610_gpio_set; 296 297 ret = gpiochip_add_data(gc, port); 298 if (ret < 0) 299 return ret; 300 301 /* Clear the interrupt status register for all GPIO's */ 302 vf610_gpio_writel(~0, port->base + PORT_ISFR); 303 304 ret = gpiochip_irqchip_add(gc, &vf610_gpio_irq_chip, 0, 305 handle_edge_irq, IRQ_TYPE_NONE); 306 if (ret) { 307 dev_err(dev, "failed to add irqchip\n"); 308 gpiochip_remove(gc); 309 return ret; 310 } 311 gpiochip_set_chained_irqchip(gc, &vf610_gpio_irq_chip, port->irq, 312 vf610_gpio_irq_handler); 313 314 return 0; 315 } 316 317 static struct platform_driver vf610_gpio_driver = { 318 .driver = { 319 .name = "gpio-vf610", 320 .of_match_table = vf610_gpio_dt_ids, 321 }, 322 .probe = vf610_gpio_probe, 323 }; 324 325 builtin_platform_driver(vf610_gpio_driver); 326