1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Freescale vf610 GPIO support through PORT and GPIO
4 *
5 * Copyright (c) 2014 Toradex AG.
6 *
7 * Author: Stefan Agner <stefan@agner.ch>.
8 */
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/err.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/ioport.h>
17 #include <linux/irq.h>
18 #include <linux/platform_device.h>
19 #include <linux/of.h>
20 #include <linux/of_irq.h>
21 #include <linux/pinctrl/consumer.h>
22
23 #define VF610_GPIO_PER_PORT 32
24
25 struct fsl_gpio_soc_data {
26 /* SoCs has a Port Data Direction Register (PDDR) */
27 bool have_paddr;
28 };
29
30 struct vf610_gpio_port {
31 struct gpio_chip gc;
32 void __iomem *base;
33 void __iomem *gpio_base;
34 const struct fsl_gpio_soc_data *sdata;
35 u8 irqc[VF610_GPIO_PER_PORT];
36 struct clk *clk_port;
37 struct clk *clk_gpio;
38 int irq;
39 };
40
41 #define GPIO_PDOR 0x00
42 #define GPIO_PSOR 0x04
43 #define GPIO_PCOR 0x08
44 #define GPIO_PTOR 0x0c
45 #define GPIO_PDIR 0x10
46 #define GPIO_PDDR 0x14
47
48 #define PORT_PCR(n) ((n) * 0x4)
49 #define PORT_PCR_IRQC_OFFSET 16
50
51 #define PORT_ISFR 0xa0
52 #define PORT_DFER 0xc0
53 #define PORT_DFCR 0xc4
54 #define PORT_DFWR 0xc8
55
56 #define PORT_INT_OFF 0x0
57 #define PORT_INT_LOGIC_ZERO 0x8
58 #define PORT_INT_RISING_EDGE 0x9
59 #define PORT_INT_FALLING_EDGE 0xa
60 #define PORT_INT_EITHER_EDGE 0xb
61 #define PORT_INT_LOGIC_ONE 0xc
62
63 static const struct fsl_gpio_soc_data imx_data = {
64 .have_paddr = true,
65 };
66
67 static const struct of_device_id vf610_gpio_dt_ids[] = {
68 { .compatible = "fsl,vf610-gpio", .data = NULL, },
69 { .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, },
70 { /* sentinel */ }
71 };
72
vf610_gpio_writel(u32 val,void __iomem * reg)73 static inline void vf610_gpio_writel(u32 val, void __iomem *reg)
74 {
75 writel_relaxed(val, reg);
76 }
77
vf610_gpio_readl(void __iomem * reg)78 static inline u32 vf610_gpio_readl(void __iomem *reg)
79 {
80 return readl_relaxed(reg);
81 }
82
vf610_gpio_get(struct gpio_chip * gc,unsigned int gpio)83 static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio)
84 {
85 struct vf610_gpio_port *port = gpiochip_get_data(gc);
86 unsigned long mask = BIT(gpio);
87 unsigned long offset = GPIO_PDIR;
88
89 if (port->sdata && port->sdata->have_paddr) {
90 mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
91 if (mask)
92 offset = GPIO_PDOR;
93 }
94
95 return !!(vf610_gpio_readl(port->gpio_base + offset) & BIT(gpio));
96 }
97
vf610_gpio_set(struct gpio_chip * gc,unsigned int gpio,int val)98 static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
99 {
100 struct vf610_gpio_port *port = gpiochip_get_data(gc);
101 unsigned long mask = BIT(gpio);
102 unsigned long offset = val ? GPIO_PSOR : GPIO_PCOR;
103
104 vf610_gpio_writel(mask, port->gpio_base + offset);
105 }
106
vf610_gpio_direction_input(struct gpio_chip * chip,unsigned gpio)107 static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
108 {
109 struct vf610_gpio_port *port = gpiochip_get_data(chip);
110 unsigned long mask = BIT(gpio);
111 u32 val;
112
113 if (port->sdata && port->sdata->have_paddr) {
114 val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
115 val &= ~mask;
116 vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
117 }
118
119 return pinctrl_gpio_direction_input(chip->base + gpio);
120 }
121
vf610_gpio_direction_output(struct gpio_chip * chip,unsigned gpio,int value)122 static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
123 int value)
124 {
125 struct vf610_gpio_port *port = gpiochip_get_data(chip);
126 unsigned long mask = BIT(gpio);
127 u32 val;
128
129 vf610_gpio_set(chip, gpio, value);
130
131 if (port->sdata && port->sdata->have_paddr) {
132 val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
133 val |= mask;
134 vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
135 }
136
137 return pinctrl_gpio_direction_output(chip->base + gpio);
138 }
139
vf610_gpio_irq_handler(struct irq_desc * desc)140 static void vf610_gpio_irq_handler(struct irq_desc *desc)
141 {
142 struct vf610_gpio_port *port =
143 gpiochip_get_data(irq_desc_get_handler_data(desc));
144 struct irq_chip *chip = irq_desc_get_chip(desc);
145 int pin;
146 unsigned long irq_isfr;
147
148 chained_irq_enter(chip, desc);
149
150 irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR);
151
152 for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
153 vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);
154
155 generic_handle_domain_irq(port->gc.irq.domain, pin);
156 }
157
158 chained_irq_exit(chip, desc);
159 }
160
vf610_gpio_irq_ack(struct irq_data * d)161 static void vf610_gpio_irq_ack(struct irq_data *d)
162 {
163 struct vf610_gpio_port *port =
164 gpiochip_get_data(irq_data_get_irq_chip_data(d));
165 int gpio = d->hwirq;
166
167 vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR);
168 }
169
vf610_gpio_irq_set_type(struct irq_data * d,u32 type)170 static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type)
171 {
172 struct vf610_gpio_port *port =
173 gpiochip_get_data(irq_data_get_irq_chip_data(d));
174 u8 irqc;
175
176 switch (type) {
177 case IRQ_TYPE_EDGE_RISING:
178 irqc = PORT_INT_RISING_EDGE;
179 break;
180 case IRQ_TYPE_EDGE_FALLING:
181 irqc = PORT_INT_FALLING_EDGE;
182 break;
183 case IRQ_TYPE_EDGE_BOTH:
184 irqc = PORT_INT_EITHER_EDGE;
185 break;
186 case IRQ_TYPE_LEVEL_LOW:
187 irqc = PORT_INT_LOGIC_ZERO;
188 break;
189 case IRQ_TYPE_LEVEL_HIGH:
190 irqc = PORT_INT_LOGIC_ONE;
191 break;
192 default:
193 return -EINVAL;
194 }
195
196 port->irqc[d->hwirq] = irqc;
197
198 if (type & IRQ_TYPE_LEVEL_MASK)
199 irq_set_handler_locked(d, handle_level_irq);
200 else
201 irq_set_handler_locked(d, handle_edge_irq);
202
203 return 0;
204 }
205
vf610_gpio_irq_mask(struct irq_data * d)206 static void vf610_gpio_irq_mask(struct irq_data *d)
207 {
208 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
209 struct vf610_gpio_port *port = gpiochip_get_data(gc);
210 irq_hw_number_t gpio_num = irqd_to_hwirq(d);
211 void __iomem *pcr_base = port->base + PORT_PCR(gpio_num);
212
213 vf610_gpio_writel(0, pcr_base);
214 gpiochip_disable_irq(gc, gpio_num);
215 }
216
vf610_gpio_irq_unmask(struct irq_data * d)217 static void vf610_gpio_irq_unmask(struct irq_data *d)
218 {
219 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
220 struct vf610_gpio_port *port = gpiochip_get_data(gc);
221 irq_hw_number_t gpio_num = irqd_to_hwirq(d);
222 void __iomem *pcr_base = port->base + PORT_PCR(gpio_num);
223
224 gpiochip_enable_irq(gc, gpio_num);
225 vf610_gpio_writel(port->irqc[gpio_num] << PORT_PCR_IRQC_OFFSET,
226 pcr_base);
227 }
228
vf610_gpio_irq_set_wake(struct irq_data * d,u32 enable)229 static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable)
230 {
231 struct vf610_gpio_port *port =
232 gpiochip_get_data(irq_data_get_irq_chip_data(d));
233
234 if (enable)
235 enable_irq_wake(port->irq);
236 else
237 disable_irq_wake(port->irq);
238
239 return 0;
240 }
241
242 static const struct irq_chip vf610_irqchip = {
243 .name = "gpio-vf610",
244 .irq_ack = vf610_gpio_irq_ack,
245 .irq_mask = vf610_gpio_irq_mask,
246 .irq_unmask = vf610_gpio_irq_unmask,
247 .irq_set_type = vf610_gpio_irq_set_type,
248 .irq_set_wake = vf610_gpio_irq_set_wake,
249 .flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND
250 | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
251 GPIOCHIP_IRQ_RESOURCE_HELPERS,
252 };
253
vf610_gpio_disable_clk(void * data)254 static void vf610_gpio_disable_clk(void *data)
255 {
256 clk_disable_unprepare(data);
257 }
258
vf610_gpio_probe(struct platform_device * pdev)259 static int vf610_gpio_probe(struct platform_device *pdev)
260 {
261 struct device *dev = &pdev->dev;
262 struct vf610_gpio_port *port;
263 struct gpio_chip *gc;
264 struct gpio_irq_chip *girq;
265 int i;
266 int ret;
267
268 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
269 if (!port)
270 return -ENOMEM;
271
272 port->sdata = of_device_get_match_data(dev);
273 port->base = devm_platform_ioremap_resource(pdev, 0);
274 if (IS_ERR(port->base))
275 return PTR_ERR(port->base);
276
277 port->gpio_base = devm_platform_ioremap_resource(pdev, 1);
278 if (IS_ERR(port->gpio_base))
279 return PTR_ERR(port->gpio_base);
280
281 port->irq = platform_get_irq(pdev, 0);
282 if (port->irq < 0)
283 return port->irq;
284
285 port->clk_port = devm_clk_get(dev, "port");
286 ret = PTR_ERR_OR_ZERO(port->clk_port);
287 if (!ret) {
288 ret = clk_prepare_enable(port->clk_port);
289 if (ret)
290 return ret;
291 ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
292 port->clk_port);
293 if (ret)
294 return ret;
295 } else if (ret == -EPROBE_DEFER) {
296 /*
297 * Percolate deferrals, for anything else,
298 * just live without the clocking.
299 */
300 return ret;
301 }
302
303 port->clk_gpio = devm_clk_get(dev, "gpio");
304 ret = PTR_ERR_OR_ZERO(port->clk_gpio);
305 if (!ret) {
306 ret = clk_prepare_enable(port->clk_gpio);
307 if (ret)
308 return ret;
309 ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
310 port->clk_gpio);
311 if (ret)
312 return ret;
313 } else if (ret == -EPROBE_DEFER) {
314 return ret;
315 }
316
317 gc = &port->gc;
318 gc->parent = dev;
319 gc->label = dev_name(dev);
320 gc->ngpio = VF610_GPIO_PER_PORT;
321 gc->base = -1;
322
323 gc->request = gpiochip_generic_request;
324 gc->free = gpiochip_generic_free;
325 gc->direction_input = vf610_gpio_direction_input;
326 gc->get = vf610_gpio_get;
327 gc->direction_output = vf610_gpio_direction_output;
328 gc->set = vf610_gpio_set;
329
330 /* Mask all GPIO interrupts */
331 for (i = 0; i < gc->ngpio; i++)
332 vf610_gpio_writel(0, port->base + PORT_PCR(i));
333
334 /* Clear the interrupt status register for all GPIO's */
335 vf610_gpio_writel(~0, port->base + PORT_ISFR);
336
337 girq = &gc->irq;
338 gpio_irq_chip_set_chip(girq, &vf610_irqchip);
339 girq->parent_handler = vf610_gpio_irq_handler;
340 girq->num_parents = 1;
341 girq->parents = devm_kcalloc(&pdev->dev, 1,
342 sizeof(*girq->parents),
343 GFP_KERNEL);
344 if (!girq->parents)
345 return -ENOMEM;
346 girq->parents[0] = port->irq;
347 girq->default_type = IRQ_TYPE_NONE;
348 girq->handler = handle_edge_irq;
349
350 return devm_gpiochip_add_data(dev, gc, port);
351 }
352
353 static struct platform_driver vf610_gpio_driver = {
354 .driver = {
355 .name = "gpio-vf610",
356 .of_match_table = vf610_gpio_dt_ids,
357 },
358 .probe = vf610_gpio_probe,
359 };
360
361 builtin_platform_driver(vf610_gpio_driver);
362