136e2add1SLinus Walleij // SPDX-License-Identifier: GPL-2.0+ 27f2691a1SStefan Agner /* 3adaaf63eSPaul Gortmaker * Freescale vf610 GPIO support through PORT and GPIO 47f2691a1SStefan Agner * 57f2691a1SStefan Agner * Copyright (c) 2014 Toradex AG. 67f2691a1SStefan Agner * 77f2691a1SStefan Agner * Author: Stefan Agner <stefan@agner.ch>. 87f2691a1SStefan Agner */ 97f2691a1SStefan Agner #include <linux/bitops.h> 1091393622SA.s. Dong #include <linux/clk.h> 117f2691a1SStefan Agner #include <linux/err.h> 1245e8296cSLinus Walleij #include <linux/gpio/driver.h> 137f2691a1SStefan Agner #include <linux/init.h> 147f2691a1SStefan Agner #include <linux/interrupt.h> 157f2691a1SStefan Agner #include <linux/io.h> 167f2691a1SStefan Agner #include <linux/ioport.h> 177f2691a1SStefan Agner #include <linux/irq.h> 187f2691a1SStefan Agner #include <linux/platform_device.h> 197f2691a1SStefan Agner #include <linux/of.h> 207f2691a1SStefan Agner #include <linux/of_irq.h> 218af3a0b2SLeon Romanovsky #include <linux/pinctrl/consumer.h> 227f2691a1SStefan Agner 237f2691a1SStefan Agner #define VF610_GPIO_PER_PORT 32 247f2691a1SStefan Agner 25659d8a62SDong Aisheng struct fsl_gpio_soc_data { 26659d8a62SDong Aisheng /* SoCs has a Port Data Direction Register (PDDR) */ 27659d8a62SDong Aisheng bool have_paddr; 28659d8a62SDong Aisheng }; 29659d8a62SDong Aisheng 307f2691a1SStefan Agner struct vf610_gpio_port { 317f2691a1SStefan Agner struct gpio_chip gc; 327f2691a1SStefan Agner void __iomem *base; 337f2691a1SStefan Agner void __iomem *gpio_base; 34659d8a62SDong Aisheng const struct fsl_gpio_soc_data *sdata; 357f2691a1SStefan Agner u8 irqc[VF610_GPIO_PER_PORT]; 3691393622SA.s. Dong struct clk *clk_port; 3791393622SA.s. Dong struct clk *clk_gpio; 387f2691a1SStefan Agner int irq; 397f2691a1SStefan Agner }; 407f2691a1SStefan Agner 417f2691a1SStefan Agner #define GPIO_PDOR 0x00 427f2691a1SStefan Agner #define GPIO_PSOR 0x04 437f2691a1SStefan Agner #define GPIO_PCOR 0x08 447f2691a1SStefan Agner #define GPIO_PTOR 0x0c 457f2691a1SStefan Agner #define GPIO_PDIR 0x10 46659d8a62SDong Aisheng #define GPIO_PDDR 0x14 477f2691a1SStefan Agner 487f2691a1SStefan Agner #define PORT_PCR(n) ((n) * 0x4) 497f2691a1SStefan Agner #define PORT_PCR_IRQC_OFFSET 16 507f2691a1SStefan Agner 517f2691a1SStefan Agner #define PORT_ISFR 0xa0 527f2691a1SStefan Agner #define PORT_DFER 0xc0 537f2691a1SStefan Agner #define PORT_DFCR 0xc4 547f2691a1SStefan Agner #define PORT_DFWR 0xc8 557f2691a1SStefan Agner 567f2691a1SStefan Agner #define PORT_INT_OFF 0x0 577f2691a1SStefan Agner #define PORT_INT_LOGIC_ZERO 0x8 587f2691a1SStefan Agner #define PORT_INT_RISING_EDGE 0x9 597f2691a1SStefan Agner #define PORT_INT_FALLING_EDGE 0xa 607f2691a1SStefan Agner #define PORT_INT_EITHER_EDGE 0xb 617f2691a1SStefan Agner #define PORT_INT_LOGIC_ONE 0xc 627f2691a1SStefan Agner 63659d8a62SDong Aisheng static const struct fsl_gpio_soc_data imx_data = { 64659d8a62SDong Aisheng .have_paddr = true, 65659d8a62SDong Aisheng }; 66659d8a62SDong Aisheng 677f2691a1SStefan Agner static const struct of_device_id vf610_gpio_dt_ids[] = { 68659d8a62SDong Aisheng { .compatible = "fsl,vf610-gpio", .data = NULL, }, 69659d8a62SDong Aisheng { .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, }, 707f2691a1SStefan Agner { /* sentinel */ } 717f2691a1SStefan Agner }; 727f2691a1SStefan Agner 737f2691a1SStefan Agner static inline void vf610_gpio_writel(u32 val, void __iomem *reg) 747f2691a1SStefan Agner { 757f2691a1SStefan Agner writel_relaxed(val, reg); 767f2691a1SStefan Agner } 777f2691a1SStefan Agner 787f2691a1SStefan Agner static inline u32 vf610_gpio_readl(void __iomem *reg) 797f2691a1SStefan Agner { 807f2691a1SStefan Agner return readl_relaxed(reg); 817f2691a1SStefan Agner } 827f2691a1SStefan Agner 837f2691a1SStefan Agner static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio) 847f2691a1SStefan Agner { 8565389b49SLinus Walleij struct vf610_gpio_port *port = gpiochip_get_data(gc); 86659d8a62SDong Aisheng unsigned long mask = BIT(gpio); 874a8909d0SAndrey Smirnov unsigned long offset = GPIO_PDIR; 887f2691a1SStefan Agner 89659d8a62SDong Aisheng if (port->sdata && port->sdata->have_paddr) { 90659d8a62SDong Aisheng mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR); 914a8909d0SAndrey Smirnov if (mask) 924a8909d0SAndrey Smirnov offset = GPIO_PDOR; 93659d8a62SDong Aisheng } 944a8909d0SAndrey Smirnov 954a8909d0SAndrey Smirnov return !!(vf610_gpio_readl(port->gpio_base + offset) & BIT(gpio)); 967f2691a1SStefan Agner } 977f2691a1SStefan Agner 987f2691a1SStefan Agner static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 997f2691a1SStefan Agner { 10065389b49SLinus Walleij struct vf610_gpio_port *port = gpiochip_get_data(gc); 1017f2691a1SStefan Agner unsigned long mask = BIT(gpio); 102a262555bSAndrey Smirnov unsigned long offset = val ? GPIO_PSOR : GPIO_PCOR; 1037f2691a1SStefan Agner 104a262555bSAndrey Smirnov vf610_gpio_writel(mask, port->gpio_base + offset); 1057f2691a1SStefan Agner } 1067f2691a1SStefan Agner 1077f2691a1SStefan Agner static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) 1087f2691a1SStefan Agner { 109659d8a62SDong Aisheng struct vf610_gpio_port *port = gpiochip_get_data(chip); 110659d8a62SDong Aisheng unsigned long mask = BIT(gpio); 111659d8a62SDong Aisheng u32 val; 112659d8a62SDong Aisheng 113659d8a62SDong Aisheng if (port->sdata && port->sdata->have_paddr) { 114659d8a62SDong Aisheng val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR); 115659d8a62SDong Aisheng val &= ~mask; 116659d8a62SDong Aisheng vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR); 117659d8a62SDong Aisheng } 118659d8a62SDong Aisheng 1197f2691a1SStefan Agner return pinctrl_gpio_direction_input(chip->base + gpio); 1207f2691a1SStefan Agner } 1217f2691a1SStefan Agner 1227f2691a1SStefan Agner static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, 1237f2691a1SStefan Agner int value) 1247f2691a1SStefan Agner { 125659d8a62SDong Aisheng struct vf610_gpio_port *port = gpiochip_get_data(chip); 126659d8a62SDong Aisheng unsigned long mask = BIT(gpio); 1279bf3ac46SHaibo Chen u32 val; 128659d8a62SDong Aisheng 1299bf3ac46SHaibo Chen if (port->sdata && port->sdata->have_paddr) { 1309bf3ac46SHaibo Chen val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR); 1319bf3ac46SHaibo Chen val |= mask; 1329bf3ac46SHaibo Chen vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR); 1339bf3ac46SHaibo Chen } 134659d8a62SDong Aisheng 1357f2691a1SStefan Agner vf610_gpio_set(chip, gpio, value); 1367f2691a1SStefan Agner 1377f2691a1SStefan Agner return pinctrl_gpio_direction_output(chip->base + gpio); 1387f2691a1SStefan Agner } 1397f2691a1SStefan Agner 140bd0b9ac4SThomas Gleixner static void vf610_gpio_irq_handler(struct irq_desc *desc) 1417f2691a1SStefan Agner { 1422f930643SLinus Walleij struct vf610_gpio_port *port = 14365389b49SLinus Walleij gpiochip_get_data(irq_desc_get_handler_data(desc)); 1447f2691a1SStefan Agner struct irq_chip *chip = irq_desc_get_chip(desc); 1457f2691a1SStefan Agner int pin; 1467f2691a1SStefan Agner unsigned long irq_isfr; 1477f2691a1SStefan Agner 1487f2691a1SStefan Agner chained_irq_enter(chip, desc); 1497f2691a1SStefan Agner 1507f2691a1SStefan Agner irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR); 1517f2691a1SStefan Agner 1527f2691a1SStefan Agner for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) { 1537f2691a1SStefan Agner vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR); 1547f2691a1SStefan Agner 155dbd1c54fSMarc Zyngier generic_handle_domain_irq(port->gc.irq.domain, pin); 1567f2691a1SStefan Agner } 1577f2691a1SStefan Agner 1587f2691a1SStefan Agner chained_irq_exit(chip, desc); 1597f2691a1SStefan Agner } 1607f2691a1SStefan Agner 1617f2691a1SStefan Agner static void vf610_gpio_irq_ack(struct irq_data *d) 1627f2691a1SStefan Agner { 1632f930643SLinus Walleij struct vf610_gpio_port *port = 16465389b49SLinus Walleij gpiochip_get_data(irq_data_get_irq_chip_data(d)); 1657f2691a1SStefan Agner int gpio = d->hwirq; 1667f2691a1SStefan Agner 1677f2691a1SStefan Agner vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR); 1687f2691a1SStefan Agner } 1697f2691a1SStefan Agner 1707f2691a1SStefan Agner static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type) 1717f2691a1SStefan Agner { 1722f930643SLinus Walleij struct vf610_gpio_port *port = 17365389b49SLinus Walleij gpiochip_get_data(irq_data_get_irq_chip_data(d)); 1747f2691a1SStefan Agner u8 irqc; 1757f2691a1SStefan Agner 1767f2691a1SStefan Agner switch (type) { 1777f2691a1SStefan Agner case IRQ_TYPE_EDGE_RISING: 1787f2691a1SStefan Agner irqc = PORT_INT_RISING_EDGE; 1797f2691a1SStefan Agner break; 1807f2691a1SStefan Agner case IRQ_TYPE_EDGE_FALLING: 1817f2691a1SStefan Agner irqc = PORT_INT_FALLING_EDGE; 1827f2691a1SStefan Agner break; 1837f2691a1SStefan Agner case IRQ_TYPE_EDGE_BOTH: 1847f2691a1SStefan Agner irqc = PORT_INT_EITHER_EDGE; 1857f2691a1SStefan Agner break; 1867f2691a1SStefan Agner case IRQ_TYPE_LEVEL_LOW: 1877f2691a1SStefan Agner irqc = PORT_INT_LOGIC_ZERO; 1887f2691a1SStefan Agner break; 1897f2691a1SStefan Agner case IRQ_TYPE_LEVEL_HIGH: 1907f2691a1SStefan Agner irqc = PORT_INT_LOGIC_ONE; 1917f2691a1SStefan Agner break; 1927f2691a1SStefan Agner default: 1937f2691a1SStefan Agner return -EINVAL; 1947f2691a1SStefan Agner } 1957f2691a1SStefan Agner 1967f2691a1SStefan Agner port->irqc[d->hwirq] = irqc; 1977f2691a1SStefan Agner 198fd968115SStefan Agner if (type & IRQ_TYPE_LEVEL_MASK) 199a7147db0SThomas Gleixner irq_set_handler_locked(d, handle_level_irq); 200fd968115SStefan Agner else 201a7147db0SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 202fd968115SStefan Agner 2037f2691a1SStefan Agner return 0; 2047f2691a1SStefan Agner } 2057f2691a1SStefan Agner 2067f2691a1SStefan Agner static void vf610_gpio_irq_mask(struct irq_data *d) 2077f2691a1SStefan Agner { 208e6ef4f8eSAlexander Stein struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 209e6ef4f8eSAlexander Stein struct vf610_gpio_port *port = gpiochip_get_data(gc); 210e6ef4f8eSAlexander Stein irq_hw_number_t gpio_num = irqd_to_hwirq(d); 211e6ef4f8eSAlexander Stein void __iomem *pcr_base = port->base + PORT_PCR(gpio_num); 2127f2691a1SStefan Agner 2137f2691a1SStefan Agner vf610_gpio_writel(0, pcr_base); 214e6ef4f8eSAlexander Stein gpiochip_disable_irq(gc, gpio_num); 2157f2691a1SStefan Agner } 2167f2691a1SStefan Agner 2177f2691a1SStefan Agner static void vf610_gpio_irq_unmask(struct irq_data *d) 2187f2691a1SStefan Agner { 219e6ef4f8eSAlexander Stein struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 220e6ef4f8eSAlexander Stein struct vf610_gpio_port *port = gpiochip_get_data(gc); 221e6ef4f8eSAlexander Stein irq_hw_number_t gpio_num = irqd_to_hwirq(d); 222e6ef4f8eSAlexander Stein void __iomem *pcr_base = port->base + PORT_PCR(gpio_num); 2237f2691a1SStefan Agner 224e6ef4f8eSAlexander Stein gpiochip_enable_irq(gc, gpio_num); 225e6ef4f8eSAlexander Stein vf610_gpio_writel(port->irqc[gpio_num] << PORT_PCR_IRQC_OFFSET, 2267f2691a1SStefan Agner pcr_base); 2277f2691a1SStefan Agner } 2287f2691a1SStefan Agner 2297f2691a1SStefan Agner static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable) 2307f2691a1SStefan Agner { 2312f930643SLinus Walleij struct vf610_gpio_port *port = 23265389b49SLinus Walleij gpiochip_get_data(irq_data_get_irq_chip_data(d)); 2337f2691a1SStefan Agner 2347f2691a1SStefan Agner if (enable) 2357f2691a1SStefan Agner enable_irq_wake(port->irq); 2367f2691a1SStefan Agner else 2377f2691a1SStefan Agner disable_irq_wake(port->irq); 2387f2691a1SStefan Agner 2397f2691a1SStefan Agner return 0; 2407f2691a1SStefan Agner } 2417f2691a1SStefan Agner 242e6ef4f8eSAlexander Stein static const struct irq_chip vf610_irqchip = { 243e6ef4f8eSAlexander Stein .name = "gpio-vf610", 244e6ef4f8eSAlexander Stein .irq_ack = vf610_gpio_irq_ack, 245e6ef4f8eSAlexander Stein .irq_mask = vf610_gpio_irq_mask, 246e6ef4f8eSAlexander Stein .irq_unmask = vf610_gpio_irq_unmask, 247e6ef4f8eSAlexander Stein .irq_set_type = vf610_gpio_irq_set_type, 248e6ef4f8eSAlexander Stein .irq_set_wake = vf610_gpio_irq_set_wake, 249e6ef4f8eSAlexander Stein .flags = IRQCHIP_IMMUTABLE, 250e6ef4f8eSAlexander Stein GPIOCHIP_IRQ_RESOURCE_HELPERS, 251e6ef4f8eSAlexander Stein }; 252e6ef4f8eSAlexander Stein 253db9ed63cSAndrey Smirnov static void vf610_gpio_disable_clk(void *data) 254db9ed63cSAndrey Smirnov { 255db9ed63cSAndrey Smirnov clk_disable_unprepare(data); 256db9ed63cSAndrey Smirnov } 2577f2691a1SStefan Agner 2587f2691a1SStefan Agner static int vf610_gpio_probe(struct platform_device *pdev) 2597f2691a1SStefan Agner { 2607f2691a1SStefan Agner struct device *dev = &pdev->dev; 2617f2691a1SStefan Agner struct vf610_gpio_port *port; 2627f2691a1SStefan Agner struct gpio_chip *gc; 263e599256aSLinus Walleij struct gpio_irq_chip *girq; 2647ae710f9SAndrew Lunn int i; 2657f2691a1SStefan Agner int ret; 2667f2691a1SStefan Agner 2672e35bb6cSAndrey Smirnov port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); 2687f2691a1SStefan Agner if (!port) 2697f2691a1SStefan Agner return -ENOMEM; 2707f2691a1SStefan Agner 27123e577ebSThierry Reding port->sdata = of_device_get_match_data(dev); 272df53665bSEnrico Weigelt, metux IT consult port->base = devm_platform_ioremap_resource(pdev, 0); 2737f2691a1SStefan Agner if (IS_ERR(port->base)) 2747f2691a1SStefan Agner return PTR_ERR(port->base); 2757f2691a1SStefan Agner 276df53665bSEnrico Weigelt, metux IT consult port->gpio_base = devm_platform_ioremap_resource(pdev, 1); 2777f2691a1SStefan Agner if (IS_ERR(port->gpio_base)) 2787f2691a1SStefan Agner return PTR_ERR(port->gpio_base); 2797f2691a1SStefan Agner 2807f2691a1SStefan Agner port->irq = platform_get_irq(pdev, 0); 2817f2691a1SStefan Agner if (port->irq < 0) 2827f2691a1SStefan Agner return port->irq; 2837f2691a1SStefan Agner 2842e35bb6cSAndrey Smirnov port->clk_port = devm_clk_get(dev, "port"); 285663ba742SAndrey Smirnov ret = PTR_ERR_OR_ZERO(port->clk_port); 286663ba742SAndrey Smirnov if (!ret) { 28791393622SA.s. Dong ret = clk_prepare_enable(port->clk_port); 28891393622SA.s. Dong if (ret) 28991393622SA.s. Dong return ret; 290db9ed63cSAndrey Smirnov ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk, 291db9ed63cSAndrey Smirnov port->clk_port); 292db9ed63cSAndrey Smirnov if (ret) 293db9ed63cSAndrey Smirnov return ret; 294663ba742SAndrey Smirnov } else if (ret == -EPROBE_DEFER) { 29591393622SA.s. Dong /* 29691393622SA.s. Dong * Percolate deferrals, for anything else, 29791393622SA.s. Dong * just live without the clocking. 29891393622SA.s. Dong */ 299663ba742SAndrey Smirnov return ret; 30091393622SA.s. Dong } 30191393622SA.s. Dong 3022e35bb6cSAndrey Smirnov port->clk_gpio = devm_clk_get(dev, "gpio"); 303663ba742SAndrey Smirnov ret = PTR_ERR_OR_ZERO(port->clk_gpio); 304663ba742SAndrey Smirnov if (!ret) { 30591393622SA.s. Dong ret = clk_prepare_enable(port->clk_gpio); 306db9ed63cSAndrey Smirnov if (ret) 30791393622SA.s. Dong return ret; 308fc57949cSAndrey Smirnov ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk, 309fc57949cSAndrey Smirnov port->clk_gpio); 310fc57949cSAndrey Smirnov if (ret) 311fc57949cSAndrey Smirnov return ret; 312663ba742SAndrey Smirnov } else if (ret == -EPROBE_DEFER) { 313663ba742SAndrey Smirnov return ret; 31491393622SA.s. Dong } 31591393622SA.s. Dong 3167f2691a1SStefan Agner gc = &port->gc; 31758383c78SLinus Walleij gc->parent = dev; 3186f8ecb7fSHaibo Chen gc->label = dev_name(dev); 319d32efe37SAxel Lin gc->ngpio = VF610_GPIO_PER_PORT; 320*bb5ad5efSHaibo Chen gc->base = -1; 3217f2691a1SStefan Agner 322203f0daaSJonas Gorski gc->request = gpiochip_generic_request; 323203f0daaSJonas Gorski gc->free = gpiochip_generic_free; 324d32efe37SAxel Lin gc->direction_input = vf610_gpio_direction_input; 325d32efe37SAxel Lin gc->get = vf610_gpio_get; 326d32efe37SAxel Lin gc->direction_output = vf610_gpio_direction_output; 327d32efe37SAxel Lin gc->set = vf610_gpio_set; 3287f2691a1SStefan Agner 3297ae710f9SAndrew Lunn /* Mask all GPIO interrupts */ 3307ae710f9SAndrew Lunn for (i = 0; i < gc->ngpio; i++) 3317ae710f9SAndrew Lunn vf610_gpio_writel(0, port->base + PORT_PCR(i)); 3327ae710f9SAndrew Lunn 3337f2691a1SStefan Agner /* Clear the interrupt status register for all GPIO's */ 3347f2691a1SStefan Agner vf610_gpio_writel(~0, port->base + PORT_ISFR); 3357f2691a1SStefan Agner 336e599256aSLinus Walleij girq = &gc->irq; 337e6ef4f8eSAlexander Stein gpio_irq_chip_set_chip(girq, &vf610_irqchip); 338e599256aSLinus Walleij girq->parent_handler = vf610_gpio_irq_handler; 339e599256aSLinus Walleij girq->num_parents = 1; 340e599256aSLinus Walleij girq->parents = devm_kcalloc(&pdev->dev, 1, 341e599256aSLinus Walleij sizeof(*girq->parents), 342e599256aSLinus Walleij GFP_KERNEL); 343e599256aSLinus Walleij if (!girq->parents) 344e599256aSLinus Walleij return -ENOMEM; 345e599256aSLinus Walleij girq->parents[0] = port->irq; 346e599256aSLinus Walleij girq->default_type = IRQ_TYPE_NONE; 347e599256aSLinus Walleij girq->handler = handle_edge_irq; 3487f2691a1SStefan Agner 349e599256aSLinus Walleij return devm_gpiochip_add_data(dev, gc, port); 3507f2691a1SStefan Agner } 3517f2691a1SStefan Agner 3527f2691a1SStefan Agner static struct platform_driver vf610_gpio_driver = { 3537f2691a1SStefan Agner .driver = { 3547f2691a1SStefan Agner .name = "gpio-vf610", 3557f2691a1SStefan Agner .of_match_table = vf610_gpio_dt_ids, 3567f2691a1SStefan Agner }, 3577f2691a1SStefan Agner .probe = vf610_gpio_probe, 3587f2691a1SStefan Agner }; 3597f2691a1SStefan Agner 360df950da1SGeliang Tang builtin_platform_driver(vf610_gpio_driver); 361