136e2add1SLinus Walleij // SPDX-License-Identifier: GPL-2.0+ 27f2691a1SStefan Agner /* 3adaaf63eSPaul Gortmaker * Freescale vf610 GPIO support through PORT and GPIO 47f2691a1SStefan Agner * 57f2691a1SStefan Agner * Copyright (c) 2014 Toradex AG. 67f2691a1SStefan Agner * 77f2691a1SStefan Agner * Author: Stefan Agner <stefan@agner.ch>. 87f2691a1SStefan Agner */ 97f2691a1SStefan Agner #include <linux/bitops.h> 1091393622SA.s. Dong #include <linux/clk.h> 117f2691a1SStefan Agner #include <linux/err.h> 1245e8296cSLinus Walleij #include <linux/gpio/driver.h> 137f2691a1SStefan Agner #include <linux/init.h> 147f2691a1SStefan Agner #include <linux/interrupt.h> 157f2691a1SStefan Agner #include <linux/io.h> 167f2691a1SStefan Agner #include <linux/ioport.h> 177f2691a1SStefan Agner #include <linux/irq.h> 187f2691a1SStefan Agner #include <linux/platform_device.h> 197f2691a1SStefan Agner #include <linux/of.h> 207f2691a1SStefan Agner #include <linux/of_device.h> 217f2691a1SStefan Agner #include <linux/of_irq.h> 227f2691a1SStefan Agner 237f2691a1SStefan Agner #define VF610_GPIO_PER_PORT 32 247f2691a1SStefan Agner 25659d8a62SDong Aisheng struct fsl_gpio_soc_data { 26659d8a62SDong Aisheng /* SoCs has a Port Data Direction Register (PDDR) */ 27659d8a62SDong Aisheng bool have_paddr; 28659d8a62SDong Aisheng }; 29659d8a62SDong Aisheng 307f2691a1SStefan Agner struct vf610_gpio_port { 317f2691a1SStefan Agner struct gpio_chip gc; 327f2691a1SStefan Agner void __iomem *base; 337f2691a1SStefan Agner void __iomem *gpio_base; 34659d8a62SDong Aisheng const struct fsl_gpio_soc_data *sdata; 357f2691a1SStefan Agner u8 irqc[VF610_GPIO_PER_PORT]; 3691393622SA.s. Dong struct clk *clk_port; 3791393622SA.s. Dong struct clk *clk_gpio; 387f2691a1SStefan Agner int irq; 397f2691a1SStefan Agner }; 407f2691a1SStefan Agner 417f2691a1SStefan Agner #define GPIO_PDOR 0x00 427f2691a1SStefan Agner #define GPIO_PSOR 0x04 437f2691a1SStefan Agner #define GPIO_PCOR 0x08 447f2691a1SStefan Agner #define GPIO_PTOR 0x0c 457f2691a1SStefan Agner #define GPIO_PDIR 0x10 46659d8a62SDong Aisheng #define GPIO_PDDR 0x14 477f2691a1SStefan Agner 487f2691a1SStefan Agner #define PORT_PCR(n) ((n) * 0x4) 497f2691a1SStefan Agner #define PORT_PCR_IRQC_OFFSET 16 507f2691a1SStefan Agner 517f2691a1SStefan Agner #define PORT_ISFR 0xa0 527f2691a1SStefan Agner #define PORT_DFER 0xc0 537f2691a1SStefan Agner #define PORT_DFCR 0xc4 547f2691a1SStefan Agner #define PORT_DFWR 0xc8 557f2691a1SStefan Agner 567f2691a1SStefan Agner #define PORT_INT_OFF 0x0 577f2691a1SStefan Agner #define PORT_INT_LOGIC_ZERO 0x8 587f2691a1SStefan Agner #define PORT_INT_RISING_EDGE 0x9 597f2691a1SStefan Agner #define PORT_INT_FALLING_EDGE 0xa 607f2691a1SStefan Agner #define PORT_INT_EITHER_EDGE 0xb 617f2691a1SStefan Agner #define PORT_INT_LOGIC_ONE 0xc 627f2691a1SStefan Agner 63fd968115SStefan Agner static struct irq_chip vf610_gpio_irq_chip; 64fd968115SStefan Agner 65659d8a62SDong Aisheng static const struct fsl_gpio_soc_data imx_data = { 66659d8a62SDong Aisheng .have_paddr = true, 67659d8a62SDong Aisheng }; 68659d8a62SDong Aisheng 697f2691a1SStefan Agner static const struct of_device_id vf610_gpio_dt_ids[] = { 70659d8a62SDong Aisheng { .compatible = "fsl,vf610-gpio", .data = NULL, }, 71659d8a62SDong Aisheng { .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, }, 727f2691a1SStefan Agner { /* sentinel */ } 737f2691a1SStefan Agner }; 747f2691a1SStefan Agner 757f2691a1SStefan Agner static inline void vf610_gpio_writel(u32 val, void __iomem *reg) 767f2691a1SStefan Agner { 777f2691a1SStefan Agner writel_relaxed(val, reg); 787f2691a1SStefan Agner } 797f2691a1SStefan Agner 807f2691a1SStefan Agner static inline u32 vf610_gpio_readl(void __iomem *reg) 817f2691a1SStefan Agner { 827f2691a1SStefan Agner return readl_relaxed(reg); 837f2691a1SStefan Agner } 847f2691a1SStefan Agner 857f2691a1SStefan Agner static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio) 867f2691a1SStefan Agner { 8765389b49SLinus Walleij struct vf610_gpio_port *port = gpiochip_get_data(gc); 88659d8a62SDong Aisheng unsigned long mask = BIT(gpio); 89659d8a62SDong Aisheng void __iomem *addr; 907f2691a1SStefan Agner 91659d8a62SDong Aisheng if (port->sdata && port->sdata->have_paddr) { 92659d8a62SDong Aisheng mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR); 93659d8a62SDong Aisheng addr = mask ? port->gpio_base + GPIO_PDOR : 94659d8a62SDong Aisheng port->gpio_base + GPIO_PDIR; 95659d8a62SDong Aisheng return !!(vf610_gpio_readl(addr) & BIT(gpio)); 96659d8a62SDong Aisheng } else { 97659d8a62SDong Aisheng return !!(vf610_gpio_readl(port->gpio_base + GPIO_PDIR) 98659d8a62SDong Aisheng & BIT(gpio)); 99659d8a62SDong Aisheng } 1007f2691a1SStefan Agner } 1017f2691a1SStefan Agner 1027f2691a1SStefan Agner static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 1037f2691a1SStefan Agner { 10465389b49SLinus Walleij struct vf610_gpio_port *port = gpiochip_get_data(gc); 1057f2691a1SStefan Agner unsigned long mask = BIT(gpio); 1067f2691a1SStefan Agner 1077f2691a1SStefan Agner if (val) 1087f2691a1SStefan Agner vf610_gpio_writel(mask, port->gpio_base + GPIO_PSOR); 1097f2691a1SStefan Agner else 1107f2691a1SStefan Agner vf610_gpio_writel(mask, port->gpio_base + GPIO_PCOR); 1117f2691a1SStefan Agner } 1127f2691a1SStefan Agner 1137f2691a1SStefan Agner static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) 1147f2691a1SStefan Agner { 115659d8a62SDong Aisheng struct vf610_gpio_port *port = gpiochip_get_data(chip); 116659d8a62SDong Aisheng unsigned long mask = BIT(gpio); 117659d8a62SDong Aisheng u32 val; 118659d8a62SDong Aisheng 119659d8a62SDong Aisheng if (port->sdata && port->sdata->have_paddr) { 120659d8a62SDong Aisheng val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR); 121659d8a62SDong Aisheng val &= ~mask; 122659d8a62SDong Aisheng vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR); 123659d8a62SDong Aisheng } 124659d8a62SDong Aisheng 1257f2691a1SStefan Agner return pinctrl_gpio_direction_input(chip->base + gpio); 1267f2691a1SStefan Agner } 1277f2691a1SStefan Agner 1287f2691a1SStefan Agner static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, 1297f2691a1SStefan Agner int value) 1307f2691a1SStefan Agner { 131659d8a62SDong Aisheng struct vf610_gpio_port *port = gpiochip_get_data(chip); 132659d8a62SDong Aisheng unsigned long mask = BIT(gpio); 133659d8a62SDong Aisheng 134659d8a62SDong Aisheng if (port->sdata && port->sdata->have_paddr) 135659d8a62SDong Aisheng vf610_gpio_writel(mask, port->gpio_base + GPIO_PDDR); 136659d8a62SDong Aisheng 1377f2691a1SStefan Agner vf610_gpio_set(chip, gpio, value); 1387f2691a1SStefan Agner 1397f2691a1SStefan Agner return pinctrl_gpio_direction_output(chip->base + gpio); 1407f2691a1SStefan Agner } 1417f2691a1SStefan Agner 142bd0b9ac4SThomas Gleixner static void vf610_gpio_irq_handler(struct irq_desc *desc) 1437f2691a1SStefan Agner { 1442f930643SLinus Walleij struct vf610_gpio_port *port = 14565389b49SLinus Walleij gpiochip_get_data(irq_desc_get_handler_data(desc)); 1467f2691a1SStefan Agner struct irq_chip *chip = irq_desc_get_chip(desc); 1477f2691a1SStefan Agner int pin; 1487f2691a1SStefan Agner unsigned long irq_isfr; 1497f2691a1SStefan Agner 1507f2691a1SStefan Agner chained_irq_enter(chip, desc); 1517f2691a1SStefan Agner 1527f2691a1SStefan Agner irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR); 1537f2691a1SStefan Agner 1547f2691a1SStefan Agner for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) { 1557f2691a1SStefan Agner vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR); 1567f2691a1SStefan Agner 157f0fbe7bcSThierry Reding generic_handle_irq(irq_find_mapping(port->gc.irq.domain, pin)); 1587f2691a1SStefan Agner } 1597f2691a1SStefan Agner 1607f2691a1SStefan Agner chained_irq_exit(chip, desc); 1617f2691a1SStefan Agner } 1627f2691a1SStefan Agner 1637f2691a1SStefan Agner static void vf610_gpio_irq_ack(struct irq_data *d) 1647f2691a1SStefan Agner { 1652f930643SLinus Walleij struct vf610_gpio_port *port = 16665389b49SLinus Walleij gpiochip_get_data(irq_data_get_irq_chip_data(d)); 1677f2691a1SStefan Agner int gpio = d->hwirq; 1687f2691a1SStefan Agner 1697f2691a1SStefan Agner vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR); 1707f2691a1SStefan Agner } 1717f2691a1SStefan Agner 1727f2691a1SStefan Agner static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type) 1737f2691a1SStefan Agner { 1742f930643SLinus Walleij struct vf610_gpio_port *port = 17565389b49SLinus Walleij gpiochip_get_data(irq_data_get_irq_chip_data(d)); 1767f2691a1SStefan Agner u8 irqc; 1777f2691a1SStefan Agner 1787f2691a1SStefan Agner switch (type) { 1797f2691a1SStefan Agner case IRQ_TYPE_EDGE_RISING: 1807f2691a1SStefan Agner irqc = PORT_INT_RISING_EDGE; 1817f2691a1SStefan Agner break; 1827f2691a1SStefan Agner case IRQ_TYPE_EDGE_FALLING: 1837f2691a1SStefan Agner irqc = PORT_INT_FALLING_EDGE; 1847f2691a1SStefan Agner break; 1857f2691a1SStefan Agner case IRQ_TYPE_EDGE_BOTH: 1867f2691a1SStefan Agner irqc = PORT_INT_EITHER_EDGE; 1877f2691a1SStefan Agner break; 1887f2691a1SStefan Agner case IRQ_TYPE_LEVEL_LOW: 1897f2691a1SStefan Agner irqc = PORT_INT_LOGIC_ZERO; 1907f2691a1SStefan Agner break; 1917f2691a1SStefan Agner case IRQ_TYPE_LEVEL_HIGH: 1927f2691a1SStefan Agner irqc = PORT_INT_LOGIC_ONE; 1937f2691a1SStefan Agner break; 1947f2691a1SStefan Agner default: 1957f2691a1SStefan Agner return -EINVAL; 1967f2691a1SStefan Agner } 1977f2691a1SStefan Agner 1987f2691a1SStefan Agner port->irqc[d->hwirq] = irqc; 1997f2691a1SStefan Agner 200fd968115SStefan Agner if (type & IRQ_TYPE_LEVEL_MASK) 201a7147db0SThomas Gleixner irq_set_handler_locked(d, handle_level_irq); 202fd968115SStefan Agner else 203a7147db0SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 204fd968115SStefan Agner 2057f2691a1SStefan Agner return 0; 2067f2691a1SStefan Agner } 2077f2691a1SStefan Agner 2087f2691a1SStefan Agner static void vf610_gpio_irq_mask(struct irq_data *d) 2097f2691a1SStefan Agner { 2102f930643SLinus Walleij struct vf610_gpio_port *port = 21165389b49SLinus Walleij gpiochip_get_data(irq_data_get_irq_chip_data(d)); 2127f2691a1SStefan Agner void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq); 2137f2691a1SStefan Agner 2147f2691a1SStefan Agner vf610_gpio_writel(0, pcr_base); 2157f2691a1SStefan Agner } 2167f2691a1SStefan Agner 2177f2691a1SStefan Agner static void vf610_gpio_irq_unmask(struct irq_data *d) 2187f2691a1SStefan Agner { 2192f930643SLinus Walleij struct vf610_gpio_port *port = 22065389b49SLinus Walleij gpiochip_get_data(irq_data_get_irq_chip_data(d)); 2217f2691a1SStefan Agner void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq); 2227f2691a1SStefan Agner 2237f2691a1SStefan Agner vf610_gpio_writel(port->irqc[d->hwirq] << PORT_PCR_IRQC_OFFSET, 2247f2691a1SStefan Agner pcr_base); 2257f2691a1SStefan Agner } 2267f2691a1SStefan Agner 2277f2691a1SStefan Agner static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable) 2287f2691a1SStefan Agner { 2292f930643SLinus Walleij struct vf610_gpio_port *port = 23065389b49SLinus Walleij gpiochip_get_data(irq_data_get_irq_chip_data(d)); 2317f2691a1SStefan Agner 2327f2691a1SStefan Agner if (enable) 2337f2691a1SStefan Agner enable_irq_wake(port->irq); 2347f2691a1SStefan Agner else 2357f2691a1SStefan Agner disable_irq_wake(port->irq); 2367f2691a1SStefan Agner 2377f2691a1SStefan Agner return 0; 2387f2691a1SStefan Agner } 2397f2691a1SStefan Agner 2407f2691a1SStefan Agner static struct irq_chip vf610_gpio_irq_chip = { 2417f2691a1SStefan Agner .name = "gpio-vf610", 2427f2691a1SStefan Agner .irq_ack = vf610_gpio_irq_ack, 2437f2691a1SStefan Agner .irq_mask = vf610_gpio_irq_mask, 2447f2691a1SStefan Agner .irq_unmask = vf610_gpio_irq_unmask, 2457f2691a1SStefan Agner .irq_set_type = vf610_gpio_irq_set_type, 2467f2691a1SStefan Agner .irq_set_wake = vf610_gpio_irq_set_wake, 2477f2691a1SStefan Agner }; 2487f2691a1SStefan Agner 2497f2691a1SStefan Agner static int vf610_gpio_probe(struct platform_device *pdev) 2507f2691a1SStefan Agner { 2517f2691a1SStefan Agner struct device *dev = &pdev->dev; 2527f2691a1SStefan Agner struct device_node *np = dev->of_node; 2537f2691a1SStefan Agner struct vf610_gpio_port *port; 2547f2691a1SStefan Agner struct resource *iores; 2557f2691a1SStefan Agner struct gpio_chip *gc; 2567ae710f9SAndrew Lunn int i; 2577f2691a1SStefan Agner int ret; 2587f2691a1SStefan Agner 2597f2691a1SStefan Agner port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); 2607f2691a1SStefan Agner if (!port) 2617f2691a1SStefan Agner return -ENOMEM; 2627f2691a1SStefan Agner 26323e577ebSThierry Reding port->sdata = of_device_get_match_data(dev); 2647f2691a1SStefan Agner iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2657f2691a1SStefan Agner port->base = devm_ioremap_resource(dev, iores); 2667f2691a1SStefan Agner if (IS_ERR(port->base)) 2677f2691a1SStefan Agner return PTR_ERR(port->base); 2687f2691a1SStefan Agner 2697f2691a1SStefan Agner iores = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2707f2691a1SStefan Agner port->gpio_base = devm_ioremap_resource(dev, iores); 2717f2691a1SStefan Agner if (IS_ERR(port->gpio_base)) 2727f2691a1SStefan Agner return PTR_ERR(port->gpio_base); 2737f2691a1SStefan Agner 2747f2691a1SStefan Agner port->irq = platform_get_irq(pdev, 0); 2757f2691a1SStefan Agner if (port->irq < 0) 2767f2691a1SStefan Agner return port->irq; 2777f2691a1SStefan Agner 27891393622SA.s. Dong port->clk_port = devm_clk_get(&pdev->dev, "port"); 27991393622SA.s. Dong if (!IS_ERR(port->clk_port)) { 28091393622SA.s. Dong ret = clk_prepare_enable(port->clk_port); 28191393622SA.s. Dong if (ret) 28291393622SA.s. Dong return ret; 28391393622SA.s. Dong } else if (port->clk_port == ERR_PTR(-EPROBE_DEFER)) { 28491393622SA.s. Dong /* 28591393622SA.s. Dong * Percolate deferrals, for anything else, 28691393622SA.s. Dong * just live without the clocking. 28791393622SA.s. Dong */ 28891393622SA.s. Dong return PTR_ERR(port->clk_port); 28991393622SA.s. Dong } 29091393622SA.s. Dong 29191393622SA.s. Dong port->clk_gpio = devm_clk_get(&pdev->dev, "gpio"); 29291393622SA.s. Dong if (!IS_ERR(port->clk_gpio)) { 29391393622SA.s. Dong ret = clk_prepare_enable(port->clk_gpio); 29491393622SA.s. Dong if (ret) { 29591393622SA.s. Dong clk_disable_unprepare(port->clk_port); 29691393622SA.s. Dong return ret; 29791393622SA.s. Dong } 29891393622SA.s. Dong } else if (port->clk_gpio == ERR_PTR(-EPROBE_DEFER)) { 29991393622SA.s. Dong clk_disable_unprepare(port->clk_port); 30091393622SA.s. Dong return PTR_ERR(port->clk_gpio); 30191393622SA.s. Dong } 30291393622SA.s. Dong 30391393622SA.s. Dong platform_set_drvdata(pdev, port); 30491393622SA.s. Dong 3057f2691a1SStefan Agner gc = &port->gc; 3067f2691a1SStefan Agner gc->of_node = np; 30758383c78SLinus Walleij gc->parent = dev; 308d32efe37SAxel Lin gc->label = "vf610-gpio"; 309d32efe37SAxel Lin gc->ngpio = VF610_GPIO_PER_PORT; 3107f2691a1SStefan Agner gc->base = of_alias_get_id(np, "gpio") * VF610_GPIO_PER_PORT; 3117f2691a1SStefan Agner 312203f0daaSJonas Gorski gc->request = gpiochip_generic_request; 313203f0daaSJonas Gorski gc->free = gpiochip_generic_free; 314d32efe37SAxel Lin gc->direction_input = vf610_gpio_direction_input; 315d32efe37SAxel Lin gc->get = vf610_gpio_get; 316d32efe37SAxel Lin gc->direction_output = vf610_gpio_direction_output; 317d32efe37SAxel Lin gc->set = vf610_gpio_set; 3187f2691a1SStefan Agner 31965389b49SLinus Walleij ret = gpiochip_add_data(gc, port); 3207f2691a1SStefan Agner if (ret < 0) 3217f2691a1SStefan Agner return ret; 3227f2691a1SStefan Agner 3237ae710f9SAndrew Lunn /* Mask all GPIO interrupts */ 3247ae710f9SAndrew Lunn for (i = 0; i < gc->ngpio; i++) 3257ae710f9SAndrew Lunn vf610_gpio_writel(0, port->base + PORT_PCR(i)); 3267ae710f9SAndrew Lunn 3277f2691a1SStefan Agner /* Clear the interrupt status register for all GPIO's */ 3287f2691a1SStefan Agner vf610_gpio_writel(~0, port->base + PORT_ISFR); 3297f2691a1SStefan Agner 3307f2691a1SStefan Agner ret = gpiochip_irqchip_add(gc, &vf610_gpio_irq_chip, 0, 331fd968115SStefan Agner handle_edge_irq, IRQ_TYPE_NONE); 3327f2691a1SStefan Agner if (ret) { 3337f2691a1SStefan Agner dev_err(dev, "failed to add irqchip\n"); 3347f2691a1SStefan Agner gpiochip_remove(gc); 3357f2691a1SStefan Agner return ret; 3367f2691a1SStefan Agner } 3377f2691a1SStefan Agner gpiochip_set_chained_irqchip(gc, &vf610_gpio_irq_chip, port->irq, 3387f2691a1SStefan Agner vf610_gpio_irq_handler); 3397f2691a1SStefan Agner 3407f2691a1SStefan Agner return 0; 3417f2691a1SStefan Agner } 3427f2691a1SStefan Agner 34391393622SA.s. Dong static int vf610_gpio_remove(struct platform_device *pdev) 34491393622SA.s. Dong { 34591393622SA.s. Dong struct vf610_gpio_port *port = platform_get_drvdata(pdev); 34691393622SA.s. Dong 34791393622SA.s. Dong gpiochip_remove(&port->gc); 34891393622SA.s. Dong if (!IS_ERR(port->clk_port)) 34991393622SA.s. Dong clk_disable_unprepare(port->clk_port); 35091393622SA.s. Dong if (!IS_ERR(port->clk_gpio)) 35191393622SA.s. Dong clk_disable_unprepare(port->clk_gpio); 35291393622SA.s. Dong 35391393622SA.s. Dong return 0; 35491393622SA.s. Dong } 35591393622SA.s. Dong 3567f2691a1SStefan Agner static struct platform_driver vf610_gpio_driver = { 3577f2691a1SStefan Agner .driver = { 3587f2691a1SStefan Agner .name = "gpio-vf610", 3597f2691a1SStefan Agner .of_match_table = vf610_gpio_dt_ids, 3607f2691a1SStefan Agner }, 3617f2691a1SStefan Agner .probe = vf610_gpio_probe, 36291393622SA.s. Dong .remove = vf610_gpio_remove, 3637f2691a1SStefan Agner }; 3647f2691a1SStefan Agner 365df950da1SGeliang Tang builtin_platform_driver(vf610_gpio_driver); 366