xref: /openbmc/linux/drivers/gpio/gpio-vf610.c (revision 45e8296c)
17f2691a1SStefan Agner /*
2adaaf63eSPaul Gortmaker  * Freescale vf610 GPIO support through PORT and GPIO
37f2691a1SStefan Agner  *
47f2691a1SStefan Agner  * Copyright (c) 2014 Toradex AG.
57f2691a1SStefan Agner  *
67f2691a1SStefan Agner  * Author: Stefan Agner <stefan@agner.ch>.
77f2691a1SStefan Agner  *
87f2691a1SStefan Agner  * This program is free software; you can redistribute it and/or
97f2691a1SStefan Agner  * modify it under the terms of the GNU General Public License
107f2691a1SStefan Agner  * as published by the Free Software Foundation; either version 2
117f2691a1SStefan Agner  * of the License, or (at your option) any later version.
127f2691a1SStefan Agner  * This program is distributed in the hope that it will be useful,
137f2691a1SStefan Agner  * but WITHOUT ANY WARRANTY; without even the implied warranty of
147f2691a1SStefan Agner  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
157f2691a1SStefan Agner  * GNU General Public License for more details.
167f2691a1SStefan Agner  */
177f2691a1SStefan Agner 
187f2691a1SStefan Agner #include <linux/bitops.h>
197f2691a1SStefan Agner #include <linux/err.h>
2045e8296cSLinus Walleij #include <linux/gpio/driver.h>
217f2691a1SStefan Agner #include <linux/init.h>
227f2691a1SStefan Agner #include <linux/interrupt.h>
237f2691a1SStefan Agner #include <linux/io.h>
247f2691a1SStefan Agner #include <linux/ioport.h>
257f2691a1SStefan Agner #include <linux/irq.h>
267f2691a1SStefan Agner #include <linux/platform_device.h>
277f2691a1SStefan Agner #include <linux/of.h>
287f2691a1SStefan Agner #include <linux/of_device.h>
297f2691a1SStefan Agner #include <linux/of_irq.h>
307f2691a1SStefan Agner 
317f2691a1SStefan Agner #define VF610_GPIO_PER_PORT		32
327f2691a1SStefan Agner 
33659d8a62SDong Aisheng struct fsl_gpio_soc_data {
34659d8a62SDong Aisheng 	/* SoCs has a Port Data Direction Register (PDDR) */
35659d8a62SDong Aisheng 	bool have_paddr;
36659d8a62SDong Aisheng };
37659d8a62SDong Aisheng 
387f2691a1SStefan Agner struct vf610_gpio_port {
397f2691a1SStefan Agner 	struct gpio_chip gc;
407f2691a1SStefan Agner 	void __iomem *base;
417f2691a1SStefan Agner 	void __iomem *gpio_base;
42659d8a62SDong Aisheng 	const struct fsl_gpio_soc_data *sdata;
437f2691a1SStefan Agner 	u8 irqc[VF610_GPIO_PER_PORT];
447f2691a1SStefan Agner 	int irq;
457f2691a1SStefan Agner };
467f2691a1SStefan Agner 
477f2691a1SStefan Agner #define GPIO_PDOR		0x00
487f2691a1SStefan Agner #define GPIO_PSOR		0x04
497f2691a1SStefan Agner #define GPIO_PCOR		0x08
507f2691a1SStefan Agner #define GPIO_PTOR		0x0c
517f2691a1SStefan Agner #define GPIO_PDIR		0x10
52659d8a62SDong Aisheng #define GPIO_PDDR		0x14
537f2691a1SStefan Agner 
547f2691a1SStefan Agner #define PORT_PCR(n)		((n) * 0x4)
557f2691a1SStefan Agner #define PORT_PCR_IRQC_OFFSET	16
567f2691a1SStefan Agner 
577f2691a1SStefan Agner #define PORT_ISFR		0xa0
587f2691a1SStefan Agner #define PORT_DFER		0xc0
597f2691a1SStefan Agner #define PORT_DFCR		0xc4
607f2691a1SStefan Agner #define PORT_DFWR		0xc8
617f2691a1SStefan Agner 
627f2691a1SStefan Agner #define PORT_INT_OFF		0x0
637f2691a1SStefan Agner #define PORT_INT_LOGIC_ZERO	0x8
647f2691a1SStefan Agner #define PORT_INT_RISING_EDGE	0x9
657f2691a1SStefan Agner #define PORT_INT_FALLING_EDGE	0xa
667f2691a1SStefan Agner #define PORT_INT_EITHER_EDGE	0xb
677f2691a1SStefan Agner #define PORT_INT_LOGIC_ONE	0xc
687f2691a1SStefan Agner 
69fd968115SStefan Agner static struct irq_chip vf610_gpio_irq_chip;
70fd968115SStefan Agner 
71659d8a62SDong Aisheng static const struct fsl_gpio_soc_data imx_data = {
72659d8a62SDong Aisheng 	.have_paddr = true,
73659d8a62SDong Aisheng };
74659d8a62SDong Aisheng 
757f2691a1SStefan Agner static const struct of_device_id vf610_gpio_dt_ids[] = {
76659d8a62SDong Aisheng 	{ .compatible = "fsl,vf610-gpio",	.data = NULL, },
77659d8a62SDong Aisheng 	{ .compatible = "fsl,imx7ulp-gpio",	.data = &imx_data, },
787f2691a1SStefan Agner 	{ /* sentinel */ }
797f2691a1SStefan Agner };
807f2691a1SStefan Agner 
817f2691a1SStefan Agner static inline void vf610_gpio_writel(u32 val, void __iomem *reg)
827f2691a1SStefan Agner {
837f2691a1SStefan Agner 	writel_relaxed(val, reg);
847f2691a1SStefan Agner }
857f2691a1SStefan Agner 
867f2691a1SStefan Agner static inline u32 vf610_gpio_readl(void __iomem *reg)
877f2691a1SStefan Agner {
887f2691a1SStefan Agner 	return readl_relaxed(reg);
897f2691a1SStefan Agner }
907f2691a1SStefan Agner 
917f2691a1SStefan Agner static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio)
927f2691a1SStefan Agner {
9365389b49SLinus Walleij 	struct vf610_gpio_port *port = gpiochip_get_data(gc);
94659d8a62SDong Aisheng 	unsigned long mask = BIT(gpio);
95659d8a62SDong Aisheng 	void __iomem *addr;
967f2691a1SStefan Agner 
97659d8a62SDong Aisheng 	if (port->sdata && port->sdata->have_paddr) {
98659d8a62SDong Aisheng 		mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
99659d8a62SDong Aisheng 		addr = mask ? port->gpio_base + GPIO_PDOR :
100659d8a62SDong Aisheng 			      port->gpio_base + GPIO_PDIR;
101659d8a62SDong Aisheng 		return !!(vf610_gpio_readl(addr) & BIT(gpio));
102659d8a62SDong Aisheng 	} else {
103659d8a62SDong Aisheng 		return !!(vf610_gpio_readl(port->gpio_base + GPIO_PDIR)
104659d8a62SDong Aisheng 					   & BIT(gpio));
105659d8a62SDong Aisheng 	}
1067f2691a1SStefan Agner }
1077f2691a1SStefan Agner 
1087f2691a1SStefan Agner static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
1097f2691a1SStefan Agner {
11065389b49SLinus Walleij 	struct vf610_gpio_port *port = gpiochip_get_data(gc);
1117f2691a1SStefan Agner 	unsigned long mask = BIT(gpio);
1127f2691a1SStefan Agner 
1137f2691a1SStefan Agner 	if (val)
1147f2691a1SStefan Agner 		vf610_gpio_writel(mask, port->gpio_base + GPIO_PSOR);
1157f2691a1SStefan Agner 	else
1167f2691a1SStefan Agner 		vf610_gpio_writel(mask, port->gpio_base + GPIO_PCOR);
1177f2691a1SStefan Agner }
1187f2691a1SStefan Agner 
1197f2691a1SStefan Agner static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1207f2691a1SStefan Agner {
121659d8a62SDong Aisheng 	struct vf610_gpio_port *port = gpiochip_get_data(chip);
122659d8a62SDong Aisheng 	unsigned long mask = BIT(gpio);
123659d8a62SDong Aisheng 	u32 val;
124659d8a62SDong Aisheng 
125659d8a62SDong Aisheng 	if (port->sdata && port->sdata->have_paddr) {
126659d8a62SDong Aisheng 		val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
127659d8a62SDong Aisheng 		val &= ~mask;
128659d8a62SDong Aisheng 		vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
129659d8a62SDong Aisheng 	}
130659d8a62SDong Aisheng 
1317f2691a1SStefan Agner 	return pinctrl_gpio_direction_input(chip->base + gpio);
1327f2691a1SStefan Agner }
1337f2691a1SStefan Agner 
1347f2691a1SStefan Agner static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
1357f2691a1SStefan Agner 				       int value)
1367f2691a1SStefan Agner {
137659d8a62SDong Aisheng 	struct vf610_gpio_port *port = gpiochip_get_data(chip);
138659d8a62SDong Aisheng 	unsigned long mask = BIT(gpio);
139659d8a62SDong Aisheng 
140659d8a62SDong Aisheng 	if (port->sdata && port->sdata->have_paddr)
141659d8a62SDong Aisheng 		vf610_gpio_writel(mask, port->gpio_base + GPIO_PDDR);
142659d8a62SDong Aisheng 
1437f2691a1SStefan Agner 	vf610_gpio_set(chip, gpio, value);
1447f2691a1SStefan Agner 
1457f2691a1SStefan Agner 	return pinctrl_gpio_direction_output(chip->base + gpio);
1467f2691a1SStefan Agner }
1477f2691a1SStefan Agner 
148bd0b9ac4SThomas Gleixner static void vf610_gpio_irq_handler(struct irq_desc *desc)
1497f2691a1SStefan Agner {
1502f930643SLinus Walleij 	struct vf610_gpio_port *port =
15165389b49SLinus Walleij 		gpiochip_get_data(irq_desc_get_handler_data(desc));
1527f2691a1SStefan Agner 	struct irq_chip *chip = irq_desc_get_chip(desc);
1537f2691a1SStefan Agner 	int pin;
1547f2691a1SStefan Agner 	unsigned long irq_isfr;
1557f2691a1SStefan Agner 
1567f2691a1SStefan Agner 	chained_irq_enter(chip, desc);
1577f2691a1SStefan Agner 
1587f2691a1SStefan Agner 	irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR);
1597f2691a1SStefan Agner 
1607f2691a1SStefan Agner 	for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
1617f2691a1SStefan Agner 		vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);
1627f2691a1SStefan Agner 
163f0fbe7bcSThierry Reding 		generic_handle_irq(irq_find_mapping(port->gc.irq.domain, pin));
1647f2691a1SStefan Agner 	}
1657f2691a1SStefan Agner 
1667f2691a1SStefan Agner 	chained_irq_exit(chip, desc);
1677f2691a1SStefan Agner }
1687f2691a1SStefan Agner 
1697f2691a1SStefan Agner static void vf610_gpio_irq_ack(struct irq_data *d)
1707f2691a1SStefan Agner {
1712f930643SLinus Walleij 	struct vf610_gpio_port *port =
17265389b49SLinus Walleij 		gpiochip_get_data(irq_data_get_irq_chip_data(d));
1737f2691a1SStefan Agner 	int gpio = d->hwirq;
1747f2691a1SStefan Agner 
1757f2691a1SStefan Agner 	vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR);
1767f2691a1SStefan Agner }
1777f2691a1SStefan Agner 
1787f2691a1SStefan Agner static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type)
1797f2691a1SStefan Agner {
1802f930643SLinus Walleij 	struct vf610_gpio_port *port =
18165389b49SLinus Walleij 		gpiochip_get_data(irq_data_get_irq_chip_data(d));
1827f2691a1SStefan Agner 	u8 irqc;
1837f2691a1SStefan Agner 
1847f2691a1SStefan Agner 	switch (type) {
1857f2691a1SStefan Agner 	case IRQ_TYPE_EDGE_RISING:
1867f2691a1SStefan Agner 		irqc = PORT_INT_RISING_EDGE;
1877f2691a1SStefan Agner 		break;
1887f2691a1SStefan Agner 	case IRQ_TYPE_EDGE_FALLING:
1897f2691a1SStefan Agner 		irqc = PORT_INT_FALLING_EDGE;
1907f2691a1SStefan Agner 		break;
1917f2691a1SStefan Agner 	case IRQ_TYPE_EDGE_BOTH:
1927f2691a1SStefan Agner 		irqc = PORT_INT_EITHER_EDGE;
1937f2691a1SStefan Agner 		break;
1947f2691a1SStefan Agner 	case IRQ_TYPE_LEVEL_LOW:
1957f2691a1SStefan Agner 		irqc = PORT_INT_LOGIC_ZERO;
1967f2691a1SStefan Agner 		break;
1977f2691a1SStefan Agner 	case IRQ_TYPE_LEVEL_HIGH:
1987f2691a1SStefan Agner 		irqc = PORT_INT_LOGIC_ONE;
1997f2691a1SStefan Agner 		break;
2007f2691a1SStefan Agner 	default:
2017f2691a1SStefan Agner 		return -EINVAL;
2027f2691a1SStefan Agner 	}
2037f2691a1SStefan Agner 
2047f2691a1SStefan Agner 	port->irqc[d->hwirq] = irqc;
2057f2691a1SStefan Agner 
206fd968115SStefan Agner 	if (type & IRQ_TYPE_LEVEL_MASK)
207a7147db0SThomas Gleixner 		irq_set_handler_locked(d, handle_level_irq);
208fd968115SStefan Agner 	else
209a7147db0SThomas Gleixner 		irq_set_handler_locked(d, handle_edge_irq);
210fd968115SStefan Agner 
2117f2691a1SStefan Agner 	return 0;
2127f2691a1SStefan Agner }
2137f2691a1SStefan Agner 
2147f2691a1SStefan Agner static void vf610_gpio_irq_mask(struct irq_data *d)
2157f2691a1SStefan Agner {
2162f930643SLinus Walleij 	struct vf610_gpio_port *port =
21765389b49SLinus Walleij 		gpiochip_get_data(irq_data_get_irq_chip_data(d));
2187f2691a1SStefan Agner 	void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq);
2197f2691a1SStefan Agner 
2207f2691a1SStefan Agner 	vf610_gpio_writel(0, pcr_base);
2217f2691a1SStefan Agner }
2227f2691a1SStefan Agner 
2237f2691a1SStefan Agner static void vf610_gpio_irq_unmask(struct irq_data *d)
2247f2691a1SStefan Agner {
2252f930643SLinus Walleij 	struct vf610_gpio_port *port =
22665389b49SLinus Walleij 		gpiochip_get_data(irq_data_get_irq_chip_data(d));
2277f2691a1SStefan Agner 	void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq);
2287f2691a1SStefan Agner 
2297f2691a1SStefan Agner 	vf610_gpio_writel(port->irqc[d->hwirq] << PORT_PCR_IRQC_OFFSET,
2307f2691a1SStefan Agner 			  pcr_base);
2317f2691a1SStefan Agner }
2327f2691a1SStefan Agner 
2337f2691a1SStefan Agner static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable)
2347f2691a1SStefan Agner {
2352f930643SLinus Walleij 	struct vf610_gpio_port *port =
23665389b49SLinus Walleij 		gpiochip_get_data(irq_data_get_irq_chip_data(d));
2377f2691a1SStefan Agner 
2387f2691a1SStefan Agner 	if (enable)
2397f2691a1SStefan Agner 		enable_irq_wake(port->irq);
2407f2691a1SStefan Agner 	else
2417f2691a1SStefan Agner 		disable_irq_wake(port->irq);
2427f2691a1SStefan Agner 
2437f2691a1SStefan Agner 	return 0;
2447f2691a1SStefan Agner }
2457f2691a1SStefan Agner 
2467f2691a1SStefan Agner static struct irq_chip vf610_gpio_irq_chip = {
2477f2691a1SStefan Agner 	.name		= "gpio-vf610",
2487f2691a1SStefan Agner 	.irq_ack	= vf610_gpio_irq_ack,
2497f2691a1SStefan Agner 	.irq_mask	= vf610_gpio_irq_mask,
2507f2691a1SStefan Agner 	.irq_unmask	= vf610_gpio_irq_unmask,
2517f2691a1SStefan Agner 	.irq_set_type	= vf610_gpio_irq_set_type,
2527f2691a1SStefan Agner 	.irq_set_wake	= vf610_gpio_irq_set_wake,
2537f2691a1SStefan Agner };
2547f2691a1SStefan Agner 
2557f2691a1SStefan Agner static int vf610_gpio_probe(struct platform_device *pdev)
2567f2691a1SStefan Agner {
2577f2691a1SStefan Agner 	struct device *dev = &pdev->dev;
2587f2691a1SStefan Agner 	struct device_node *np = dev->of_node;
2597f2691a1SStefan Agner 	struct vf610_gpio_port *port;
2607f2691a1SStefan Agner 	struct resource *iores;
2617f2691a1SStefan Agner 	struct gpio_chip *gc;
2627f2691a1SStefan Agner 	int ret;
2637f2691a1SStefan Agner 
2647f2691a1SStefan Agner 	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
2657f2691a1SStefan Agner 	if (!port)
2667f2691a1SStefan Agner 		return -ENOMEM;
2677f2691a1SStefan Agner 
26823e577ebSThierry Reding 	port->sdata = of_device_get_match_data(dev);
2697f2691a1SStefan Agner 	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2707f2691a1SStefan Agner 	port->base = devm_ioremap_resource(dev, iores);
2717f2691a1SStefan Agner 	if (IS_ERR(port->base))
2727f2691a1SStefan Agner 		return PTR_ERR(port->base);
2737f2691a1SStefan Agner 
2747f2691a1SStefan Agner 	iores = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2757f2691a1SStefan Agner 	port->gpio_base = devm_ioremap_resource(dev, iores);
2767f2691a1SStefan Agner 	if (IS_ERR(port->gpio_base))
2777f2691a1SStefan Agner 		return PTR_ERR(port->gpio_base);
2787f2691a1SStefan Agner 
2797f2691a1SStefan Agner 	port->irq = platform_get_irq(pdev, 0);
2807f2691a1SStefan Agner 	if (port->irq < 0)
2817f2691a1SStefan Agner 		return port->irq;
2827f2691a1SStefan Agner 
2837f2691a1SStefan Agner 	gc = &port->gc;
2847f2691a1SStefan Agner 	gc->of_node = np;
28558383c78SLinus Walleij 	gc->parent = dev;
286d32efe37SAxel Lin 	gc->label = "vf610-gpio";
287d32efe37SAxel Lin 	gc->ngpio = VF610_GPIO_PER_PORT;
2887f2691a1SStefan Agner 	gc->base = of_alias_get_id(np, "gpio") * VF610_GPIO_PER_PORT;
2897f2691a1SStefan Agner 
290203f0daaSJonas Gorski 	gc->request = gpiochip_generic_request;
291203f0daaSJonas Gorski 	gc->free = gpiochip_generic_free;
292d32efe37SAxel Lin 	gc->direction_input = vf610_gpio_direction_input;
293d32efe37SAxel Lin 	gc->get = vf610_gpio_get;
294d32efe37SAxel Lin 	gc->direction_output = vf610_gpio_direction_output;
295d32efe37SAxel Lin 	gc->set = vf610_gpio_set;
2967f2691a1SStefan Agner 
29765389b49SLinus Walleij 	ret = gpiochip_add_data(gc, port);
2987f2691a1SStefan Agner 	if (ret < 0)
2997f2691a1SStefan Agner 		return ret;
3007f2691a1SStefan Agner 
3017f2691a1SStefan Agner 	/* Clear the interrupt status register for all GPIO's */
3027f2691a1SStefan Agner 	vf610_gpio_writel(~0, port->base + PORT_ISFR);
3037f2691a1SStefan Agner 
3047f2691a1SStefan Agner 	ret = gpiochip_irqchip_add(gc, &vf610_gpio_irq_chip, 0,
305fd968115SStefan Agner 				   handle_edge_irq, IRQ_TYPE_NONE);
3067f2691a1SStefan Agner 	if (ret) {
3077f2691a1SStefan Agner 		dev_err(dev, "failed to add irqchip\n");
3087f2691a1SStefan Agner 		gpiochip_remove(gc);
3097f2691a1SStefan Agner 		return ret;
3107f2691a1SStefan Agner 	}
3117f2691a1SStefan Agner 	gpiochip_set_chained_irqchip(gc, &vf610_gpio_irq_chip, port->irq,
3127f2691a1SStefan Agner 				     vf610_gpio_irq_handler);
3137f2691a1SStefan Agner 
3147f2691a1SStefan Agner 	return 0;
3157f2691a1SStefan Agner }
3167f2691a1SStefan Agner 
3177f2691a1SStefan Agner static struct platform_driver vf610_gpio_driver = {
3187f2691a1SStefan Agner 	.driver		= {
3197f2691a1SStefan Agner 		.name	= "gpio-vf610",
3207f2691a1SStefan Agner 		.of_match_table = vf610_gpio_dt_ids,
3217f2691a1SStefan Agner 	},
3227f2691a1SStefan Agner 	.probe		= vf610_gpio_probe,
3237f2691a1SStefan Agner };
3247f2691a1SStefan Agner 
325df950da1SGeliang Tang builtin_platform_driver(vf610_gpio_driver);
326