1 /* 2 * Copyright (C) 2017 Socionext Inc. 3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/bitops.h> 16 #include <linux/gpio/driver.h> 17 #include <linux/irq.h> 18 #include <linux/irqdomain.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/of_irq.h> 23 #include <linux/platform_device.h> 24 #include <linux/spinlock.h> 25 #include <dt-bindings/gpio/uniphier-gpio.h> 26 27 #define UNIPHIER_GPIO_BANK_MASK \ 28 GENMASK((UNIPHIER_GPIO_LINES_PER_BANK) - 1, 0) 29 30 #define UNIPHIER_GPIO_IRQ_MAX_NUM 24 31 32 #define UNIPHIER_GPIO_PORT_DATA 0x0 /* data */ 33 #define UNIPHIER_GPIO_PORT_DIR 0x4 /* direction (1:in, 0:out) */ 34 #define UNIPHIER_GPIO_IRQ_EN 0x90 /* irq enable */ 35 #define UNIPHIER_GPIO_IRQ_MODE 0x94 /* irq mode (1: both edge) */ 36 #define UNIPHIER_GPIO_IRQ_FLT_EN 0x98 /* noise filter enable */ 37 #define UNIPHIER_GPIO_IRQ_FLT_CYC 0x9c /* noise filter clock cycle */ 38 39 struct uniphier_gpio_priv { 40 struct gpio_chip chip; 41 struct irq_chip irq_chip; 42 struct irq_domain *domain; 43 void __iomem *regs; 44 spinlock_t lock; 45 u32 saved_vals[0]; 46 }; 47 48 static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank) 49 { 50 unsigned int reg; 51 52 reg = (bank + 1) * 8; 53 54 /* 55 * Unfortunately, the GPIO port registers are not contiguous because 56 * offset 0x90-0x9f is used for IRQ. Add 0x10 when crossing the region. 57 */ 58 if (reg >= UNIPHIER_GPIO_IRQ_EN) 59 reg += 0x10; 60 61 return reg; 62 } 63 64 static void uniphier_gpio_get_bank_and_mask(unsigned int offset, 65 unsigned int *bank, u32 *mask) 66 { 67 *bank = offset / UNIPHIER_GPIO_LINES_PER_BANK; 68 *mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK); 69 } 70 71 static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv, 72 unsigned int reg, u32 mask, u32 val) 73 { 74 unsigned long flags; 75 u32 tmp; 76 77 spin_lock_irqsave(&priv->lock, flags); 78 tmp = readl(priv->regs + reg); 79 tmp &= ~mask; 80 tmp |= mask & val; 81 writel(tmp, priv->regs + reg); 82 spin_unlock_irqrestore(&priv->lock, flags); 83 } 84 85 static void uniphier_gpio_bank_write(struct gpio_chip *chip, unsigned int bank, 86 unsigned int reg, u32 mask, u32 val) 87 { 88 struct uniphier_gpio_priv *priv = gpiochip_get_data(chip); 89 90 if (!mask) 91 return; 92 93 uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg, 94 mask, val); 95 } 96 97 static void uniphier_gpio_offset_write(struct gpio_chip *chip, 98 unsigned int offset, unsigned int reg, 99 int val) 100 { 101 unsigned int bank; 102 u32 mask; 103 104 uniphier_gpio_get_bank_and_mask(offset, &bank, &mask); 105 106 uniphier_gpio_bank_write(chip, bank, reg, mask, val ? mask : 0); 107 } 108 109 static int uniphier_gpio_offset_read(struct gpio_chip *chip, 110 unsigned int offset, unsigned int reg) 111 { 112 struct uniphier_gpio_priv *priv = gpiochip_get_data(chip); 113 unsigned int bank, reg_offset; 114 u32 mask; 115 116 uniphier_gpio_get_bank_and_mask(offset, &bank, &mask); 117 reg_offset = uniphier_gpio_bank_to_reg(bank) + reg; 118 119 return !!(readl(priv->regs + reg_offset) & mask); 120 } 121 122 static int uniphier_gpio_get_direction(struct gpio_chip *chip, 123 unsigned int offset) 124 { 125 return uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DIR); 126 } 127 128 static int uniphier_gpio_direction_input(struct gpio_chip *chip, 129 unsigned int offset) 130 { 131 uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 1); 132 133 return 0; 134 } 135 136 static int uniphier_gpio_direction_output(struct gpio_chip *chip, 137 unsigned int offset, int val) 138 { 139 uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val); 140 uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 0); 141 142 return 0; 143 } 144 145 static int uniphier_gpio_get(struct gpio_chip *chip, unsigned int offset) 146 { 147 return uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DATA); 148 } 149 150 static void uniphier_gpio_set(struct gpio_chip *chip, 151 unsigned int offset, int val) 152 { 153 uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val); 154 } 155 156 static void uniphier_gpio_set_multiple(struct gpio_chip *chip, 157 unsigned long *mask, unsigned long *bits) 158 { 159 unsigned int bank, shift, bank_mask, bank_bits; 160 int i; 161 162 for (i = 0; i < chip->ngpio; i += UNIPHIER_GPIO_LINES_PER_BANK) { 163 bank = i / UNIPHIER_GPIO_LINES_PER_BANK; 164 shift = i % BITS_PER_LONG; 165 bank_mask = (mask[BIT_WORD(i)] >> shift) & 166 UNIPHIER_GPIO_BANK_MASK; 167 bank_bits = bits[BIT_WORD(i)] >> shift; 168 169 uniphier_gpio_bank_write(chip, bank, UNIPHIER_GPIO_PORT_DATA, 170 bank_mask, bank_bits); 171 } 172 } 173 174 static int uniphier_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) 175 { 176 struct irq_fwspec fwspec; 177 178 if (offset < UNIPHIER_GPIO_IRQ_OFFSET) 179 return -ENXIO; 180 181 fwspec.fwnode = of_node_to_fwnode(chip->parent->of_node); 182 fwspec.param_count = 2; 183 fwspec.param[0] = offset - UNIPHIER_GPIO_IRQ_OFFSET; 184 fwspec.param[1] = IRQ_TYPE_NONE; 185 186 return irq_create_fwspec_mapping(&fwspec); 187 } 188 189 static void uniphier_gpio_irq_mask(struct irq_data *data) 190 { 191 struct uniphier_gpio_priv *priv = data->chip_data; 192 u32 mask = BIT(data->hwirq); 193 194 uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, 0); 195 196 return irq_chip_mask_parent(data); 197 } 198 199 static void uniphier_gpio_irq_unmask(struct irq_data *data) 200 { 201 struct uniphier_gpio_priv *priv = data->chip_data; 202 u32 mask = BIT(data->hwirq); 203 204 uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, mask); 205 206 return irq_chip_unmask_parent(data); 207 } 208 209 static int uniphier_gpio_irq_set_type(struct irq_data *data, unsigned int type) 210 { 211 struct uniphier_gpio_priv *priv = data->chip_data; 212 u32 mask = BIT(data->hwirq); 213 u32 val = 0; 214 215 if (type == IRQ_TYPE_EDGE_BOTH) { 216 val = mask; 217 type = IRQ_TYPE_EDGE_FALLING; 218 } 219 220 uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_MODE, mask, val); 221 /* To enable both edge detection, the noise filter must be enabled. */ 222 uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_FLT_EN, mask, val); 223 224 return irq_chip_set_type_parent(data, type); 225 } 226 227 static int uniphier_gpio_irq_get_parent_hwirq(struct uniphier_gpio_priv *priv, 228 unsigned int hwirq) 229 { 230 struct device_node *np = priv->chip.parent->of_node; 231 const __be32 *range; 232 u32 base, parent_base, size; 233 int len; 234 235 range = of_get_property(np, "socionext,interrupt-ranges", &len); 236 if (!range) 237 return -EINVAL; 238 239 len /= sizeof(*range); 240 241 for (; len >= 3; len -= 3) { 242 base = be32_to_cpu(*range++); 243 parent_base = be32_to_cpu(*range++); 244 size = be32_to_cpu(*range++); 245 246 if (base <= hwirq && hwirq < base + size) 247 return hwirq - base + parent_base; 248 } 249 250 return -ENOENT; 251 } 252 253 static int uniphier_gpio_irq_domain_translate(struct irq_domain *domain, 254 struct irq_fwspec *fwspec, 255 unsigned long *out_hwirq, 256 unsigned int *out_type) 257 { 258 if (WARN_ON(fwspec->param_count < 2)) 259 return -EINVAL; 260 261 *out_hwirq = fwspec->param[0]; 262 *out_type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; 263 264 return 0; 265 } 266 267 static int uniphier_gpio_irq_domain_alloc(struct irq_domain *domain, 268 unsigned int virq, 269 unsigned int nr_irqs, void *arg) 270 { 271 struct uniphier_gpio_priv *priv = domain->host_data; 272 struct irq_fwspec parent_fwspec; 273 irq_hw_number_t hwirq; 274 unsigned int type; 275 int ret; 276 277 if (WARN_ON(nr_irqs != 1)) 278 return -EINVAL; 279 280 ret = uniphier_gpio_irq_domain_translate(domain, arg, &hwirq, &type); 281 if (ret) 282 return ret; 283 284 ret = uniphier_gpio_irq_get_parent_hwirq(priv, hwirq); 285 if (ret < 0) 286 return ret; 287 288 /* parent is UniPhier AIDET */ 289 parent_fwspec.fwnode = domain->parent->fwnode; 290 parent_fwspec.param_count = 2; 291 parent_fwspec.param[0] = ret; 292 parent_fwspec.param[1] = (type == IRQ_TYPE_EDGE_BOTH) ? 293 IRQ_TYPE_EDGE_FALLING : type; 294 295 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, 296 &priv->irq_chip, priv); 297 if (ret) 298 return ret; 299 300 return irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec); 301 } 302 303 static int uniphier_gpio_irq_domain_activate(struct irq_domain *domain, 304 struct irq_data *data, bool early) 305 { 306 struct uniphier_gpio_priv *priv = domain->host_data; 307 struct gpio_chip *chip = &priv->chip; 308 309 gpiochip_lock_as_irq(chip, data->hwirq + UNIPHIER_GPIO_IRQ_OFFSET); 310 return 0; 311 } 312 313 static void uniphier_gpio_irq_domain_deactivate(struct irq_domain *domain, 314 struct irq_data *data) 315 { 316 struct uniphier_gpio_priv *priv = domain->host_data; 317 struct gpio_chip *chip = &priv->chip; 318 319 gpiochip_unlock_as_irq(chip, data->hwirq + UNIPHIER_GPIO_IRQ_OFFSET); 320 } 321 322 static const struct irq_domain_ops uniphier_gpio_irq_domain_ops = { 323 .alloc = uniphier_gpio_irq_domain_alloc, 324 .free = irq_domain_free_irqs_common, 325 .activate = uniphier_gpio_irq_domain_activate, 326 .deactivate = uniphier_gpio_irq_domain_deactivate, 327 .translate = uniphier_gpio_irq_domain_translate, 328 }; 329 330 static void uniphier_gpio_hw_init(struct uniphier_gpio_priv *priv) 331 { 332 /* 333 * Due to the hardware design, the noise filter must be enabled to 334 * detect both edge interrupts. This filter is intended to remove the 335 * noise from the irq lines. It does not work for GPIO input, so GPIO 336 * debounce is not supported. Unfortunately, the filter period is 337 * shared among all irq lines. Just choose a sensible period here. 338 */ 339 writel(0xff, priv->regs + UNIPHIER_GPIO_IRQ_FLT_CYC); 340 } 341 342 static unsigned int uniphier_gpio_get_nbanks(unsigned int ngpio) 343 { 344 return DIV_ROUND_UP(ngpio, UNIPHIER_GPIO_LINES_PER_BANK); 345 } 346 347 static int uniphier_gpio_probe(struct platform_device *pdev) 348 { 349 struct device *dev = &pdev->dev; 350 struct device_node *parent_np; 351 struct irq_domain *parent_domain; 352 struct uniphier_gpio_priv *priv; 353 struct gpio_chip *chip; 354 struct irq_chip *irq_chip; 355 struct resource *regs; 356 unsigned int nregs; 357 u32 ngpios; 358 int ret; 359 360 parent_np = of_irq_find_parent(dev->of_node); 361 if (!parent_np) 362 return -ENXIO; 363 364 parent_domain = irq_find_host(parent_np); 365 of_node_put(parent_np); 366 if (!parent_domain) 367 return -EPROBE_DEFER; 368 369 ret = of_property_read_u32(dev->of_node, "ngpios", &ngpios); 370 if (ret) 371 return ret; 372 373 nregs = uniphier_gpio_get_nbanks(ngpios) * 2 + 3; 374 priv = devm_kzalloc(dev, struct_size(priv, saved_vals, nregs), 375 GFP_KERNEL); 376 if (!priv) 377 return -ENOMEM; 378 379 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 380 priv->regs = devm_ioremap_resource(dev, regs); 381 if (IS_ERR(priv->regs)) 382 return PTR_ERR(priv->regs); 383 384 spin_lock_init(&priv->lock); 385 386 chip = &priv->chip; 387 chip->label = dev_name(dev); 388 chip->parent = dev; 389 chip->request = gpiochip_generic_request; 390 chip->free = gpiochip_generic_free; 391 chip->get_direction = uniphier_gpio_get_direction; 392 chip->direction_input = uniphier_gpio_direction_input; 393 chip->direction_output = uniphier_gpio_direction_output; 394 chip->get = uniphier_gpio_get; 395 chip->set = uniphier_gpio_set; 396 chip->set_multiple = uniphier_gpio_set_multiple; 397 chip->to_irq = uniphier_gpio_to_irq; 398 chip->base = -1; 399 chip->ngpio = ngpios; 400 401 irq_chip = &priv->irq_chip; 402 irq_chip->name = dev_name(dev); 403 irq_chip->irq_mask = uniphier_gpio_irq_mask; 404 irq_chip->irq_unmask = uniphier_gpio_irq_unmask; 405 irq_chip->irq_eoi = irq_chip_eoi_parent; 406 irq_chip->irq_set_affinity = irq_chip_set_affinity_parent; 407 irq_chip->irq_set_type = uniphier_gpio_irq_set_type; 408 409 uniphier_gpio_hw_init(priv); 410 411 ret = devm_gpiochip_add_data(dev, chip, priv); 412 if (ret) 413 return ret; 414 415 priv->domain = irq_domain_create_hierarchy( 416 parent_domain, 0, 417 UNIPHIER_GPIO_IRQ_MAX_NUM, 418 of_node_to_fwnode(dev->of_node), 419 &uniphier_gpio_irq_domain_ops, priv); 420 if (!priv->domain) 421 return -ENOMEM; 422 423 platform_set_drvdata(pdev, priv); 424 425 return 0; 426 } 427 428 static int uniphier_gpio_remove(struct platform_device *pdev) 429 { 430 struct uniphier_gpio_priv *priv = platform_get_drvdata(pdev); 431 432 irq_domain_remove(priv->domain); 433 434 return 0; 435 } 436 437 static int __maybe_unused uniphier_gpio_suspend(struct device *dev) 438 { 439 struct uniphier_gpio_priv *priv = dev_get_drvdata(dev); 440 unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio); 441 u32 *val = priv->saved_vals; 442 unsigned int reg; 443 int i; 444 445 for (i = 0; i < nbanks; i++) { 446 reg = uniphier_gpio_bank_to_reg(i); 447 448 *val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DATA); 449 *val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DIR); 450 } 451 452 *val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_EN); 453 *val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_MODE); 454 *val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN); 455 456 return 0; 457 } 458 459 static int __maybe_unused uniphier_gpio_resume(struct device *dev) 460 { 461 struct uniphier_gpio_priv *priv = dev_get_drvdata(dev); 462 unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio); 463 const u32 *val = priv->saved_vals; 464 unsigned int reg; 465 int i; 466 467 for (i = 0; i < nbanks; i++) { 468 reg = uniphier_gpio_bank_to_reg(i); 469 470 writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DATA); 471 writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DIR); 472 } 473 474 writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_EN); 475 writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_MODE); 476 writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN); 477 478 uniphier_gpio_hw_init(priv); 479 480 return 0; 481 } 482 483 static const struct dev_pm_ops uniphier_gpio_pm_ops = { 484 SET_LATE_SYSTEM_SLEEP_PM_OPS(uniphier_gpio_suspend, 485 uniphier_gpio_resume) 486 }; 487 488 static const struct of_device_id uniphier_gpio_match[] = { 489 { .compatible = "socionext,uniphier-gpio" }, 490 { /* sentinel */ } 491 }; 492 MODULE_DEVICE_TABLE(of, uniphier_gpio_match); 493 494 static struct platform_driver uniphier_gpio_driver = { 495 .probe = uniphier_gpio_probe, 496 .remove = uniphier_gpio_remove, 497 .driver = { 498 .name = "uniphier-gpio", 499 .of_match_table = uniphier_gpio_match, 500 .pm = &uniphier_gpio_pm_ops, 501 }, 502 }; 503 module_platform_driver(uniphier_gpio_driver); 504 505 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>"); 506 MODULE_DESCRIPTION("UniPhier GPIO driver"); 507 MODULE_LICENSE("GPL v2"); 508