1 /*
2  * Timberdale FPGA GPIO driver
3  * Copyright (c) 2009 Intel Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2 as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17  */
18 
19 /* Supports:
20  * Timberdale FPGA GPIO
21  */
22 
23 #include <linux/module.h>
24 #include <linux/gpio.h>
25 #include <linux/platform_device.h>
26 #include <linux/irq.h>
27 #include <linux/io.h>
28 #include <linux/timb_gpio.h>
29 #include <linux/interrupt.h>
30 #include <linux/slab.h>
31 
32 #define DRIVER_NAME "timb-gpio"
33 
34 #define TGPIOVAL	0x00
35 #define TGPIODIR	0x04
36 #define TGPIO_IER	0x08
37 #define TGPIO_ISR	0x0c
38 #define TGPIO_IPR	0x10
39 #define TGPIO_ICR	0x14
40 #define TGPIO_FLR	0x18
41 #define TGPIO_LVR	0x1c
42 #define TGPIO_VER	0x20
43 #define TGPIO_BFLR	0x24
44 
45 struct timbgpio {
46 	void __iomem		*membase;
47 	spinlock_t		lock; /* mutual exclusion */
48 	struct gpio_chip	gpio;
49 	int			irq_base;
50 	unsigned long		last_ier;
51 };
52 
53 static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
54 	unsigned offset, bool enabled)
55 {
56 	struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
57 	u32 reg;
58 
59 	spin_lock(&tgpio->lock);
60 	reg = ioread32(tgpio->membase + offset);
61 
62 	if (enabled)
63 		reg |= (1 << index);
64 	else
65 		reg &= ~(1 << index);
66 
67 	iowrite32(reg, tgpio->membase + offset);
68 	spin_unlock(&tgpio->lock);
69 
70 	return 0;
71 }
72 
73 static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
74 {
75 	return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
76 }
77 
78 static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
79 {
80 	struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
81 	u32 value;
82 
83 	value = ioread32(tgpio->membase + TGPIOVAL);
84 	return (value & (1 << nr)) ? 1 : 0;
85 }
86 
87 static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
88 						unsigned nr, int val)
89 {
90 	return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
91 }
92 
93 static void timbgpio_gpio_set(struct gpio_chip *gpio,
94 				unsigned nr, int val)
95 {
96 	timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
97 }
98 
99 static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
100 {
101 	struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
102 
103 	if (tgpio->irq_base <= 0)
104 		return -EINVAL;
105 
106 	return tgpio->irq_base + offset;
107 }
108 
109 /*
110  * GPIO IRQ
111  */
112 static void timbgpio_irq_disable(struct irq_data *d)
113 {
114 	struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
115 	int offset = d->irq - tgpio->irq_base;
116 	unsigned long flags;
117 
118 	spin_lock_irqsave(&tgpio->lock, flags);
119 	tgpio->last_ier &= ~(1UL << offset);
120 	iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
121 	spin_unlock_irqrestore(&tgpio->lock, flags);
122 }
123 
124 static void timbgpio_irq_enable(struct irq_data *d)
125 {
126 	struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
127 	int offset = d->irq - tgpio->irq_base;
128 	unsigned long flags;
129 
130 	spin_lock_irqsave(&tgpio->lock, flags);
131 	tgpio->last_ier |= 1UL << offset;
132 	iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
133 	spin_unlock_irqrestore(&tgpio->lock, flags);
134 }
135 
136 static int timbgpio_irq_type(struct irq_data *d, unsigned trigger)
137 {
138 	struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
139 	int offset = d->irq - tgpio->irq_base;
140 	unsigned long flags;
141 	u32 lvr, flr, bflr = 0;
142 	u32 ver;
143 	int ret = 0;
144 
145 	if (offset < 0 || offset > tgpio->gpio.ngpio)
146 		return -EINVAL;
147 
148 	ver = ioread32(tgpio->membase + TGPIO_VER);
149 
150 	spin_lock_irqsave(&tgpio->lock, flags);
151 
152 	lvr = ioread32(tgpio->membase + TGPIO_LVR);
153 	flr = ioread32(tgpio->membase + TGPIO_FLR);
154 	if (ver > 2)
155 		bflr = ioread32(tgpio->membase + TGPIO_BFLR);
156 
157 	if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
158 		bflr &= ~(1 << offset);
159 		flr &= ~(1 << offset);
160 		if (trigger & IRQ_TYPE_LEVEL_HIGH)
161 			lvr |= 1 << offset;
162 		else
163 			lvr &= ~(1 << offset);
164 	}
165 
166 	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
167 		if (ver < 3) {
168 			ret = -EINVAL;
169 			goto out;
170 		} else {
171 			flr |= 1 << offset;
172 			bflr |= 1 << offset;
173 		}
174 	} else {
175 		bflr &= ~(1 << offset);
176 		flr |= 1 << offset;
177 		if (trigger & IRQ_TYPE_EDGE_FALLING)
178 			lvr &= ~(1 << offset);
179 		else
180 			lvr |= 1 << offset;
181 	}
182 
183 	iowrite32(lvr, tgpio->membase + TGPIO_LVR);
184 	iowrite32(flr, tgpio->membase + TGPIO_FLR);
185 	if (ver > 2)
186 		iowrite32(bflr, tgpio->membase + TGPIO_BFLR);
187 
188 	iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);
189 
190 out:
191 	spin_unlock_irqrestore(&tgpio->lock, flags);
192 	return ret;
193 }
194 
195 static void timbgpio_irq(struct irq_desc *desc)
196 {
197 	struct timbgpio *tgpio = irq_desc_get_handler_data(desc);
198 	struct irq_data *data = irq_desc_get_irq_data(desc);
199 	unsigned long ipr;
200 	int offset;
201 
202 	data->chip->irq_ack(data);
203 	ipr = ioread32(tgpio->membase + TGPIO_IPR);
204 	iowrite32(ipr, tgpio->membase + TGPIO_ICR);
205 
206 	/*
207 	 * Some versions of the hardware trash the IER register if more than
208 	 * one interrupt is received simultaneously.
209 	 */
210 	iowrite32(0, tgpio->membase + TGPIO_IER);
211 
212 	for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
213 		generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));
214 
215 	iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
216 }
217 
218 static struct irq_chip timbgpio_irqchip = {
219 	.name		= "GPIO",
220 	.irq_enable	= timbgpio_irq_enable,
221 	.irq_disable	= timbgpio_irq_disable,
222 	.irq_set_type	= timbgpio_irq_type,
223 };
224 
225 static int timbgpio_probe(struct platform_device *pdev)
226 {
227 	int err, i;
228 	struct device *dev = &pdev->dev;
229 	struct gpio_chip *gc;
230 	struct timbgpio *tgpio;
231 	struct resource *iomem;
232 	struct timbgpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
233 	int irq = platform_get_irq(pdev, 0);
234 
235 	if (!pdata || pdata->nr_pins > 32) {
236 		dev_err(dev, "Invalid platform data\n");
237 		return -EINVAL;
238 	}
239 
240 	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
241 	if (!iomem) {
242 		dev_err(dev, "Unable to get resource\n");
243 		return -EINVAL;
244 	}
245 
246 	tgpio = devm_kzalloc(dev, sizeof(struct timbgpio), GFP_KERNEL);
247 	if (!tgpio) {
248 		dev_err(dev, "Memory alloc failed\n");
249 		return -EINVAL;
250 	}
251 	tgpio->irq_base = pdata->irq_base;
252 
253 	spin_lock_init(&tgpio->lock);
254 
255 	if (!devm_request_mem_region(dev, iomem->start, resource_size(iomem),
256 				     DRIVER_NAME)) {
257 		dev_err(dev, "Region already claimed\n");
258 		return -EBUSY;
259 	}
260 
261 	tgpio->membase = devm_ioremap(dev, iomem->start, resource_size(iomem));
262 	if (!tgpio->membase) {
263 		dev_err(dev, "Cannot ioremap\n");
264 		return -ENOMEM;
265 	}
266 
267 	gc = &tgpio->gpio;
268 
269 	gc->label = dev_name(&pdev->dev);
270 	gc->owner = THIS_MODULE;
271 	gc->dev = &pdev->dev;
272 	gc->direction_input = timbgpio_gpio_direction_input;
273 	gc->get = timbgpio_gpio_get;
274 	gc->direction_output = timbgpio_gpio_direction_output;
275 	gc->set = timbgpio_gpio_set;
276 	gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
277 	gc->dbg_show = NULL;
278 	gc->base = pdata->gpio_base;
279 	gc->ngpio = pdata->nr_pins;
280 	gc->can_sleep = false;
281 
282 	err = gpiochip_add(gc);
283 	if (err)
284 		return err;
285 
286 	platform_set_drvdata(pdev, tgpio);
287 
288 	/* make sure to disable interrupts */
289 	iowrite32(0x0, tgpio->membase + TGPIO_IER);
290 
291 	if (irq < 0 || tgpio->irq_base <= 0)
292 		return 0;
293 
294 	for (i = 0; i < pdata->nr_pins; i++) {
295 		irq_set_chip_and_handler(tgpio->irq_base + i,
296 			&timbgpio_irqchip, handle_simple_irq);
297 		irq_set_chip_data(tgpio->irq_base + i, tgpio);
298 		irq_clear_status_flags(tgpio->irq_base + i, IRQ_NOREQUEST | IRQ_NOPROBE);
299 	}
300 
301 	irq_set_chained_handler_and_data(irq, timbgpio_irq, tgpio);
302 
303 	return 0;
304 }
305 
306 static int timbgpio_remove(struct platform_device *pdev)
307 {
308 	struct timbgpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
309 	struct timbgpio *tgpio = platform_get_drvdata(pdev);
310 	int irq = platform_get_irq(pdev, 0);
311 
312 	if (irq >= 0 && tgpio->irq_base > 0) {
313 		int i;
314 		for (i = 0; i < pdata->nr_pins; i++) {
315 			irq_set_chip(tgpio->irq_base + i, NULL);
316 			irq_set_chip_data(tgpio->irq_base + i, NULL);
317 		}
318 
319 		irq_set_handler(irq, NULL);
320 		irq_set_handler_data(irq, NULL);
321 	}
322 
323 	gpiochip_remove(&tgpio->gpio);
324 
325 	return 0;
326 }
327 
328 static struct platform_driver timbgpio_platform_driver = {
329 	.driver = {
330 		.name	= DRIVER_NAME,
331 	},
332 	.probe		= timbgpio_probe,
333 	.remove		= timbgpio_remove,
334 };
335 
336 /*--------------------------------------------------------------------------*/
337 
338 module_platform_driver(timbgpio_platform_driver);
339 
340 MODULE_DESCRIPTION("Timberdale GPIO driver");
341 MODULE_LICENSE("GPL v2");
342 MODULE_AUTHOR("Mocean Laboratories");
343 MODULE_ALIAS("platform:"DRIVER_NAME);
344 
345