xref: /openbmc/linux/drivers/gpio/gpio-thunderx.c (revision ba61bb17)
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 2016, 2017 Cavium Inc.
7  */
8 
9 #include <linux/bitops.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/irq.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/pci.h>
17 #include <linux/spinlock.h>
18 
19 
20 #define GPIO_RX_DAT	0x0
21 #define GPIO_TX_SET	0x8
22 #define GPIO_TX_CLR	0x10
23 #define GPIO_CONST	0x90
24 #define  GPIO_CONST_GPIOS_MASK 0xff
25 #define GPIO_BIT_CFG	0x400
26 #define  GPIO_BIT_CFG_TX_OE		BIT(0)
27 #define  GPIO_BIT_CFG_PIN_XOR		BIT(1)
28 #define  GPIO_BIT_CFG_INT_EN		BIT(2)
29 #define  GPIO_BIT_CFG_INT_TYPE		BIT(3)
30 #define  GPIO_BIT_CFG_FIL_MASK		GENMASK(11, 4)
31 #define  GPIO_BIT_CFG_FIL_CNT_SHIFT	4
32 #define  GPIO_BIT_CFG_FIL_SEL_SHIFT	8
33 #define  GPIO_BIT_CFG_TX_OD		BIT(12)
34 #define  GPIO_BIT_CFG_PIN_SEL_MASK	GENMASK(25, 16)
35 #define GPIO_INTR	0x800
36 #define  GPIO_INTR_INTR			BIT(0)
37 #define  GPIO_INTR_INTR_W1S		BIT(1)
38 #define  GPIO_INTR_ENA_W1C		BIT(2)
39 #define  GPIO_INTR_ENA_W1S		BIT(3)
40 #define GPIO_2ND_BANK	0x1400
41 
42 #define GLITCH_FILTER_400NS ((4u << GPIO_BIT_CFG_FIL_SEL_SHIFT) | \
43 			     (9u << GPIO_BIT_CFG_FIL_CNT_SHIFT))
44 
45 struct thunderx_gpio;
46 
47 struct thunderx_line {
48 	struct thunderx_gpio	*txgpio;
49 	unsigned int		line;
50 	unsigned int		fil_bits;
51 };
52 
53 struct thunderx_gpio {
54 	struct gpio_chip	chip;
55 	u8 __iomem		*register_base;
56 	struct irq_domain	*irqd;
57 	struct msix_entry	*msix_entries;	/* per line MSI-X */
58 	struct thunderx_line	*line_entries;	/* per line irq info */
59 	raw_spinlock_t		lock;
60 	unsigned long		invert_mask[2];
61 	unsigned long		od_mask[2];
62 	int			base_msi;
63 };
64 
65 static unsigned int bit_cfg_reg(unsigned int line)
66 {
67 	return 8 * line + GPIO_BIT_CFG;
68 }
69 
70 static unsigned int intr_reg(unsigned int line)
71 {
72 	return 8 * line + GPIO_INTR;
73 }
74 
75 static bool thunderx_gpio_is_gpio_nowarn(struct thunderx_gpio *txgpio,
76 					 unsigned int line)
77 {
78 	u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
79 
80 	return (bit_cfg & GPIO_BIT_CFG_PIN_SEL_MASK) == 0;
81 }
82 
83 /*
84  * Check (and WARN) that the pin is available for GPIO.  We will not
85  * allow modification of the state of non-GPIO pins from this driver.
86  */
87 static bool thunderx_gpio_is_gpio(struct thunderx_gpio *txgpio,
88 				  unsigned int line)
89 {
90 	bool rv = thunderx_gpio_is_gpio_nowarn(txgpio, line);
91 
92 	WARN_RATELIMIT(!rv, "Pin %d not available for GPIO\n", line);
93 
94 	return rv;
95 }
96 
97 static int thunderx_gpio_request(struct gpio_chip *chip, unsigned int line)
98 {
99 	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
100 
101 	return thunderx_gpio_is_gpio(txgpio, line) ? 0 : -EIO;
102 }
103 
104 static int thunderx_gpio_dir_in(struct gpio_chip *chip, unsigned int line)
105 {
106 	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
107 
108 	if (!thunderx_gpio_is_gpio(txgpio, line))
109 		return -EIO;
110 
111 	raw_spin_lock(&txgpio->lock);
112 	clear_bit(line, txgpio->invert_mask);
113 	clear_bit(line, txgpio->od_mask);
114 	writeq(txgpio->line_entries[line].fil_bits,
115 	       txgpio->register_base + bit_cfg_reg(line));
116 	raw_spin_unlock(&txgpio->lock);
117 	return 0;
118 }
119 
120 static void thunderx_gpio_set(struct gpio_chip *chip, unsigned int line,
121 			      int value)
122 {
123 	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
124 	int bank = line / 64;
125 	int bank_bit = line % 64;
126 
127 	void __iomem *reg = txgpio->register_base +
128 		(bank * GPIO_2ND_BANK) + (value ? GPIO_TX_SET : GPIO_TX_CLR);
129 
130 	writeq(BIT_ULL(bank_bit), reg);
131 }
132 
133 static int thunderx_gpio_dir_out(struct gpio_chip *chip, unsigned int line,
134 				 int value)
135 {
136 	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
137 	u64 bit_cfg = txgpio->line_entries[line].fil_bits | GPIO_BIT_CFG_TX_OE;
138 
139 	if (!thunderx_gpio_is_gpio(txgpio, line))
140 		return -EIO;
141 
142 	raw_spin_lock(&txgpio->lock);
143 
144 	thunderx_gpio_set(chip, line, value);
145 
146 	if (test_bit(line, txgpio->invert_mask))
147 		bit_cfg |= GPIO_BIT_CFG_PIN_XOR;
148 
149 	if (test_bit(line, txgpio->od_mask))
150 		bit_cfg |= GPIO_BIT_CFG_TX_OD;
151 
152 	writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));
153 
154 	raw_spin_unlock(&txgpio->lock);
155 	return 0;
156 }
157 
158 static int thunderx_gpio_get_direction(struct gpio_chip *chip, unsigned int line)
159 {
160 	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
161 	u64 bit_cfg;
162 
163 	if (!thunderx_gpio_is_gpio_nowarn(txgpio, line))
164 		/*
165 		 * Say it is input for now to avoid WARNing on
166 		 * gpiochip_add_data().  We will WARN if someone
167 		 * requests it or tries to use it.
168 		 */
169 		return 1;
170 
171 	bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
172 
173 	return !(bit_cfg & GPIO_BIT_CFG_TX_OE);
174 }
175 
176 static int thunderx_gpio_set_config(struct gpio_chip *chip,
177 				    unsigned int line,
178 				    unsigned long cfg)
179 {
180 	bool orig_invert, orig_od, orig_dat, new_invert, new_od;
181 	u32 arg, sel;
182 	u64 bit_cfg;
183 	int bank = line / 64;
184 	int bank_bit = line % 64;
185 	int ret = -ENOTSUPP;
186 	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
187 	void __iomem *reg = txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET;
188 
189 	if (!thunderx_gpio_is_gpio(txgpio, line))
190 		return -EIO;
191 
192 	raw_spin_lock(&txgpio->lock);
193 	orig_invert = test_bit(line, txgpio->invert_mask);
194 	new_invert  = orig_invert;
195 	orig_od = test_bit(line, txgpio->od_mask);
196 	new_od = orig_od;
197 	orig_dat = ((readq(reg) >> bank_bit) & 1) ^ orig_invert;
198 	bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
199 	switch (pinconf_to_config_param(cfg)) {
200 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
201 		/*
202 		 * Weird, setting open-drain mode causes signal
203 		 * inversion.  Note this so we can compensate in the
204 		 * dir_out function.
205 		 */
206 		set_bit(line, txgpio->invert_mask);
207 		new_invert  = true;
208 		set_bit(line, txgpio->od_mask);
209 		new_od = true;
210 		ret = 0;
211 		break;
212 	case PIN_CONFIG_DRIVE_PUSH_PULL:
213 		clear_bit(line, txgpio->invert_mask);
214 		new_invert  = false;
215 		clear_bit(line, txgpio->od_mask);
216 		new_od  = false;
217 		ret = 0;
218 		break;
219 	case PIN_CONFIG_INPUT_DEBOUNCE:
220 		arg = pinconf_to_config_argument(cfg);
221 		if (arg > 1228) { /* 15 * 2^15 * 2.5nS maximum */
222 			ret = -EINVAL;
223 			break;
224 		}
225 		arg *= 400; /* scale to 2.5nS clocks. */
226 		sel = 0;
227 		while (arg > 15) {
228 			sel++;
229 			arg++; /* always round up */
230 			arg >>= 1;
231 		}
232 		txgpio->line_entries[line].fil_bits =
233 			(sel << GPIO_BIT_CFG_FIL_SEL_SHIFT) |
234 			(arg << GPIO_BIT_CFG_FIL_CNT_SHIFT);
235 		bit_cfg &= ~GPIO_BIT_CFG_FIL_MASK;
236 		bit_cfg |= txgpio->line_entries[line].fil_bits;
237 		writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));
238 		ret = 0;
239 		break;
240 	default:
241 		break;
242 	}
243 	raw_spin_unlock(&txgpio->lock);
244 
245 	/*
246 	 * If currently output and OPEN_DRAIN changed, install the new
247 	 * settings
248 	 */
249 	if ((new_invert != orig_invert || new_od != orig_od) &&
250 	    (bit_cfg & GPIO_BIT_CFG_TX_OE))
251 		ret = thunderx_gpio_dir_out(chip, line, orig_dat ^ new_invert);
252 
253 	return ret;
254 }
255 
256 static int thunderx_gpio_get(struct gpio_chip *chip, unsigned int line)
257 {
258 	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
259 	int bank = line / 64;
260 	int bank_bit = line % 64;
261 	u64 read_bits = readq(txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_RX_DAT);
262 	u64 masked_bits = read_bits & BIT_ULL(bank_bit);
263 
264 	if (test_bit(line, txgpio->invert_mask))
265 		return masked_bits == 0;
266 	else
267 		return masked_bits != 0;
268 }
269 
270 static void thunderx_gpio_set_multiple(struct gpio_chip *chip,
271 				       unsigned long *mask,
272 				       unsigned long *bits)
273 {
274 	int bank;
275 	u64 set_bits, clear_bits;
276 	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
277 
278 	for (bank = 0; bank <= chip->ngpio / 64; bank++) {
279 		set_bits = bits[bank] & mask[bank];
280 		clear_bits = ~bits[bank] & mask[bank];
281 		writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET);
282 		writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR);
283 	}
284 }
285 
286 static void thunderx_gpio_irq_ack(struct irq_data *data)
287 {
288 	struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
289 
290 	writeq(GPIO_INTR_INTR,
291 	       txline->txgpio->register_base + intr_reg(txline->line));
292 }
293 
294 static void thunderx_gpio_irq_mask(struct irq_data *data)
295 {
296 	struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
297 
298 	writeq(GPIO_INTR_ENA_W1C,
299 	       txline->txgpio->register_base + intr_reg(txline->line));
300 }
301 
302 static void thunderx_gpio_irq_mask_ack(struct irq_data *data)
303 {
304 	struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
305 
306 	writeq(GPIO_INTR_ENA_W1C | GPIO_INTR_INTR,
307 	       txline->txgpio->register_base + intr_reg(txline->line));
308 }
309 
310 static void thunderx_gpio_irq_unmask(struct irq_data *data)
311 {
312 	struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
313 
314 	writeq(GPIO_INTR_ENA_W1S,
315 	       txline->txgpio->register_base + intr_reg(txline->line));
316 }
317 
318 static int thunderx_gpio_irq_set_type(struct irq_data *data,
319 				      unsigned int flow_type)
320 {
321 	struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
322 	struct thunderx_gpio *txgpio = txline->txgpio;
323 	u64 bit_cfg;
324 
325 	irqd_set_trigger_type(data, flow_type);
326 
327 	bit_cfg = txline->fil_bits | GPIO_BIT_CFG_INT_EN;
328 
329 	if (flow_type & IRQ_TYPE_EDGE_BOTH) {
330 		irq_set_handler_locked(data, handle_fasteoi_ack_irq);
331 		bit_cfg |= GPIO_BIT_CFG_INT_TYPE;
332 	} else {
333 		irq_set_handler_locked(data, handle_fasteoi_mask_irq);
334 	}
335 
336 	raw_spin_lock(&txgpio->lock);
337 	if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)) {
338 		bit_cfg |= GPIO_BIT_CFG_PIN_XOR;
339 		set_bit(txline->line, txgpio->invert_mask);
340 	} else {
341 		clear_bit(txline->line, txgpio->invert_mask);
342 	}
343 	clear_bit(txline->line, txgpio->od_mask);
344 	writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(txline->line));
345 	raw_spin_unlock(&txgpio->lock);
346 
347 	return IRQ_SET_MASK_OK;
348 }
349 
350 static void thunderx_gpio_irq_enable(struct irq_data *data)
351 {
352 	irq_chip_enable_parent(data);
353 	thunderx_gpio_irq_unmask(data);
354 }
355 
356 static void thunderx_gpio_irq_disable(struct irq_data *data)
357 {
358 	thunderx_gpio_irq_mask(data);
359 	irq_chip_disable_parent(data);
360 }
361 
362 static int thunderx_gpio_irq_request_resources(struct irq_data *data)
363 {
364 	struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
365 	struct thunderx_gpio *txgpio = txline->txgpio;
366 	struct irq_data *parent_data = data->parent_data;
367 	int r;
368 
369 	r = gpiochip_lock_as_irq(&txgpio->chip, txline->line);
370 	if (r)
371 		return r;
372 
373 	if (parent_data && parent_data->chip->irq_request_resources) {
374 		r = parent_data->chip->irq_request_resources(parent_data);
375 		if (r)
376 			goto error;
377 	}
378 
379 	return 0;
380 error:
381 	gpiochip_unlock_as_irq(&txgpio->chip, txline->line);
382 	return r;
383 }
384 
385 static void thunderx_gpio_irq_release_resources(struct irq_data *data)
386 {
387 	struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
388 	struct thunderx_gpio *txgpio = txline->txgpio;
389 	struct irq_data *parent_data = data->parent_data;
390 
391 	if (parent_data && parent_data->chip->irq_release_resources)
392 		parent_data->chip->irq_release_resources(parent_data);
393 
394 	gpiochip_unlock_as_irq(&txgpio->chip, txline->line);
395 }
396 
397 /*
398  * Interrupts are chained from underlying MSI-X vectors.  We have
399  * these irq_chip functions to be able to handle level triggering
400  * semantics and other acknowledgment tasks associated with the GPIO
401  * mechanism.
402  */
403 static struct irq_chip thunderx_gpio_irq_chip = {
404 	.name			= "GPIO",
405 	.irq_enable		= thunderx_gpio_irq_enable,
406 	.irq_disable		= thunderx_gpio_irq_disable,
407 	.irq_ack		= thunderx_gpio_irq_ack,
408 	.irq_mask		= thunderx_gpio_irq_mask,
409 	.irq_mask_ack		= thunderx_gpio_irq_mask_ack,
410 	.irq_unmask		= thunderx_gpio_irq_unmask,
411 	.irq_eoi		= irq_chip_eoi_parent,
412 	.irq_set_affinity	= irq_chip_set_affinity_parent,
413 	.irq_request_resources	= thunderx_gpio_irq_request_resources,
414 	.irq_release_resources	= thunderx_gpio_irq_release_resources,
415 	.irq_set_type		= thunderx_gpio_irq_set_type,
416 
417 	.flags			= IRQCHIP_SET_TYPE_MASKED
418 };
419 
420 static int thunderx_gpio_irq_translate(struct irq_domain *d,
421 				       struct irq_fwspec *fwspec,
422 				       irq_hw_number_t *hwirq,
423 				       unsigned int *type)
424 {
425 	struct thunderx_gpio *txgpio = d->host_data;
426 
427 	if (WARN_ON(fwspec->param_count < 2))
428 		return -EINVAL;
429 	if (fwspec->param[0] >= txgpio->chip.ngpio)
430 		return -EINVAL;
431 	*hwirq = fwspec->param[0];
432 	*type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
433 	return 0;
434 }
435 
436 static int thunderx_gpio_irq_alloc(struct irq_domain *d, unsigned int virq,
437 				   unsigned int nr_irqs, void *arg)
438 {
439 	struct thunderx_line *txline = arg;
440 
441 	return irq_domain_set_hwirq_and_chip(d, virq, txline->line,
442 					     &thunderx_gpio_irq_chip, txline);
443 }
444 
445 static const struct irq_domain_ops thunderx_gpio_irqd_ops = {
446 	.alloc		= thunderx_gpio_irq_alloc,
447 	.translate	= thunderx_gpio_irq_translate
448 };
449 
450 static int thunderx_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
451 {
452 	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
453 
454 	return irq_find_mapping(txgpio->irqd, offset);
455 }
456 
457 static int thunderx_gpio_probe(struct pci_dev *pdev,
458 			       const struct pci_device_id *id)
459 {
460 	void __iomem * const *tbl;
461 	struct device *dev = &pdev->dev;
462 	struct thunderx_gpio *txgpio;
463 	struct gpio_chip *chip;
464 	int ngpio, i;
465 	int err = 0;
466 
467 	txgpio = devm_kzalloc(dev, sizeof(*txgpio), GFP_KERNEL);
468 	if (!txgpio)
469 		return -ENOMEM;
470 
471 	raw_spin_lock_init(&txgpio->lock);
472 	chip = &txgpio->chip;
473 
474 	pci_set_drvdata(pdev, txgpio);
475 
476 	err = pcim_enable_device(pdev);
477 	if (err) {
478 		dev_err(dev, "Failed to enable PCI device: err %d\n", err);
479 		goto out;
480 	}
481 
482 	err = pcim_iomap_regions(pdev, 1 << 0, KBUILD_MODNAME);
483 	if (err) {
484 		dev_err(dev, "Failed to iomap PCI device: err %d\n", err);
485 		goto out;
486 	}
487 
488 	tbl = pcim_iomap_table(pdev);
489 	txgpio->register_base = tbl[0];
490 	if (!txgpio->register_base) {
491 		dev_err(dev, "Cannot map PCI resource\n");
492 		err = -ENOMEM;
493 		goto out;
494 	}
495 
496 	if (pdev->subsystem_device == 0xa10a) {
497 		/* CN88XX has no GPIO_CONST register*/
498 		ngpio = 50;
499 		txgpio->base_msi = 48;
500 	} else {
501 		u64 c = readq(txgpio->register_base + GPIO_CONST);
502 
503 		ngpio = c & GPIO_CONST_GPIOS_MASK;
504 		txgpio->base_msi = (c >> 8) & 0xff;
505 	}
506 
507 	txgpio->msix_entries = devm_kcalloc(dev,
508 					  ngpio, sizeof(struct msix_entry),
509 					  GFP_KERNEL);
510 	if (!txgpio->msix_entries) {
511 		err = -ENOMEM;
512 		goto out;
513 	}
514 
515 	txgpio->line_entries = devm_kcalloc(dev,
516 					    ngpio,
517 					    sizeof(struct thunderx_line),
518 					    GFP_KERNEL);
519 	if (!txgpio->line_entries) {
520 		err = -ENOMEM;
521 		goto out;
522 	}
523 
524 	for (i = 0; i < ngpio; i++) {
525 		u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(i));
526 
527 		txgpio->msix_entries[i].entry = txgpio->base_msi + (2 * i);
528 		txgpio->line_entries[i].line = i;
529 		txgpio->line_entries[i].txgpio = txgpio;
530 		/*
531 		 * If something has already programmed the pin, use
532 		 * the existing glitch filter settings, otherwise go
533 		 * to 400nS.
534 		 */
535 		txgpio->line_entries[i].fil_bits = bit_cfg ?
536 			(bit_cfg & GPIO_BIT_CFG_FIL_MASK) : GLITCH_FILTER_400NS;
537 
538 		if ((bit_cfg & GPIO_BIT_CFG_TX_OE) && (bit_cfg & GPIO_BIT_CFG_TX_OD))
539 			set_bit(i, txgpio->od_mask);
540 		if (bit_cfg & GPIO_BIT_CFG_PIN_XOR)
541 			set_bit(i, txgpio->invert_mask);
542 	}
543 
544 
545 	/* Enable all MSI-X for interrupts on all possible lines. */
546 	err = pci_enable_msix_range(pdev, txgpio->msix_entries, ngpio, ngpio);
547 	if (err < 0)
548 		goto out;
549 
550 	/*
551 	 * Push GPIO specific irqdomain on hierarchy created as a side
552 	 * effect of the pci_enable_msix()
553 	 */
554 	txgpio->irqd = irq_domain_create_hierarchy(irq_get_irq_data(txgpio->msix_entries[0].vector)->domain,
555 						   0, 0, of_node_to_fwnode(dev->of_node),
556 						   &thunderx_gpio_irqd_ops, txgpio);
557 	if (!txgpio->irqd) {
558 		err = -ENOMEM;
559 		goto out;
560 	}
561 
562 	/* Push on irq_data and the domain for each line. */
563 	for (i = 0; i < ngpio; i++) {
564 		err = irq_domain_push_irq(txgpio->irqd,
565 					  txgpio->msix_entries[i].vector,
566 					  &txgpio->line_entries[i]);
567 		if (err < 0)
568 			dev_err(dev, "irq_domain_push_irq: %d\n", err);
569 	}
570 
571 	chip->label = KBUILD_MODNAME;
572 	chip->parent = dev;
573 	chip->owner = THIS_MODULE;
574 	chip->request = thunderx_gpio_request;
575 	chip->base = -1; /* System allocated */
576 	chip->can_sleep = false;
577 	chip->ngpio = ngpio;
578 	chip->get_direction = thunderx_gpio_get_direction;
579 	chip->direction_input = thunderx_gpio_dir_in;
580 	chip->get = thunderx_gpio_get;
581 	chip->direction_output = thunderx_gpio_dir_out;
582 	chip->set = thunderx_gpio_set;
583 	chip->set_multiple = thunderx_gpio_set_multiple;
584 	chip->set_config = thunderx_gpio_set_config;
585 	chip->to_irq = thunderx_gpio_to_irq;
586 	err = devm_gpiochip_add_data(dev, chip, txgpio);
587 	if (err)
588 		goto out;
589 
590 	dev_info(dev, "ThunderX GPIO: %d lines with base %d.\n",
591 		 ngpio, chip->base);
592 	return 0;
593 out:
594 	pci_set_drvdata(pdev, NULL);
595 	return err;
596 }
597 
598 static void thunderx_gpio_remove(struct pci_dev *pdev)
599 {
600 	int i;
601 	struct thunderx_gpio *txgpio = pci_get_drvdata(pdev);
602 
603 	for (i = 0; i < txgpio->chip.ngpio; i++)
604 		irq_domain_pop_irq(txgpio->irqd,
605 				   txgpio->msix_entries[i].vector);
606 
607 	irq_domain_remove(txgpio->irqd);
608 
609 	pci_set_drvdata(pdev, NULL);
610 }
611 
612 static const struct pci_device_id thunderx_gpio_id_table[] = {
613 	{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 0xA00A) },
614 	{ 0, }	/* end of table */
615 };
616 
617 MODULE_DEVICE_TABLE(pci, thunderx_gpio_id_table);
618 
619 static struct pci_driver thunderx_gpio_driver = {
620 	.name = KBUILD_MODNAME,
621 	.id_table = thunderx_gpio_id_table,
622 	.probe = thunderx_gpio_probe,
623 	.remove = thunderx_gpio_remove,
624 };
625 
626 module_pci_driver(thunderx_gpio_driver);
627 
628 MODULE_DESCRIPTION("Cavium Inc. ThunderX/OCTEON-TX GPIO Driver");
629 MODULE_LICENSE("GPL");
630