1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2016, 2017 Cavium Inc. 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/irq.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/pci.h> 17 #include <linux/spinlock.h> 18 19 20 #define GPIO_RX_DAT 0x0 21 #define GPIO_TX_SET 0x8 22 #define GPIO_TX_CLR 0x10 23 #define GPIO_CONST 0x90 24 #define GPIO_CONST_GPIOS_MASK 0xff 25 #define GPIO_BIT_CFG 0x400 26 #define GPIO_BIT_CFG_TX_OE BIT(0) 27 #define GPIO_BIT_CFG_PIN_XOR BIT(1) 28 #define GPIO_BIT_CFG_INT_EN BIT(2) 29 #define GPIO_BIT_CFG_INT_TYPE BIT(3) 30 #define GPIO_BIT_CFG_FIL_MASK GENMASK(11, 4) 31 #define GPIO_BIT_CFG_FIL_CNT_SHIFT 4 32 #define GPIO_BIT_CFG_FIL_SEL_SHIFT 8 33 #define GPIO_BIT_CFG_TX_OD BIT(12) 34 #define GPIO_BIT_CFG_PIN_SEL_MASK GENMASK(25, 16) 35 #define GPIO_INTR 0x800 36 #define GPIO_INTR_INTR BIT(0) 37 #define GPIO_INTR_INTR_W1S BIT(1) 38 #define GPIO_INTR_ENA_W1C BIT(2) 39 #define GPIO_INTR_ENA_W1S BIT(3) 40 #define GPIO_2ND_BANK 0x1400 41 42 #define GLITCH_FILTER_400NS ((4u << GPIO_BIT_CFG_FIL_SEL_SHIFT) | \ 43 (9u << GPIO_BIT_CFG_FIL_CNT_SHIFT)) 44 45 struct thunderx_gpio; 46 47 struct thunderx_line { 48 struct thunderx_gpio *txgpio; 49 unsigned int line; 50 unsigned int fil_bits; 51 }; 52 53 struct thunderx_gpio { 54 struct gpio_chip chip; 55 u8 __iomem *register_base; 56 struct msix_entry *msix_entries; /* per line MSI-X */ 57 struct thunderx_line *line_entries; /* per line irq info */ 58 raw_spinlock_t lock; 59 unsigned long invert_mask[2]; 60 unsigned long od_mask[2]; 61 int base_msi; 62 }; 63 64 static unsigned int bit_cfg_reg(unsigned int line) 65 { 66 return 8 * line + GPIO_BIT_CFG; 67 } 68 69 static unsigned int intr_reg(unsigned int line) 70 { 71 return 8 * line + GPIO_INTR; 72 } 73 74 static bool thunderx_gpio_is_gpio_nowarn(struct thunderx_gpio *txgpio, 75 unsigned int line) 76 { 77 u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line)); 78 79 return (bit_cfg & GPIO_BIT_CFG_PIN_SEL_MASK) == 0; 80 } 81 82 /* 83 * Check (and WARN) that the pin is available for GPIO. We will not 84 * allow modification of the state of non-GPIO pins from this driver. 85 */ 86 static bool thunderx_gpio_is_gpio(struct thunderx_gpio *txgpio, 87 unsigned int line) 88 { 89 bool rv = thunderx_gpio_is_gpio_nowarn(txgpio, line); 90 91 WARN_RATELIMIT(!rv, "Pin %d not available for GPIO\n", line); 92 93 return rv; 94 } 95 96 static int thunderx_gpio_request(struct gpio_chip *chip, unsigned int line) 97 { 98 struct thunderx_gpio *txgpio = gpiochip_get_data(chip); 99 100 return thunderx_gpio_is_gpio(txgpio, line) ? 0 : -EIO; 101 } 102 103 static int thunderx_gpio_dir_in(struct gpio_chip *chip, unsigned int line) 104 { 105 struct thunderx_gpio *txgpio = gpiochip_get_data(chip); 106 107 if (!thunderx_gpio_is_gpio(txgpio, line)) 108 return -EIO; 109 110 raw_spin_lock(&txgpio->lock); 111 clear_bit(line, txgpio->invert_mask); 112 clear_bit(line, txgpio->od_mask); 113 writeq(txgpio->line_entries[line].fil_bits, 114 txgpio->register_base + bit_cfg_reg(line)); 115 raw_spin_unlock(&txgpio->lock); 116 return 0; 117 } 118 119 static void thunderx_gpio_set(struct gpio_chip *chip, unsigned int line, 120 int value) 121 { 122 struct thunderx_gpio *txgpio = gpiochip_get_data(chip); 123 int bank = line / 64; 124 int bank_bit = line % 64; 125 126 void __iomem *reg = txgpio->register_base + 127 (bank * GPIO_2ND_BANK) + (value ? GPIO_TX_SET : GPIO_TX_CLR); 128 129 writeq(BIT_ULL(bank_bit), reg); 130 } 131 132 static int thunderx_gpio_dir_out(struct gpio_chip *chip, unsigned int line, 133 int value) 134 { 135 struct thunderx_gpio *txgpio = gpiochip_get_data(chip); 136 u64 bit_cfg = txgpio->line_entries[line].fil_bits | GPIO_BIT_CFG_TX_OE; 137 138 if (!thunderx_gpio_is_gpio(txgpio, line)) 139 return -EIO; 140 141 raw_spin_lock(&txgpio->lock); 142 143 thunderx_gpio_set(chip, line, value); 144 145 if (test_bit(line, txgpio->invert_mask)) 146 bit_cfg |= GPIO_BIT_CFG_PIN_XOR; 147 148 if (test_bit(line, txgpio->od_mask)) 149 bit_cfg |= GPIO_BIT_CFG_TX_OD; 150 151 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line)); 152 153 raw_spin_unlock(&txgpio->lock); 154 return 0; 155 } 156 157 static int thunderx_gpio_get_direction(struct gpio_chip *chip, unsigned int line) 158 { 159 struct thunderx_gpio *txgpio = gpiochip_get_data(chip); 160 u64 bit_cfg; 161 162 if (!thunderx_gpio_is_gpio_nowarn(txgpio, line)) 163 /* 164 * Say it is input for now to avoid WARNing on 165 * gpiochip_add_data(). We will WARN if someone 166 * requests it or tries to use it. 167 */ 168 return 1; 169 170 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line)); 171 172 if (bit_cfg & GPIO_BIT_CFG_TX_OE) 173 return GPIO_LINE_DIRECTION_OUT; 174 175 return GPIO_LINE_DIRECTION_IN; 176 } 177 178 static int thunderx_gpio_set_config(struct gpio_chip *chip, 179 unsigned int line, 180 unsigned long cfg) 181 { 182 bool orig_invert, orig_od, orig_dat, new_invert, new_od; 183 u32 arg, sel; 184 u64 bit_cfg; 185 int bank = line / 64; 186 int bank_bit = line % 64; 187 int ret = -ENOTSUPP; 188 struct thunderx_gpio *txgpio = gpiochip_get_data(chip); 189 void __iomem *reg = txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET; 190 191 if (!thunderx_gpio_is_gpio(txgpio, line)) 192 return -EIO; 193 194 raw_spin_lock(&txgpio->lock); 195 orig_invert = test_bit(line, txgpio->invert_mask); 196 new_invert = orig_invert; 197 orig_od = test_bit(line, txgpio->od_mask); 198 new_od = orig_od; 199 orig_dat = ((readq(reg) >> bank_bit) & 1) ^ orig_invert; 200 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line)); 201 switch (pinconf_to_config_param(cfg)) { 202 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 203 /* 204 * Weird, setting open-drain mode causes signal 205 * inversion. Note this so we can compensate in the 206 * dir_out function. 207 */ 208 set_bit(line, txgpio->invert_mask); 209 new_invert = true; 210 set_bit(line, txgpio->od_mask); 211 new_od = true; 212 ret = 0; 213 break; 214 case PIN_CONFIG_DRIVE_PUSH_PULL: 215 clear_bit(line, txgpio->invert_mask); 216 new_invert = false; 217 clear_bit(line, txgpio->od_mask); 218 new_od = false; 219 ret = 0; 220 break; 221 case PIN_CONFIG_INPUT_DEBOUNCE: 222 arg = pinconf_to_config_argument(cfg); 223 if (arg > 1228) { /* 15 * 2^15 * 2.5nS maximum */ 224 ret = -EINVAL; 225 break; 226 } 227 arg *= 400; /* scale to 2.5nS clocks. */ 228 sel = 0; 229 while (arg > 15) { 230 sel++; 231 arg++; /* always round up */ 232 arg >>= 1; 233 } 234 txgpio->line_entries[line].fil_bits = 235 (sel << GPIO_BIT_CFG_FIL_SEL_SHIFT) | 236 (arg << GPIO_BIT_CFG_FIL_CNT_SHIFT); 237 bit_cfg &= ~GPIO_BIT_CFG_FIL_MASK; 238 bit_cfg |= txgpio->line_entries[line].fil_bits; 239 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line)); 240 ret = 0; 241 break; 242 default: 243 break; 244 } 245 raw_spin_unlock(&txgpio->lock); 246 247 /* 248 * If currently output and OPEN_DRAIN changed, install the new 249 * settings 250 */ 251 if ((new_invert != orig_invert || new_od != orig_od) && 252 (bit_cfg & GPIO_BIT_CFG_TX_OE)) 253 ret = thunderx_gpio_dir_out(chip, line, orig_dat ^ new_invert); 254 255 return ret; 256 } 257 258 static int thunderx_gpio_get(struct gpio_chip *chip, unsigned int line) 259 { 260 struct thunderx_gpio *txgpio = gpiochip_get_data(chip); 261 int bank = line / 64; 262 int bank_bit = line % 64; 263 u64 read_bits = readq(txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_RX_DAT); 264 u64 masked_bits = read_bits & BIT_ULL(bank_bit); 265 266 if (test_bit(line, txgpio->invert_mask)) 267 return masked_bits == 0; 268 else 269 return masked_bits != 0; 270 } 271 272 static void thunderx_gpio_set_multiple(struct gpio_chip *chip, 273 unsigned long *mask, 274 unsigned long *bits) 275 { 276 int bank; 277 u64 set_bits, clear_bits; 278 struct thunderx_gpio *txgpio = gpiochip_get_data(chip); 279 280 for (bank = 0; bank <= chip->ngpio / 64; bank++) { 281 set_bits = bits[bank] & mask[bank]; 282 clear_bits = ~bits[bank] & mask[bank]; 283 writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET); 284 writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR); 285 } 286 } 287 288 static void thunderx_gpio_irq_ack(struct irq_data *d) 289 { 290 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 291 struct thunderx_gpio *txgpio = gpiochip_get_data(gc); 292 293 writeq(GPIO_INTR_INTR, 294 txgpio->register_base + intr_reg(irqd_to_hwirq(d))); 295 } 296 297 static void thunderx_gpio_irq_mask(struct irq_data *d) 298 { 299 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 300 struct thunderx_gpio *txgpio = gpiochip_get_data(gc); 301 302 writeq(GPIO_INTR_ENA_W1C, 303 txgpio->register_base + intr_reg(irqd_to_hwirq(d))); 304 } 305 306 static void thunderx_gpio_irq_mask_ack(struct irq_data *d) 307 { 308 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 309 struct thunderx_gpio *txgpio = gpiochip_get_data(gc); 310 311 writeq(GPIO_INTR_ENA_W1C | GPIO_INTR_INTR, 312 txgpio->register_base + intr_reg(irqd_to_hwirq(d))); 313 } 314 315 static void thunderx_gpio_irq_unmask(struct irq_data *d) 316 { 317 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 318 struct thunderx_gpio *txgpio = gpiochip_get_data(gc); 319 320 writeq(GPIO_INTR_ENA_W1S, 321 txgpio->register_base + intr_reg(irqd_to_hwirq(d))); 322 } 323 324 static int thunderx_gpio_irq_set_type(struct irq_data *d, 325 unsigned int flow_type) 326 { 327 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 328 struct thunderx_gpio *txgpio = gpiochip_get_data(gc); 329 struct thunderx_line *txline = 330 &txgpio->line_entries[irqd_to_hwirq(d)]; 331 u64 bit_cfg; 332 333 irqd_set_trigger_type(d, flow_type); 334 335 bit_cfg = txline->fil_bits | GPIO_BIT_CFG_INT_EN; 336 337 if (flow_type & IRQ_TYPE_EDGE_BOTH) { 338 irq_set_handler_locked(d, handle_fasteoi_ack_irq); 339 bit_cfg |= GPIO_BIT_CFG_INT_TYPE; 340 } else { 341 irq_set_handler_locked(d, handle_fasteoi_mask_irq); 342 } 343 344 raw_spin_lock(&txgpio->lock); 345 if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)) { 346 bit_cfg |= GPIO_BIT_CFG_PIN_XOR; 347 set_bit(txline->line, txgpio->invert_mask); 348 } else { 349 clear_bit(txline->line, txgpio->invert_mask); 350 } 351 clear_bit(txline->line, txgpio->od_mask); 352 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(txline->line)); 353 raw_spin_unlock(&txgpio->lock); 354 355 return IRQ_SET_MASK_OK; 356 } 357 358 static void thunderx_gpio_irq_enable(struct irq_data *data) 359 { 360 irq_chip_enable_parent(data); 361 thunderx_gpio_irq_unmask(data); 362 } 363 364 static void thunderx_gpio_irq_disable(struct irq_data *data) 365 { 366 thunderx_gpio_irq_mask(data); 367 irq_chip_disable_parent(data); 368 } 369 370 /* 371 * Interrupts are chained from underlying MSI-X vectors. We have 372 * these irq_chip functions to be able to handle level triggering 373 * semantics and other acknowledgment tasks associated with the GPIO 374 * mechanism. 375 */ 376 static struct irq_chip thunderx_gpio_irq_chip = { 377 .name = "GPIO", 378 .irq_enable = thunderx_gpio_irq_enable, 379 .irq_disable = thunderx_gpio_irq_disable, 380 .irq_ack = thunderx_gpio_irq_ack, 381 .irq_mask = thunderx_gpio_irq_mask, 382 .irq_mask_ack = thunderx_gpio_irq_mask_ack, 383 .irq_unmask = thunderx_gpio_irq_unmask, 384 .irq_eoi = irq_chip_eoi_parent, 385 .irq_set_affinity = irq_chip_set_affinity_parent, 386 .irq_set_type = thunderx_gpio_irq_set_type, 387 388 .flags = IRQCHIP_SET_TYPE_MASKED 389 }; 390 391 static int thunderx_gpio_child_to_parent_hwirq(struct gpio_chip *gc, 392 unsigned int child, 393 unsigned int child_type, 394 unsigned int *parent, 395 unsigned int *parent_type) 396 { 397 struct thunderx_gpio *txgpio = gpiochip_get_data(gc); 398 399 *parent = txgpio->base_msi + (2 * child); 400 *parent_type = IRQ_TYPE_LEVEL_HIGH; 401 return 0; 402 } 403 404 static int thunderx_gpio_probe(struct pci_dev *pdev, 405 const struct pci_device_id *id) 406 { 407 void __iomem * const *tbl; 408 struct device *dev = &pdev->dev; 409 struct thunderx_gpio *txgpio; 410 struct gpio_chip *chip; 411 struct gpio_irq_chip *girq; 412 int ngpio, i; 413 int err = 0; 414 415 txgpio = devm_kzalloc(dev, sizeof(*txgpio), GFP_KERNEL); 416 if (!txgpio) 417 return -ENOMEM; 418 419 raw_spin_lock_init(&txgpio->lock); 420 chip = &txgpio->chip; 421 422 pci_set_drvdata(pdev, txgpio); 423 424 err = pcim_enable_device(pdev); 425 if (err) { 426 dev_err(dev, "Failed to enable PCI device: err %d\n", err); 427 goto out; 428 } 429 430 err = pcim_iomap_regions(pdev, 1 << 0, KBUILD_MODNAME); 431 if (err) { 432 dev_err(dev, "Failed to iomap PCI device: err %d\n", err); 433 goto out; 434 } 435 436 tbl = pcim_iomap_table(pdev); 437 txgpio->register_base = tbl[0]; 438 if (!txgpio->register_base) { 439 dev_err(dev, "Cannot map PCI resource\n"); 440 err = -ENOMEM; 441 goto out; 442 } 443 444 if (pdev->subsystem_device == 0xa10a) { 445 /* CN88XX has no GPIO_CONST register*/ 446 ngpio = 50; 447 txgpio->base_msi = 48; 448 } else { 449 u64 c = readq(txgpio->register_base + GPIO_CONST); 450 451 ngpio = c & GPIO_CONST_GPIOS_MASK; 452 txgpio->base_msi = (c >> 8) & 0xff; 453 } 454 455 txgpio->msix_entries = devm_kcalloc(dev, 456 ngpio, sizeof(struct msix_entry), 457 GFP_KERNEL); 458 if (!txgpio->msix_entries) { 459 err = -ENOMEM; 460 goto out; 461 } 462 463 txgpio->line_entries = devm_kcalloc(dev, 464 ngpio, 465 sizeof(struct thunderx_line), 466 GFP_KERNEL); 467 if (!txgpio->line_entries) { 468 err = -ENOMEM; 469 goto out; 470 } 471 472 for (i = 0; i < ngpio; i++) { 473 u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(i)); 474 475 txgpio->msix_entries[i].entry = txgpio->base_msi + (2 * i); 476 txgpio->line_entries[i].line = i; 477 txgpio->line_entries[i].txgpio = txgpio; 478 /* 479 * If something has already programmed the pin, use 480 * the existing glitch filter settings, otherwise go 481 * to 400nS. 482 */ 483 txgpio->line_entries[i].fil_bits = bit_cfg ? 484 (bit_cfg & GPIO_BIT_CFG_FIL_MASK) : GLITCH_FILTER_400NS; 485 486 if ((bit_cfg & GPIO_BIT_CFG_TX_OE) && (bit_cfg & GPIO_BIT_CFG_TX_OD)) 487 set_bit(i, txgpio->od_mask); 488 if (bit_cfg & GPIO_BIT_CFG_PIN_XOR) 489 set_bit(i, txgpio->invert_mask); 490 } 491 492 493 /* Enable all MSI-X for interrupts on all possible lines. */ 494 err = pci_enable_msix_range(pdev, txgpio->msix_entries, ngpio, ngpio); 495 if (err < 0) 496 goto out; 497 498 chip->label = KBUILD_MODNAME; 499 chip->parent = dev; 500 chip->owner = THIS_MODULE; 501 chip->request = thunderx_gpio_request; 502 chip->base = -1; /* System allocated */ 503 chip->can_sleep = false; 504 chip->ngpio = ngpio; 505 chip->get_direction = thunderx_gpio_get_direction; 506 chip->direction_input = thunderx_gpio_dir_in; 507 chip->get = thunderx_gpio_get; 508 chip->direction_output = thunderx_gpio_dir_out; 509 chip->set = thunderx_gpio_set; 510 chip->set_multiple = thunderx_gpio_set_multiple; 511 chip->set_config = thunderx_gpio_set_config; 512 girq = &chip->irq; 513 girq->chip = &thunderx_gpio_irq_chip; 514 girq->fwnode = of_node_to_fwnode(dev->of_node); 515 girq->parent_domain = 516 irq_get_irq_data(txgpio->msix_entries[0].vector)->domain; 517 girq->child_to_parent_hwirq = thunderx_gpio_child_to_parent_hwirq; 518 girq->handler = handle_bad_irq; 519 girq->default_type = IRQ_TYPE_NONE; 520 521 err = devm_gpiochip_add_data(dev, chip, txgpio); 522 if (err) 523 goto out; 524 525 /* Push on irq_data and the domain for each line. */ 526 for (i = 0; i < ngpio; i++) { 527 err = irq_domain_push_irq(chip->irq.domain, 528 txgpio->msix_entries[i].vector, 529 chip); 530 if (err < 0) 531 dev_err(dev, "irq_domain_push_irq: %d\n", err); 532 } 533 534 dev_info(dev, "ThunderX GPIO: %d lines with base %d.\n", 535 ngpio, chip->base); 536 return 0; 537 out: 538 pci_set_drvdata(pdev, NULL); 539 return err; 540 } 541 542 static void thunderx_gpio_remove(struct pci_dev *pdev) 543 { 544 int i; 545 struct thunderx_gpio *txgpio = pci_get_drvdata(pdev); 546 547 for (i = 0; i < txgpio->chip.ngpio; i++) 548 irq_domain_pop_irq(txgpio->chip.irq.domain, 549 txgpio->msix_entries[i].vector); 550 551 irq_domain_remove(txgpio->chip.irq.domain); 552 553 pci_set_drvdata(pdev, NULL); 554 } 555 556 static const struct pci_device_id thunderx_gpio_id_table[] = { 557 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 0xA00A) }, 558 { 0, } /* end of table */ 559 }; 560 561 MODULE_DEVICE_TABLE(pci, thunderx_gpio_id_table); 562 563 static struct pci_driver thunderx_gpio_driver = { 564 .name = KBUILD_MODNAME, 565 .id_table = thunderx_gpio_id_table, 566 .probe = thunderx_gpio_probe, 567 .remove = thunderx_gpio_remove, 568 }; 569 570 module_pci_driver(thunderx_gpio_driver); 571 572 MODULE_DESCRIPTION("Cavium Inc. ThunderX/OCTEON-TX GPIO Driver"); 573 MODULE_LICENSE("GPL"); 574