1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2016, 2017 Cavium Inc. 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/irq.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/pci.h> 17 #include <linux/spinlock.h> 18 19 20 #define GPIO_RX_DAT 0x0 21 #define GPIO_TX_SET 0x8 22 #define GPIO_TX_CLR 0x10 23 #define GPIO_CONST 0x90 24 #define GPIO_CONST_GPIOS_MASK 0xff 25 #define GPIO_BIT_CFG 0x400 26 #define GPIO_BIT_CFG_TX_OE BIT(0) 27 #define GPIO_BIT_CFG_PIN_XOR BIT(1) 28 #define GPIO_BIT_CFG_INT_EN BIT(2) 29 #define GPIO_BIT_CFG_INT_TYPE BIT(3) 30 #define GPIO_BIT_CFG_FIL_MASK GENMASK(11, 4) 31 #define GPIO_BIT_CFG_FIL_CNT_SHIFT 4 32 #define GPIO_BIT_CFG_FIL_SEL_SHIFT 8 33 #define GPIO_BIT_CFG_TX_OD BIT(12) 34 #define GPIO_BIT_CFG_PIN_SEL_MASK GENMASK(25, 16) 35 #define GPIO_INTR 0x800 36 #define GPIO_INTR_INTR BIT(0) 37 #define GPIO_INTR_INTR_W1S BIT(1) 38 #define GPIO_INTR_ENA_W1C BIT(2) 39 #define GPIO_INTR_ENA_W1S BIT(3) 40 #define GPIO_2ND_BANK 0x1400 41 42 #define GLITCH_FILTER_400NS ((4u << GPIO_BIT_CFG_FIL_SEL_SHIFT) | \ 43 (9u << GPIO_BIT_CFG_FIL_CNT_SHIFT)) 44 45 struct thunderx_gpio; 46 47 struct thunderx_line { 48 struct thunderx_gpio *txgpio; 49 unsigned int line; 50 unsigned int fil_bits; 51 }; 52 53 struct thunderx_gpio { 54 struct gpio_chip chip; 55 u8 __iomem *register_base; 56 struct msix_entry *msix_entries; /* per line MSI-X */ 57 struct thunderx_line *line_entries; /* per line irq info */ 58 raw_spinlock_t lock; 59 unsigned long invert_mask[2]; 60 unsigned long od_mask[2]; 61 int base_msi; 62 }; 63 64 static unsigned int bit_cfg_reg(unsigned int line) 65 { 66 return 8 * line + GPIO_BIT_CFG; 67 } 68 69 static unsigned int intr_reg(unsigned int line) 70 { 71 return 8 * line + GPIO_INTR; 72 } 73 74 static bool thunderx_gpio_is_gpio_nowarn(struct thunderx_gpio *txgpio, 75 unsigned int line) 76 { 77 u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line)); 78 79 return (bit_cfg & GPIO_BIT_CFG_PIN_SEL_MASK) == 0; 80 } 81 82 /* 83 * Check (and WARN) that the pin is available for GPIO. We will not 84 * allow modification of the state of non-GPIO pins from this driver. 85 */ 86 static bool thunderx_gpio_is_gpio(struct thunderx_gpio *txgpio, 87 unsigned int line) 88 { 89 bool rv = thunderx_gpio_is_gpio_nowarn(txgpio, line); 90 91 WARN_RATELIMIT(!rv, "Pin %d not available for GPIO\n", line); 92 93 return rv; 94 } 95 96 static int thunderx_gpio_request(struct gpio_chip *chip, unsigned int line) 97 { 98 struct thunderx_gpio *txgpio = gpiochip_get_data(chip); 99 100 return thunderx_gpio_is_gpio(txgpio, line) ? 0 : -EIO; 101 } 102 103 static int thunderx_gpio_dir_in(struct gpio_chip *chip, unsigned int line) 104 { 105 struct thunderx_gpio *txgpio = gpiochip_get_data(chip); 106 107 if (!thunderx_gpio_is_gpio(txgpio, line)) 108 return -EIO; 109 110 raw_spin_lock(&txgpio->lock); 111 clear_bit(line, txgpio->invert_mask); 112 clear_bit(line, txgpio->od_mask); 113 writeq(txgpio->line_entries[line].fil_bits, 114 txgpio->register_base + bit_cfg_reg(line)); 115 raw_spin_unlock(&txgpio->lock); 116 return 0; 117 } 118 119 static void thunderx_gpio_set(struct gpio_chip *chip, unsigned int line, 120 int value) 121 { 122 struct thunderx_gpio *txgpio = gpiochip_get_data(chip); 123 int bank = line / 64; 124 int bank_bit = line % 64; 125 126 void __iomem *reg = txgpio->register_base + 127 (bank * GPIO_2ND_BANK) + (value ? GPIO_TX_SET : GPIO_TX_CLR); 128 129 writeq(BIT_ULL(bank_bit), reg); 130 } 131 132 static int thunderx_gpio_dir_out(struct gpio_chip *chip, unsigned int line, 133 int value) 134 { 135 struct thunderx_gpio *txgpio = gpiochip_get_data(chip); 136 u64 bit_cfg = txgpio->line_entries[line].fil_bits | GPIO_BIT_CFG_TX_OE; 137 138 if (!thunderx_gpio_is_gpio(txgpio, line)) 139 return -EIO; 140 141 raw_spin_lock(&txgpio->lock); 142 143 thunderx_gpio_set(chip, line, value); 144 145 if (test_bit(line, txgpio->invert_mask)) 146 bit_cfg |= GPIO_BIT_CFG_PIN_XOR; 147 148 if (test_bit(line, txgpio->od_mask)) 149 bit_cfg |= GPIO_BIT_CFG_TX_OD; 150 151 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line)); 152 153 raw_spin_unlock(&txgpio->lock); 154 return 0; 155 } 156 157 static int thunderx_gpio_get_direction(struct gpio_chip *chip, unsigned int line) 158 { 159 struct thunderx_gpio *txgpio = gpiochip_get_data(chip); 160 u64 bit_cfg; 161 162 if (!thunderx_gpio_is_gpio_nowarn(txgpio, line)) 163 /* 164 * Say it is input for now to avoid WARNing on 165 * gpiochip_add_data(). We will WARN if someone 166 * requests it or tries to use it. 167 */ 168 return 1; 169 170 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line)); 171 172 return !(bit_cfg & GPIO_BIT_CFG_TX_OE); 173 } 174 175 static int thunderx_gpio_set_config(struct gpio_chip *chip, 176 unsigned int line, 177 unsigned long cfg) 178 { 179 bool orig_invert, orig_od, orig_dat, new_invert, new_od; 180 u32 arg, sel; 181 u64 bit_cfg; 182 int bank = line / 64; 183 int bank_bit = line % 64; 184 int ret = -ENOTSUPP; 185 struct thunderx_gpio *txgpio = gpiochip_get_data(chip); 186 void __iomem *reg = txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET; 187 188 if (!thunderx_gpio_is_gpio(txgpio, line)) 189 return -EIO; 190 191 raw_spin_lock(&txgpio->lock); 192 orig_invert = test_bit(line, txgpio->invert_mask); 193 new_invert = orig_invert; 194 orig_od = test_bit(line, txgpio->od_mask); 195 new_od = orig_od; 196 orig_dat = ((readq(reg) >> bank_bit) & 1) ^ orig_invert; 197 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line)); 198 switch (pinconf_to_config_param(cfg)) { 199 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 200 /* 201 * Weird, setting open-drain mode causes signal 202 * inversion. Note this so we can compensate in the 203 * dir_out function. 204 */ 205 set_bit(line, txgpio->invert_mask); 206 new_invert = true; 207 set_bit(line, txgpio->od_mask); 208 new_od = true; 209 ret = 0; 210 break; 211 case PIN_CONFIG_DRIVE_PUSH_PULL: 212 clear_bit(line, txgpio->invert_mask); 213 new_invert = false; 214 clear_bit(line, txgpio->od_mask); 215 new_od = false; 216 ret = 0; 217 break; 218 case PIN_CONFIG_INPUT_DEBOUNCE: 219 arg = pinconf_to_config_argument(cfg); 220 if (arg > 1228) { /* 15 * 2^15 * 2.5nS maximum */ 221 ret = -EINVAL; 222 break; 223 } 224 arg *= 400; /* scale to 2.5nS clocks. */ 225 sel = 0; 226 while (arg > 15) { 227 sel++; 228 arg++; /* always round up */ 229 arg >>= 1; 230 } 231 txgpio->line_entries[line].fil_bits = 232 (sel << GPIO_BIT_CFG_FIL_SEL_SHIFT) | 233 (arg << GPIO_BIT_CFG_FIL_CNT_SHIFT); 234 bit_cfg &= ~GPIO_BIT_CFG_FIL_MASK; 235 bit_cfg |= txgpio->line_entries[line].fil_bits; 236 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line)); 237 ret = 0; 238 break; 239 default: 240 break; 241 } 242 raw_spin_unlock(&txgpio->lock); 243 244 /* 245 * If currently output and OPEN_DRAIN changed, install the new 246 * settings 247 */ 248 if ((new_invert != orig_invert || new_od != orig_od) && 249 (bit_cfg & GPIO_BIT_CFG_TX_OE)) 250 ret = thunderx_gpio_dir_out(chip, line, orig_dat ^ new_invert); 251 252 return ret; 253 } 254 255 static int thunderx_gpio_get(struct gpio_chip *chip, unsigned int line) 256 { 257 struct thunderx_gpio *txgpio = gpiochip_get_data(chip); 258 int bank = line / 64; 259 int bank_bit = line % 64; 260 u64 read_bits = readq(txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_RX_DAT); 261 u64 masked_bits = read_bits & BIT_ULL(bank_bit); 262 263 if (test_bit(line, txgpio->invert_mask)) 264 return masked_bits == 0; 265 else 266 return masked_bits != 0; 267 } 268 269 static void thunderx_gpio_set_multiple(struct gpio_chip *chip, 270 unsigned long *mask, 271 unsigned long *bits) 272 { 273 int bank; 274 u64 set_bits, clear_bits; 275 struct thunderx_gpio *txgpio = gpiochip_get_data(chip); 276 277 for (bank = 0; bank <= chip->ngpio / 64; bank++) { 278 set_bits = bits[bank] & mask[bank]; 279 clear_bits = ~bits[bank] & mask[bank]; 280 writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET); 281 writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR); 282 } 283 } 284 285 static void thunderx_gpio_irq_ack(struct irq_data *d) 286 { 287 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 288 struct thunderx_gpio *txgpio = gpiochip_get_data(gc); 289 290 writeq(GPIO_INTR_INTR, 291 txgpio->register_base + intr_reg(irqd_to_hwirq(d))); 292 } 293 294 static void thunderx_gpio_irq_mask(struct irq_data *d) 295 { 296 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 297 struct thunderx_gpio *txgpio = gpiochip_get_data(gc); 298 299 writeq(GPIO_INTR_ENA_W1C, 300 txgpio->register_base + intr_reg(irqd_to_hwirq(d))); 301 } 302 303 static void thunderx_gpio_irq_mask_ack(struct irq_data *d) 304 { 305 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 306 struct thunderx_gpio *txgpio = gpiochip_get_data(gc); 307 308 writeq(GPIO_INTR_ENA_W1C | GPIO_INTR_INTR, 309 txgpio->register_base + intr_reg(irqd_to_hwirq(d))); 310 } 311 312 static void thunderx_gpio_irq_unmask(struct irq_data *d) 313 { 314 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 315 struct thunderx_gpio *txgpio = gpiochip_get_data(gc); 316 317 writeq(GPIO_INTR_ENA_W1S, 318 txgpio->register_base + intr_reg(irqd_to_hwirq(d))); 319 } 320 321 static int thunderx_gpio_irq_set_type(struct irq_data *d, 322 unsigned int flow_type) 323 { 324 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 325 struct thunderx_gpio *txgpio = gpiochip_get_data(gc); 326 struct thunderx_line *txline = 327 &txgpio->line_entries[irqd_to_hwirq(d)]; 328 u64 bit_cfg; 329 330 irqd_set_trigger_type(d, flow_type); 331 332 bit_cfg = txline->fil_bits | GPIO_BIT_CFG_INT_EN; 333 334 if (flow_type & IRQ_TYPE_EDGE_BOTH) { 335 irq_set_handler_locked(d, handle_fasteoi_ack_irq); 336 bit_cfg |= GPIO_BIT_CFG_INT_TYPE; 337 } else { 338 irq_set_handler_locked(d, handle_fasteoi_mask_irq); 339 } 340 341 raw_spin_lock(&txgpio->lock); 342 if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)) { 343 bit_cfg |= GPIO_BIT_CFG_PIN_XOR; 344 set_bit(txline->line, txgpio->invert_mask); 345 } else { 346 clear_bit(txline->line, txgpio->invert_mask); 347 } 348 clear_bit(txline->line, txgpio->od_mask); 349 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(txline->line)); 350 raw_spin_unlock(&txgpio->lock); 351 352 return IRQ_SET_MASK_OK; 353 } 354 355 static void thunderx_gpio_irq_enable(struct irq_data *data) 356 { 357 irq_chip_enable_parent(data); 358 thunderx_gpio_irq_unmask(data); 359 } 360 361 static void thunderx_gpio_irq_disable(struct irq_data *data) 362 { 363 thunderx_gpio_irq_mask(data); 364 irq_chip_disable_parent(data); 365 } 366 367 /* 368 * Interrupts are chained from underlying MSI-X vectors. We have 369 * these irq_chip functions to be able to handle level triggering 370 * semantics and other acknowledgment tasks associated with the GPIO 371 * mechanism. 372 */ 373 static struct irq_chip thunderx_gpio_irq_chip = { 374 .name = "GPIO", 375 .irq_enable = thunderx_gpio_irq_enable, 376 .irq_disable = thunderx_gpio_irq_disable, 377 .irq_ack = thunderx_gpio_irq_ack, 378 .irq_mask = thunderx_gpio_irq_mask, 379 .irq_mask_ack = thunderx_gpio_irq_mask_ack, 380 .irq_unmask = thunderx_gpio_irq_unmask, 381 .irq_eoi = irq_chip_eoi_parent, 382 .irq_set_affinity = irq_chip_set_affinity_parent, 383 .irq_set_type = thunderx_gpio_irq_set_type, 384 385 .flags = IRQCHIP_SET_TYPE_MASKED 386 }; 387 388 static int thunderx_gpio_child_to_parent_hwirq(struct gpio_chip *gc, 389 unsigned int child, 390 unsigned int child_type, 391 unsigned int *parent, 392 unsigned int *parent_type) 393 { 394 struct thunderx_gpio *txgpio = gpiochip_get_data(gc); 395 396 *parent = txgpio->base_msi + (2 * child); 397 *parent_type = IRQ_TYPE_LEVEL_HIGH; 398 return 0; 399 } 400 401 static int thunderx_gpio_probe(struct pci_dev *pdev, 402 const struct pci_device_id *id) 403 { 404 void __iomem * const *tbl; 405 struct device *dev = &pdev->dev; 406 struct thunderx_gpio *txgpio; 407 struct gpio_chip *chip; 408 struct gpio_irq_chip *girq; 409 int ngpio, i; 410 int err = 0; 411 412 txgpio = devm_kzalloc(dev, sizeof(*txgpio), GFP_KERNEL); 413 if (!txgpio) 414 return -ENOMEM; 415 416 raw_spin_lock_init(&txgpio->lock); 417 chip = &txgpio->chip; 418 419 pci_set_drvdata(pdev, txgpio); 420 421 err = pcim_enable_device(pdev); 422 if (err) { 423 dev_err(dev, "Failed to enable PCI device: err %d\n", err); 424 goto out; 425 } 426 427 err = pcim_iomap_regions(pdev, 1 << 0, KBUILD_MODNAME); 428 if (err) { 429 dev_err(dev, "Failed to iomap PCI device: err %d\n", err); 430 goto out; 431 } 432 433 tbl = pcim_iomap_table(pdev); 434 txgpio->register_base = tbl[0]; 435 if (!txgpio->register_base) { 436 dev_err(dev, "Cannot map PCI resource\n"); 437 err = -ENOMEM; 438 goto out; 439 } 440 441 if (pdev->subsystem_device == 0xa10a) { 442 /* CN88XX has no GPIO_CONST register*/ 443 ngpio = 50; 444 txgpio->base_msi = 48; 445 } else { 446 u64 c = readq(txgpio->register_base + GPIO_CONST); 447 448 ngpio = c & GPIO_CONST_GPIOS_MASK; 449 txgpio->base_msi = (c >> 8) & 0xff; 450 } 451 452 txgpio->msix_entries = devm_kcalloc(dev, 453 ngpio, sizeof(struct msix_entry), 454 GFP_KERNEL); 455 if (!txgpio->msix_entries) { 456 err = -ENOMEM; 457 goto out; 458 } 459 460 txgpio->line_entries = devm_kcalloc(dev, 461 ngpio, 462 sizeof(struct thunderx_line), 463 GFP_KERNEL); 464 if (!txgpio->line_entries) { 465 err = -ENOMEM; 466 goto out; 467 } 468 469 for (i = 0; i < ngpio; i++) { 470 u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(i)); 471 472 txgpio->msix_entries[i].entry = txgpio->base_msi + (2 * i); 473 txgpio->line_entries[i].line = i; 474 txgpio->line_entries[i].txgpio = txgpio; 475 /* 476 * If something has already programmed the pin, use 477 * the existing glitch filter settings, otherwise go 478 * to 400nS. 479 */ 480 txgpio->line_entries[i].fil_bits = bit_cfg ? 481 (bit_cfg & GPIO_BIT_CFG_FIL_MASK) : GLITCH_FILTER_400NS; 482 483 if ((bit_cfg & GPIO_BIT_CFG_TX_OE) && (bit_cfg & GPIO_BIT_CFG_TX_OD)) 484 set_bit(i, txgpio->od_mask); 485 if (bit_cfg & GPIO_BIT_CFG_PIN_XOR) 486 set_bit(i, txgpio->invert_mask); 487 } 488 489 490 /* Enable all MSI-X for interrupts on all possible lines. */ 491 err = pci_enable_msix_range(pdev, txgpio->msix_entries, ngpio, ngpio); 492 if (err < 0) 493 goto out; 494 495 chip->label = KBUILD_MODNAME; 496 chip->parent = dev; 497 chip->owner = THIS_MODULE; 498 chip->request = thunderx_gpio_request; 499 chip->base = -1; /* System allocated */ 500 chip->can_sleep = false; 501 chip->ngpio = ngpio; 502 chip->get_direction = thunderx_gpio_get_direction; 503 chip->direction_input = thunderx_gpio_dir_in; 504 chip->get = thunderx_gpio_get; 505 chip->direction_output = thunderx_gpio_dir_out; 506 chip->set = thunderx_gpio_set; 507 chip->set_multiple = thunderx_gpio_set_multiple; 508 chip->set_config = thunderx_gpio_set_config; 509 girq = &chip->irq; 510 girq->chip = &thunderx_gpio_irq_chip; 511 girq->fwnode = of_node_to_fwnode(dev->of_node); 512 girq->parent_domain = 513 irq_get_irq_data(txgpio->msix_entries[0].vector)->domain; 514 girq->child_to_parent_hwirq = thunderx_gpio_child_to_parent_hwirq; 515 girq->handler = handle_bad_irq; 516 girq->default_type = IRQ_TYPE_NONE; 517 518 err = devm_gpiochip_add_data(dev, chip, txgpio); 519 if (err) 520 goto out; 521 522 /* Push on irq_data and the domain for each line. */ 523 for (i = 0; i < ngpio; i++) { 524 err = irq_domain_push_irq(chip->irq.domain, 525 txgpio->msix_entries[i].vector, 526 chip); 527 if (err < 0) 528 dev_err(dev, "irq_domain_push_irq: %d\n", err); 529 } 530 531 dev_info(dev, "ThunderX GPIO: %d lines with base %d.\n", 532 ngpio, chip->base); 533 return 0; 534 out: 535 pci_set_drvdata(pdev, NULL); 536 return err; 537 } 538 539 static void thunderx_gpio_remove(struct pci_dev *pdev) 540 { 541 int i; 542 struct thunderx_gpio *txgpio = pci_get_drvdata(pdev); 543 544 for (i = 0; i < txgpio->chip.ngpio; i++) 545 irq_domain_pop_irq(txgpio->chip.irq.domain, 546 txgpio->msix_entries[i].vector); 547 548 irq_domain_remove(txgpio->chip.irq.domain); 549 550 pci_set_drvdata(pdev, NULL); 551 } 552 553 static const struct pci_device_id thunderx_gpio_id_table[] = { 554 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 0xA00A) }, 555 { 0, } /* end of table */ 556 }; 557 558 MODULE_DEVICE_TABLE(pci, thunderx_gpio_id_table); 559 560 static struct pci_driver thunderx_gpio_driver = { 561 .name = KBUILD_MODNAME, 562 .id_table = thunderx_gpio_id_table, 563 .probe = thunderx_gpio_probe, 564 .remove = thunderx_gpio_remove, 565 }; 566 567 module_pci_driver(thunderx_gpio_driver); 568 569 MODULE_DESCRIPTION("Cavium Inc. ThunderX/OCTEON-TX GPIO Driver"); 570 MODULE_LICENSE("GPL"); 571