1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016-2017 NVIDIA Corporation 4 * 5 * Author: Thierry Reding <treding@nvidia.com> 6 */ 7 8 #include <linux/gpio/driver.h> 9 #include <linux/interrupt.h> 10 #include <linux/irq.h> 11 #include <linux/module.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 15 #include <dt-bindings/gpio/tegra186-gpio.h> 16 #include <dt-bindings/gpio/tegra194-gpio.h> 17 #include <dt-bindings/gpio/tegra234-gpio.h> 18 #include <dt-bindings/gpio/tegra241-gpio.h> 19 20 /* security registers */ 21 #define TEGRA186_GPIO_CTL_SCR 0x0c 22 #define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28) 23 #define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27) 24 25 #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4) 26 27 /* control registers */ 28 #define TEGRA186_GPIO_ENABLE_CONFIG 0x00 29 #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0) 30 #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1) 31 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2) 32 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2) 33 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2) 34 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2) 35 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2) 36 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4) 37 #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5) 38 #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6) 39 40 #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04 41 #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff) 42 43 #define TEGRA186_GPIO_INPUT 0x08 44 #define TEGRA186_GPIO_INPUT_HIGH BIT(0) 45 46 #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c 47 #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0) 48 49 #define TEGRA186_GPIO_OUTPUT_VALUE 0x10 50 #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0) 51 52 #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14 53 54 #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4) 55 56 struct tegra_gpio_port { 57 const char *name; 58 unsigned int bank; 59 unsigned int port; 60 unsigned int pins; 61 }; 62 63 struct tegra186_pin_range { 64 unsigned int offset; 65 const char *group; 66 }; 67 68 struct tegra_gpio_soc { 69 const struct tegra_gpio_port *ports; 70 unsigned int num_ports; 71 const char *name; 72 unsigned int instance; 73 74 unsigned int num_irqs_per_bank; 75 76 const struct tegra186_pin_range *pin_ranges; 77 unsigned int num_pin_ranges; 78 const char *pinmux; 79 }; 80 81 struct tegra_gpio { 82 struct gpio_chip gpio; 83 struct irq_chip intc; 84 unsigned int num_irq; 85 unsigned int *irq; 86 87 const struct tegra_gpio_soc *soc; 88 unsigned int num_irqs_per_bank; 89 unsigned int num_banks; 90 91 void __iomem *secure; 92 void __iomem *base; 93 }; 94 95 static const struct tegra_gpio_port * 96 tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin) 97 { 98 unsigned int start = 0, i; 99 100 for (i = 0; i < gpio->soc->num_ports; i++) { 101 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 102 103 if (*pin >= start && *pin < start + port->pins) { 104 *pin -= start; 105 return port; 106 } 107 108 start += port->pins; 109 } 110 111 return NULL; 112 } 113 114 static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio, 115 unsigned int pin) 116 { 117 const struct tegra_gpio_port *port; 118 unsigned int offset; 119 120 port = tegra186_gpio_get_port(gpio, &pin); 121 if (!port) 122 return NULL; 123 124 offset = port->bank * 0x1000 + port->port * 0x200; 125 126 return gpio->base + offset + pin * 0x20; 127 } 128 129 static int tegra186_gpio_get_direction(struct gpio_chip *chip, 130 unsigned int offset) 131 { 132 struct tegra_gpio *gpio = gpiochip_get_data(chip); 133 void __iomem *base; 134 u32 value; 135 136 base = tegra186_gpio_get_base(gpio, offset); 137 if (WARN_ON(base == NULL)) 138 return -ENODEV; 139 140 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 141 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) 142 return GPIO_LINE_DIRECTION_OUT; 143 144 return GPIO_LINE_DIRECTION_IN; 145 } 146 147 static int tegra186_gpio_direction_input(struct gpio_chip *chip, 148 unsigned int offset) 149 { 150 struct tegra_gpio *gpio = gpiochip_get_data(chip); 151 void __iomem *base; 152 u32 value; 153 154 base = tegra186_gpio_get_base(gpio, offset); 155 if (WARN_ON(base == NULL)) 156 return -ENODEV; 157 158 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); 159 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; 160 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); 161 162 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 163 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; 164 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT; 165 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 166 167 return 0; 168 } 169 170 static int tegra186_gpio_direction_output(struct gpio_chip *chip, 171 unsigned int offset, int level) 172 { 173 struct tegra_gpio *gpio = gpiochip_get_data(chip); 174 void __iomem *base; 175 u32 value; 176 177 /* configure output level first */ 178 chip->set(chip, offset, level); 179 180 base = tegra186_gpio_get_base(gpio, offset); 181 if (WARN_ON(base == NULL)) 182 return -EINVAL; 183 184 /* set the direction */ 185 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); 186 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; 187 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); 188 189 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 190 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; 191 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT; 192 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 193 194 return 0; 195 } 196 197 static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset) 198 { 199 struct tegra_gpio *gpio = gpiochip_get_data(chip); 200 void __iomem *base; 201 u32 value; 202 203 base = tegra186_gpio_get_base(gpio, offset); 204 if (WARN_ON(base == NULL)) 205 return -ENODEV; 206 207 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 208 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) 209 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); 210 else 211 value = readl(base + TEGRA186_GPIO_INPUT); 212 213 return value & BIT(0); 214 } 215 216 static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset, 217 int level) 218 { 219 struct tegra_gpio *gpio = gpiochip_get_data(chip); 220 void __iomem *base; 221 u32 value; 222 223 base = tegra186_gpio_get_base(gpio, offset); 224 if (WARN_ON(base == NULL)) 225 return; 226 227 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); 228 if (level == 0) 229 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH; 230 else 231 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH; 232 233 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE); 234 } 235 236 static int tegra186_gpio_set_config(struct gpio_chip *chip, 237 unsigned int offset, 238 unsigned long config) 239 { 240 struct tegra_gpio *gpio = gpiochip_get_data(chip); 241 u32 debounce, value; 242 void __iomem *base; 243 244 base = tegra186_gpio_get_base(gpio, offset); 245 if (base == NULL) 246 return -ENXIO; 247 248 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 249 return -ENOTSUPP; 250 251 debounce = pinconf_to_config_argument(config); 252 253 /* 254 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce 255 * time. 256 */ 257 if (debounce > 255000) 258 return -EINVAL; 259 260 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC); 261 262 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce); 263 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL); 264 265 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 266 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE; 267 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 268 269 return 0; 270 } 271 272 static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip) 273 { 274 struct tegra_gpio *gpio = gpiochip_get_data(chip); 275 struct pinctrl_dev *pctldev; 276 struct device_node *np; 277 unsigned int i, j; 278 int err; 279 280 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0) 281 return 0; 282 283 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux); 284 if (!np) 285 return -ENODEV; 286 287 pctldev = of_pinctrl_get(np); 288 of_node_put(np); 289 if (!pctldev) 290 return -EPROBE_DEFER; 291 292 for (i = 0; i < gpio->soc->num_pin_ranges; i++) { 293 unsigned int pin = gpio->soc->pin_ranges[i].offset, port; 294 const char *group = gpio->soc->pin_ranges[i].group; 295 296 port = pin / 8; 297 pin = pin % 8; 298 299 if (port >= gpio->soc->num_ports) { 300 dev_warn(chip->parent, "invalid port %u for %s\n", 301 port, group); 302 continue; 303 } 304 305 for (j = 0; j < port; j++) 306 pin += gpio->soc->ports[j].pins; 307 308 err = gpiochip_add_pingroup_range(chip, pctldev, pin, group); 309 if (err < 0) 310 return err; 311 } 312 313 return 0; 314 } 315 316 static int tegra186_gpio_of_xlate(struct gpio_chip *chip, 317 const struct of_phandle_args *spec, 318 u32 *flags) 319 { 320 struct tegra_gpio *gpio = gpiochip_get_data(chip); 321 unsigned int port, pin, i, offset = 0; 322 323 if (WARN_ON(chip->of_gpio_n_cells < 2)) 324 return -EINVAL; 325 326 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells)) 327 return -EINVAL; 328 329 port = spec->args[0] / 8; 330 pin = spec->args[0] % 8; 331 332 if (port >= gpio->soc->num_ports) { 333 dev_err(chip->parent, "invalid port number: %u\n", port); 334 return -EINVAL; 335 } 336 337 for (i = 0; i < port; i++) 338 offset += gpio->soc->ports[i].pins; 339 340 if (flags) 341 *flags = spec->args[1]; 342 343 return offset + pin; 344 } 345 346 static void tegra186_irq_ack(struct irq_data *data) 347 { 348 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); 349 void __iomem *base; 350 351 base = tegra186_gpio_get_base(gpio, data->hwirq); 352 if (WARN_ON(base == NULL)) 353 return; 354 355 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR); 356 } 357 358 static void tegra186_irq_mask(struct irq_data *data) 359 { 360 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); 361 void __iomem *base; 362 u32 value; 363 364 base = tegra186_gpio_get_base(gpio, data->hwirq); 365 if (WARN_ON(base == NULL)) 366 return; 367 368 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 369 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; 370 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 371 } 372 373 static void tegra186_irq_unmask(struct irq_data *data) 374 { 375 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); 376 void __iomem *base; 377 u32 value; 378 379 base = tegra186_gpio_get_base(gpio, data->hwirq); 380 if (WARN_ON(base == NULL)) 381 return; 382 383 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 384 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; 385 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 386 } 387 388 static int tegra186_irq_set_type(struct irq_data *data, unsigned int type) 389 { 390 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); 391 void __iomem *base; 392 u32 value; 393 394 base = tegra186_gpio_get_base(gpio, data->hwirq); 395 if (WARN_ON(base == NULL)) 396 return -ENODEV; 397 398 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 399 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK; 400 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 401 402 switch (type & IRQ_TYPE_SENSE_MASK) { 403 case IRQ_TYPE_NONE: 404 break; 405 406 case IRQ_TYPE_EDGE_RISING: 407 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 408 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 409 break; 410 411 case IRQ_TYPE_EDGE_FALLING: 412 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 413 break; 414 415 case IRQ_TYPE_EDGE_BOTH: 416 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; 417 break; 418 419 case IRQ_TYPE_LEVEL_HIGH: 420 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; 421 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 422 break; 423 424 case IRQ_TYPE_LEVEL_LOW: 425 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; 426 break; 427 428 default: 429 return -EINVAL; 430 } 431 432 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 433 434 if ((type & IRQ_TYPE_EDGE_BOTH) == 0) 435 irq_set_handler_locked(data, handle_level_irq); 436 else 437 irq_set_handler_locked(data, handle_edge_irq); 438 439 if (data->parent_data) 440 return irq_chip_set_type_parent(data, type); 441 442 return 0; 443 } 444 445 static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on) 446 { 447 if (data->parent_data) 448 return irq_chip_set_wake_parent(data, on); 449 450 return 0; 451 } 452 453 static void tegra186_gpio_irq(struct irq_desc *desc) 454 { 455 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc); 456 struct irq_domain *domain = gpio->gpio.irq.domain; 457 struct irq_chip *chip = irq_desc_get_chip(desc); 458 unsigned int parent = irq_desc_get_irq(desc); 459 unsigned int i, j, offset = 0; 460 461 chained_irq_enter(chip, desc); 462 463 for (i = 0; i < gpio->soc->num_ports; i++) { 464 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 465 unsigned int pin; 466 unsigned long value; 467 void __iomem *base; 468 469 base = gpio->base + port->bank * 0x1000 + port->port * 0x200; 470 471 /* skip ports that are not associated with this bank */ 472 for (j = 0; j < gpio->num_irqs_per_bank; j++) { 473 if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j]) 474 break; 475 } 476 477 if (j == gpio->num_irqs_per_bank) 478 goto skip; 479 480 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1)); 481 482 for_each_set_bit(pin, &value, port->pins) { 483 int ret = generic_handle_domain_irq(domain, offset + pin); 484 WARN_RATELIMIT(ret, "hwirq = %d", offset + pin); 485 } 486 487 skip: 488 offset += port->pins; 489 } 490 491 chained_irq_exit(chip, desc); 492 } 493 494 static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain, 495 struct irq_fwspec *fwspec, 496 unsigned long *hwirq, 497 unsigned int *type) 498 { 499 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data); 500 unsigned int port, pin, i, offset = 0; 501 502 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2)) 503 return -EINVAL; 504 505 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells)) 506 return -EINVAL; 507 508 port = fwspec->param[0] / 8; 509 pin = fwspec->param[0] % 8; 510 511 if (port >= gpio->soc->num_ports) 512 return -EINVAL; 513 514 for (i = 0; i < port; i++) 515 offset += gpio->soc->ports[i].pins; 516 517 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; 518 *hwirq = offset + pin; 519 520 return 0; 521 } 522 523 static void *tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip, 524 unsigned int parent_hwirq, 525 unsigned int parent_type) 526 { 527 struct tegra_gpio *gpio = gpiochip_get_data(chip); 528 struct irq_fwspec *fwspec; 529 530 fwspec = kmalloc(sizeof(*fwspec), GFP_KERNEL); 531 if (!fwspec) 532 return NULL; 533 534 fwspec->fwnode = chip->irq.parent_domain->fwnode; 535 fwspec->param_count = 3; 536 fwspec->param[0] = gpio->soc->instance; 537 fwspec->param[1] = parent_hwirq; 538 fwspec->param[2] = parent_type; 539 540 return fwspec; 541 } 542 543 static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip, 544 unsigned int hwirq, 545 unsigned int type, 546 unsigned int *parent_hwirq, 547 unsigned int *parent_type) 548 { 549 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq); 550 *parent_type = type; 551 552 return 0; 553 } 554 555 static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip, 556 unsigned int offset) 557 { 558 struct tegra_gpio *gpio = gpiochip_get_data(chip); 559 unsigned int i; 560 561 for (i = 0; i < gpio->soc->num_ports; i++) { 562 if (offset < gpio->soc->ports[i].pins) 563 break; 564 565 offset -= gpio->soc->ports[i].pins; 566 } 567 568 return offset + i * 8; 569 } 570 571 static const struct of_device_id tegra186_pmc_of_match[] = { 572 { .compatible = "nvidia,tegra186-pmc" }, 573 { .compatible = "nvidia,tegra194-pmc" }, 574 { /* sentinel */ } 575 }; 576 577 static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio) 578 { 579 struct device *dev = gpio->gpio.parent; 580 unsigned int i, j; 581 u32 value; 582 583 for (i = 0; i < gpio->soc->num_ports; i++) { 584 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 585 unsigned int offset, p = port->port; 586 void __iomem *base; 587 588 base = gpio->secure + port->bank * 0x1000 + 0x800; 589 590 value = readl(base + TEGRA186_GPIO_CTL_SCR); 591 592 /* 593 * For controllers that haven't been locked down yet, make 594 * sure to program the default interrupt route mapping. 595 */ 596 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 && 597 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) { 598 /* 599 * On Tegra194 and later, each pin can be routed to one or more 600 * interrupts. 601 */ 602 for (j = 0; j < gpio->num_irqs_per_bank; j++) { 603 dev_dbg(dev, "programming default interrupt routing for port %s\n", 604 port->name); 605 606 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, j); 607 608 /* 609 * By default we only want to route GPIO pins to IRQ 0. This works 610 * only under the assumption that we're running as the host kernel 611 * and hence all GPIO pins are owned by Linux. 612 * 613 * For cases where Linux is the guest OS, the hypervisor will have 614 * to configure the interrupt routing and pass only the valid 615 * interrupts via device tree. 616 */ 617 if (j == 0) { 618 value = readl(base + offset); 619 value = BIT(port->pins) - 1; 620 writel(value, base + offset); 621 } 622 } 623 } 624 } 625 } 626 627 static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio) 628 { 629 struct device *dev = gpio->gpio.parent; 630 631 if (gpio->num_irq > gpio->num_banks) { 632 if (gpio->num_irq % gpio->num_banks != 0) 633 goto error; 634 } 635 636 if (gpio->num_irq < gpio->num_banks) 637 goto error; 638 639 gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks; 640 641 if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank) 642 goto error; 643 644 return 0; 645 646 error: 647 dev_err(dev, "invalid number of interrupts (%u) for %u banks\n", 648 gpio->num_irq, gpio->num_banks); 649 return -EINVAL; 650 } 651 652 static int tegra186_gpio_probe(struct platform_device *pdev) 653 { 654 unsigned int i, j, offset; 655 struct gpio_irq_chip *irq; 656 struct tegra_gpio *gpio; 657 struct device_node *np; 658 char **names; 659 int err; 660 661 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 662 if (!gpio) 663 return -ENOMEM; 664 665 gpio->soc = device_get_match_data(&pdev->dev); 666 gpio->gpio.label = gpio->soc->name; 667 gpio->gpio.parent = &pdev->dev; 668 669 /* count the number of banks in the controller */ 670 for (i = 0; i < gpio->soc->num_ports; i++) 671 if (gpio->soc->ports[i].bank > gpio->num_banks) 672 gpio->num_banks = gpio->soc->ports[i].bank; 673 674 gpio->num_banks++; 675 676 /* get register apertures */ 677 gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security"); 678 if (IS_ERR(gpio->secure)) { 679 gpio->secure = devm_platform_ioremap_resource(pdev, 0); 680 if (IS_ERR(gpio->secure)) 681 return PTR_ERR(gpio->secure); 682 } 683 684 gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio"); 685 if (IS_ERR(gpio->base)) { 686 gpio->base = devm_platform_ioremap_resource(pdev, 1); 687 if (IS_ERR(gpio->base)) 688 return PTR_ERR(gpio->base); 689 } 690 691 err = platform_irq_count(pdev); 692 if (err < 0) 693 return err; 694 695 gpio->num_irq = err; 696 697 err = tegra186_gpio_irqs_per_bank(gpio); 698 if (err < 0) 699 return err; 700 701 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq), 702 GFP_KERNEL); 703 if (!gpio->irq) 704 return -ENOMEM; 705 706 for (i = 0; i < gpio->num_irq; i++) { 707 err = platform_get_irq(pdev, i); 708 if (err < 0) 709 return err; 710 711 gpio->irq[i] = err; 712 } 713 714 gpio->gpio.request = gpiochip_generic_request; 715 gpio->gpio.free = gpiochip_generic_free; 716 gpio->gpio.get_direction = tegra186_gpio_get_direction; 717 gpio->gpio.direction_input = tegra186_gpio_direction_input; 718 gpio->gpio.direction_output = tegra186_gpio_direction_output; 719 gpio->gpio.get = tegra186_gpio_get; 720 gpio->gpio.set = tegra186_gpio_set; 721 gpio->gpio.set_config = tegra186_gpio_set_config; 722 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges; 723 724 gpio->gpio.base = -1; 725 726 for (i = 0; i < gpio->soc->num_ports; i++) 727 gpio->gpio.ngpio += gpio->soc->ports[i].pins; 728 729 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio, 730 sizeof(*names), GFP_KERNEL); 731 if (!names) 732 return -ENOMEM; 733 734 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { 735 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 736 char *name; 737 738 for (j = 0; j < port->pins; j++) { 739 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL, 740 "P%s.%02x", port->name, j); 741 if (!name) 742 return -ENOMEM; 743 744 names[offset + j] = name; 745 } 746 747 offset += port->pins; 748 } 749 750 gpio->gpio.names = (const char * const *)names; 751 752 #if defined(CONFIG_OF_GPIO) 753 gpio->gpio.of_gpio_n_cells = 2; 754 gpio->gpio.of_xlate = tegra186_gpio_of_xlate; 755 #endif /* CONFIG_OF_GPIO */ 756 757 gpio->intc.name = dev_name(&pdev->dev); 758 gpio->intc.irq_ack = tegra186_irq_ack; 759 gpio->intc.irq_mask = tegra186_irq_mask; 760 gpio->intc.irq_unmask = tegra186_irq_unmask; 761 gpio->intc.irq_set_type = tegra186_irq_set_type; 762 gpio->intc.irq_set_wake = tegra186_irq_set_wake; 763 764 irq = &gpio->gpio.irq; 765 irq->chip = &gpio->intc; 766 irq->fwnode = of_node_to_fwnode(pdev->dev.of_node); 767 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq; 768 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec; 769 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq; 770 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate; 771 irq->handler = handle_simple_irq; 772 irq->default_type = IRQ_TYPE_NONE; 773 irq->parent_handler = tegra186_gpio_irq; 774 irq->parent_handler_data = gpio; 775 irq->num_parents = gpio->num_irq; 776 777 /* 778 * To simplify things, use a single interrupt per bank for now. Some 779 * chips support up to 8 interrupts per bank, which can be useful to 780 * distribute the load and decrease the processing latency for GPIOs 781 * but it also requires a more complicated interrupt routing than we 782 * currently program. 783 */ 784 if (gpio->num_irqs_per_bank > 1) { 785 irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks, 786 sizeof(*irq->parents), GFP_KERNEL); 787 if (!irq->parents) 788 return -ENOMEM; 789 790 for (i = 0; i < gpio->num_banks; i++) 791 irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank]; 792 793 irq->num_parents = gpio->num_banks; 794 } else { 795 irq->num_parents = gpio->num_irq; 796 irq->parents = gpio->irq; 797 } 798 799 if (gpio->soc->num_irqs_per_bank > 1) 800 tegra186_gpio_init_route_mapping(gpio); 801 802 np = of_find_matching_node(NULL, tegra186_pmc_of_match); 803 if (np) { 804 irq->parent_domain = irq_find_host(np); 805 of_node_put(np); 806 807 if (!irq->parent_domain) 808 return -EPROBE_DEFER; 809 } 810 811 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio, 812 sizeof(*irq->map), GFP_KERNEL); 813 if (!irq->map) 814 return -ENOMEM; 815 816 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { 817 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 818 819 for (j = 0; j < port->pins; j++) 820 irq->map[offset + j] = irq->parents[port->bank]; 821 822 offset += port->pins; 823 } 824 825 return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio); 826 } 827 828 #define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 829 [TEGRA186_MAIN_GPIO_PORT_##_name] = { \ 830 .name = #_name, \ 831 .bank = _bank, \ 832 .port = _port, \ 833 .pins = _pins, \ 834 } 835 836 static const struct tegra_gpio_port tegra186_main_ports[] = { 837 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7), 838 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7), 839 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7), 840 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6), 841 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8), 842 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6), 843 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6), 844 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7), 845 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8), 846 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8), 847 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1), 848 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8), 849 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6), 850 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7), 851 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4), 852 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7), 853 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6), 854 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6), 855 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4), 856 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8), 857 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7), 858 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2), 859 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4), 860 }; 861 862 static const struct tegra_gpio_soc tegra186_main_soc = { 863 .num_ports = ARRAY_SIZE(tegra186_main_ports), 864 .ports = tegra186_main_ports, 865 .name = "tegra186-gpio", 866 .instance = 0, 867 .num_irqs_per_bank = 1, 868 }; 869 870 #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 871 [TEGRA186_AON_GPIO_PORT_##_name] = { \ 872 .name = #_name, \ 873 .bank = _bank, \ 874 .port = _port, \ 875 .pins = _pins, \ 876 } 877 878 static const struct tegra_gpio_port tegra186_aon_ports[] = { 879 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5), 880 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6), 881 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8), 882 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8), 883 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4), 884 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8), 885 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3), 886 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5), 887 }; 888 889 static const struct tegra_gpio_soc tegra186_aon_soc = { 890 .num_ports = ARRAY_SIZE(tegra186_aon_ports), 891 .ports = tegra186_aon_ports, 892 .name = "tegra186-gpio-aon", 893 .instance = 1, 894 .num_irqs_per_bank = 1, 895 }; 896 897 #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 898 [TEGRA194_MAIN_GPIO_PORT_##_name] = { \ 899 .name = #_name, \ 900 .bank = _bank, \ 901 .port = _port, \ 902 .pins = _pins, \ 903 } 904 905 static const struct tegra_gpio_port tegra194_main_ports[] = { 906 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8), 907 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2), 908 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8), 909 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4), 910 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8), 911 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6), 912 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8), 913 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8), 914 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5), 915 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6), 916 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8), 917 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4), 918 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8), 919 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3), 920 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6), 921 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8), 922 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8), 923 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6), 924 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8), 925 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8), 926 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1), 927 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8), 928 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2), 929 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8), 930 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8), 931 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8), 932 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2), 933 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2) 934 }; 935 936 static const struct tegra186_pin_range tegra194_main_pin_ranges[] = { 937 { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" }, 938 { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" }, 939 }; 940 941 static const struct tegra_gpio_soc tegra194_main_soc = { 942 .num_ports = ARRAY_SIZE(tegra194_main_ports), 943 .ports = tegra194_main_ports, 944 .name = "tegra194-gpio", 945 .instance = 0, 946 .num_irqs_per_bank = 8, 947 .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges), 948 .pin_ranges = tegra194_main_pin_ranges, 949 .pinmux = "nvidia,tegra194-pinmux", 950 }; 951 952 #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 953 [TEGRA194_AON_GPIO_PORT_##_name] = { \ 954 .name = #_name, \ 955 .bank = _bank, \ 956 .port = _port, \ 957 .pins = _pins, \ 958 } 959 960 static const struct tegra_gpio_port tegra194_aon_ports[] = { 961 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8), 962 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4), 963 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8), 964 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3), 965 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7) 966 }; 967 968 static const struct tegra_gpio_soc tegra194_aon_soc = { 969 .num_ports = ARRAY_SIZE(tegra194_aon_ports), 970 .ports = tegra194_aon_ports, 971 .name = "tegra194-gpio-aon", 972 .instance = 1, 973 .num_irqs_per_bank = 8, 974 }; 975 976 #define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 977 [TEGRA234_MAIN_GPIO_PORT_##_name] = { \ 978 .name = #_name, \ 979 .bank = _bank, \ 980 .port = _port, \ 981 .pins = _pins, \ 982 } 983 984 static const struct tegra_gpio_port tegra234_main_ports[] = { 985 TEGRA234_MAIN_GPIO_PORT( A, 0, 0, 8), 986 TEGRA234_MAIN_GPIO_PORT( B, 0, 3, 1), 987 TEGRA234_MAIN_GPIO_PORT( C, 5, 1, 8), 988 TEGRA234_MAIN_GPIO_PORT( D, 5, 2, 4), 989 TEGRA234_MAIN_GPIO_PORT( E, 5, 3, 8), 990 TEGRA234_MAIN_GPIO_PORT( F, 5, 4, 6), 991 TEGRA234_MAIN_GPIO_PORT( G, 4, 0, 8), 992 TEGRA234_MAIN_GPIO_PORT( H, 4, 1, 8), 993 TEGRA234_MAIN_GPIO_PORT( I, 4, 2, 7), 994 TEGRA234_MAIN_GPIO_PORT( J, 5, 0, 6), 995 TEGRA234_MAIN_GPIO_PORT( K, 3, 0, 8), 996 TEGRA234_MAIN_GPIO_PORT( L, 3, 1, 4), 997 TEGRA234_MAIN_GPIO_PORT( M, 2, 0, 8), 998 TEGRA234_MAIN_GPIO_PORT( N, 2, 1, 8), 999 TEGRA234_MAIN_GPIO_PORT( P, 2, 2, 8), 1000 TEGRA234_MAIN_GPIO_PORT( Q, 2, 3, 8), 1001 TEGRA234_MAIN_GPIO_PORT( R, 2, 4, 6), 1002 TEGRA234_MAIN_GPIO_PORT( X, 1, 0, 8), 1003 TEGRA234_MAIN_GPIO_PORT( Y, 1, 1, 8), 1004 TEGRA234_MAIN_GPIO_PORT( Z, 1, 2, 8), 1005 TEGRA234_MAIN_GPIO_PORT(AC, 0, 1, 8), 1006 TEGRA234_MAIN_GPIO_PORT(AD, 0, 2, 4), 1007 TEGRA234_MAIN_GPIO_PORT(AE, 3, 3, 2), 1008 TEGRA234_MAIN_GPIO_PORT(AF, 3, 4, 4), 1009 TEGRA234_MAIN_GPIO_PORT(AG, 3, 2, 8), 1010 }; 1011 1012 static const struct tegra_gpio_soc tegra234_main_soc = { 1013 .num_ports = ARRAY_SIZE(tegra234_main_ports), 1014 .ports = tegra234_main_ports, 1015 .name = "tegra234-gpio", 1016 .instance = 0, 1017 .num_irqs_per_bank = 8, 1018 }; 1019 1020 #define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1021 [TEGRA234_AON_GPIO_PORT_##_name] = { \ 1022 .name = #_name, \ 1023 .bank = _bank, \ 1024 .port = _port, \ 1025 .pins = _pins, \ 1026 } 1027 1028 static const struct tegra_gpio_port tegra234_aon_ports[] = { 1029 TEGRA234_AON_GPIO_PORT(AA, 0, 4, 8), 1030 TEGRA234_AON_GPIO_PORT(BB, 0, 5, 4), 1031 TEGRA234_AON_GPIO_PORT(CC, 0, 2, 8), 1032 TEGRA234_AON_GPIO_PORT(DD, 0, 3, 3), 1033 TEGRA234_AON_GPIO_PORT(EE, 0, 0, 8), 1034 TEGRA234_AON_GPIO_PORT(GG, 0, 1, 1), 1035 }; 1036 1037 static const struct tegra_gpio_soc tegra234_aon_soc = { 1038 .num_ports = ARRAY_SIZE(tegra234_aon_ports), 1039 .ports = tegra234_aon_ports, 1040 .name = "tegra234-gpio-aon", 1041 .instance = 1, 1042 .num_irqs_per_bank = 8, 1043 }; 1044 1045 #define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1046 [TEGRA241_MAIN_GPIO_PORT_##_name] = { \ 1047 .name = #_name, \ 1048 .bank = _bank, \ 1049 .port = _port, \ 1050 .pins = _pins, \ 1051 } 1052 1053 static const struct tegra_gpio_port tegra241_main_ports[] = { 1054 TEGRA241_MAIN_GPIO_PORT(A, 0, 0, 8), 1055 TEGRA241_MAIN_GPIO_PORT(B, 0, 1, 8), 1056 TEGRA241_MAIN_GPIO_PORT(C, 0, 2, 2), 1057 TEGRA241_MAIN_GPIO_PORT(D, 0, 3, 6), 1058 TEGRA241_MAIN_GPIO_PORT(E, 0, 4, 8), 1059 TEGRA241_MAIN_GPIO_PORT(F, 1, 0, 8), 1060 TEGRA241_MAIN_GPIO_PORT(G, 1, 1, 8), 1061 TEGRA241_MAIN_GPIO_PORT(H, 1, 2, 8), 1062 TEGRA241_MAIN_GPIO_PORT(J, 1, 3, 8), 1063 TEGRA241_MAIN_GPIO_PORT(K, 1, 4, 4), 1064 TEGRA241_MAIN_GPIO_PORT(L, 1, 5, 6), 1065 }; 1066 1067 static const struct tegra_gpio_soc tegra241_main_soc = { 1068 .num_ports = ARRAY_SIZE(tegra241_main_ports), 1069 .ports = tegra241_main_ports, 1070 .name = "tegra241-gpio", 1071 .instance = 0, 1072 }; 1073 1074 #define TEGRA241_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1075 [TEGRA241_AON_GPIO_PORT_##_name] = { \ 1076 .name = #_name, \ 1077 .bank = _bank, \ 1078 .port = _port, \ 1079 .pins = _pins, \ 1080 } 1081 1082 static const struct tegra_gpio_port tegra241_aon_ports[] = { 1083 TEGRA241_AON_GPIO_PORT(AA, 0, 0, 8), 1084 TEGRA241_AON_GPIO_PORT(BB, 0, 0, 4), 1085 }; 1086 1087 static const struct tegra_gpio_soc tegra241_aon_soc = { 1088 .num_ports = ARRAY_SIZE(tegra241_aon_ports), 1089 .ports = tegra241_aon_ports, 1090 .name = "tegra241-gpio-aon", 1091 .instance = 1, 1092 }; 1093 1094 static const struct of_device_id tegra186_gpio_of_match[] = { 1095 { 1096 .compatible = "nvidia,tegra186-gpio", 1097 .data = &tegra186_main_soc 1098 }, { 1099 .compatible = "nvidia,tegra186-gpio-aon", 1100 .data = &tegra186_aon_soc 1101 }, { 1102 .compatible = "nvidia,tegra194-gpio", 1103 .data = &tegra194_main_soc 1104 }, { 1105 .compatible = "nvidia,tegra194-gpio-aon", 1106 .data = &tegra194_aon_soc 1107 }, { 1108 .compatible = "nvidia,tegra234-gpio", 1109 .data = &tegra234_main_soc 1110 }, { 1111 .compatible = "nvidia,tegra234-gpio-aon", 1112 .data = &tegra234_aon_soc 1113 }, { 1114 /* sentinel */ 1115 } 1116 }; 1117 MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match); 1118 1119 static const struct acpi_device_id tegra186_gpio_acpi_match[] = { 1120 { .id = "NVDA0108", .driver_data = (kernel_ulong_t)&tegra186_main_soc }, 1121 { .id = "NVDA0208", .driver_data = (kernel_ulong_t)&tegra186_aon_soc }, 1122 { .id = "NVDA0308", .driver_data = (kernel_ulong_t)&tegra194_main_soc }, 1123 { .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc }, 1124 { .id = "NVDA0508", .driver_data = (kernel_ulong_t)&tegra241_main_soc }, 1125 { .id = "NVDA0608", .driver_data = (kernel_ulong_t)&tegra241_aon_soc }, 1126 {} 1127 }; 1128 MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match); 1129 1130 static struct platform_driver tegra186_gpio_driver = { 1131 .driver = { 1132 .name = "tegra186-gpio", 1133 .of_match_table = tegra186_gpio_of_match, 1134 .acpi_match_table = tegra186_gpio_acpi_match, 1135 }, 1136 .probe = tegra186_gpio_probe, 1137 }; 1138 module_platform_driver(tegra186_gpio_driver); 1139 1140 MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver"); 1141 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 1142 MODULE_LICENSE("GPL v2"); 1143