1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016-2022 NVIDIA Corporation 4 * 5 * Author: Thierry Reding <treding@nvidia.com> 6 * Dipen Patel <dpatel@nvidia.com> 7 */ 8 9 #include <linux/gpio/driver.h> 10 #include <linux/hte.h> 11 #include <linux/interrupt.h> 12 #include <linux/irq.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/seq_file.h> 17 18 #include <dt-bindings/gpio/tegra186-gpio.h> 19 #include <dt-bindings/gpio/tegra194-gpio.h> 20 #include <dt-bindings/gpio/tegra234-gpio.h> 21 #include <dt-bindings/gpio/tegra241-gpio.h> 22 23 /* security registers */ 24 #define TEGRA186_GPIO_CTL_SCR 0x0c 25 #define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28) 26 #define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27) 27 28 #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4) 29 30 #define TEGRA186_GPIO_VM 0x00 31 #define TEGRA186_GPIO_VM_RW_MASK 0x03 32 #define TEGRA186_GPIO_SCR 0x04 33 #define TEGRA186_GPIO_SCR_PIN_SIZE 0x08 34 #define TEGRA186_GPIO_SCR_PORT_SIZE 0x40 35 #define TEGRA186_GPIO_SCR_SEC_WEN BIT(28) 36 #define TEGRA186_GPIO_SCR_SEC_REN BIT(27) 37 #define TEGRA186_GPIO_SCR_SEC_G1W BIT(9) 38 #define TEGRA186_GPIO_SCR_SEC_G1R BIT(1) 39 #define TEGRA186_GPIO_FULL_ACCESS (TEGRA186_GPIO_SCR_SEC_WEN | \ 40 TEGRA186_GPIO_SCR_SEC_REN | \ 41 TEGRA186_GPIO_SCR_SEC_G1R | \ 42 TEGRA186_GPIO_SCR_SEC_G1W) 43 #define TEGRA186_GPIO_SCR_SEC_ENABLE (TEGRA186_GPIO_SCR_SEC_WEN | \ 44 TEGRA186_GPIO_SCR_SEC_REN) 45 46 /* control registers */ 47 #define TEGRA186_GPIO_ENABLE_CONFIG 0x00 48 #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0) 49 #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1) 50 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2) 51 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2) 52 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2) 53 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2) 54 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2) 55 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4) 56 #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5) 57 #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6) 58 #define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC BIT(7) 59 60 #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04 61 #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff) 62 63 #define TEGRA186_GPIO_INPUT 0x08 64 #define TEGRA186_GPIO_INPUT_HIGH BIT(0) 65 66 #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c 67 #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0) 68 69 #define TEGRA186_GPIO_OUTPUT_VALUE 0x10 70 #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0) 71 72 #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14 73 74 #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4) 75 76 struct tegra_gpio_port { 77 const char *name; 78 unsigned int bank; 79 unsigned int port; 80 unsigned int pins; 81 }; 82 83 struct tegra186_pin_range { 84 unsigned int offset; 85 const char *group; 86 }; 87 88 struct tegra_gpio_soc { 89 const struct tegra_gpio_port *ports; 90 unsigned int num_ports; 91 const char *name; 92 unsigned int instance; 93 94 unsigned int num_irqs_per_bank; 95 96 const struct tegra186_pin_range *pin_ranges; 97 unsigned int num_pin_ranges; 98 const char *pinmux; 99 bool has_gte; 100 bool has_vm_support; 101 }; 102 103 struct tegra_gpio { 104 struct gpio_chip gpio; 105 unsigned int num_irq; 106 unsigned int *irq; 107 108 const struct tegra_gpio_soc *soc; 109 unsigned int num_irqs_per_bank; 110 unsigned int num_banks; 111 112 void __iomem *secure; 113 void __iomem *base; 114 }; 115 116 static const struct tegra_gpio_port * 117 tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin) 118 { 119 unsigned int start = 0, i; 120 121 for (i = 0; i < gpio->soc->num_ports; i++) { 122 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 123 124 if (*pin >= start && *pin < start + port->pins) { 125 *pin -= start; 126 return port; 127 } 128 129 start += port->pins; 130 } 131 132 return NULL; 133 } 134 135 static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio, 136 unsigned int pin) 137 { 138 const struct tegra_gpio_port *port; 139 unsigned int offset; 140 141 port = tegra186_gpio_get_port(gpio, &pin); 142 if (!port) 143 return NULL; 144 145 offset = port->bank * 0x1000 + port->port * 0x200; 146 147 return gpio->base + offset + pin * 0x20; 148 } 149 150 static void __iomem *tegra186_gpio_get_secure_base(struct tegra_gpio *gpio, 151 unsigned int pin) 152 { 153 const struct tegra_gpio_port *port; 154 unsigned int offset; 155 156 port = tegra186_gpio_get_port(gpio, &pin); 157 if (!port) 158 return NULL; 159 160 offset = port->bank * 0x1000 + port->port * TEGRA186_GPIO_SCR_PORT_SIZE; 161 162 return gpio->secure + offset + pin * TEGRA186_GPIO_SCR_PIN_SIZE; 163 } 164 165 static inline bool tegra186_gpio_is_accessible(struct tegra_gpio *gpio, unsigned int pin) 166 { 167 void __iomem *secure; 168 u32 value; 169 170 secure = tegra186_gpio_get_secure_base(gpio, pin); 171 172 if (gpio->soc->has_vm_support) { 173 value = readl(secure + TEGRA186_GPIO_VM); 174 if ((value & TEGRA186_GPIO_VM_RW_MASK) != TEGRA186_GPIO_VM_RW_MASK) 175 return false; 176 } 177 178 value = __raw_readl(secure + TEGRA186_GPIO_SCR); 179 180 if ((value & TEGRA186_GPIO_SCR_SEC_ENABLE) == 0) 181 return true; 182 183 if ((value & TEGRA186_GPIO_FULL_ACCESS) == TEGRA186_GPIO_FULL_ACCESS) 184 return true; 185 186 return false; 187 } 188 189 static int tegra186_init_valid_mask(struct gpio_chip *chip, 190 unsigned long *valid_mask, unsigned int ngpios) 191 { 192 struct tegra_gpio *gpio = gpiochip_get_data(chip); 193 unsigned int j; 194 195 for (j = 0; j < ngpios; j++) { 196 if (!tegra186_gpio_is_accessible(gpio, j)) 197 clear_bit(j, valid_mask); 198 } 199 return 0; 200 } 201 202 static int tegra186_gpio_get_direction(struct gpio_chip *chip, 203 unsigned int offset) 204 { 205 struct tegra_gpio *gpio = gpiochip_get_data(chip); 206 void __iomem *base; 207 u32 value; 208 209 base = tegra186_gpio_get_base(gpio, offset); 210 if (WARN_ON(base == NULL)) 211 return -ENODEV; 212 213 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 214 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) 215 return GPIO_LINE_DIRECTION_OUT; 216 217 return GPIO_LINE_DIRECTION_IN; 218 } 219 220 static int tegra186_gpio_direction_input(struct gpio_chip *chip, 221 unsigned int offset) 222 { 223 struct tegra_gpio *gpio = gpiochip_get_data(chip); 224 void __iomem *base; 225 u32 value; 226 227 base = tegra186_gpio_get_base(gpio, offset); 228 if (WARN_ON(base == NULL)) 229 return -ENODEV; 230 231 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); 232 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; 233 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); 234 235 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 236 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; 237 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT; 238 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 239 240 return 0; 241 } 242 243 static int tegra186_gpio_direction_output(struct gpio_chip *chip, 244 unsigned int offset, int level) 245 { 246 struct tegra_gpio *gpio = gpiochip_get_data(chip); 247 void __iomem *base; 248 u32 value; 249 250 /* configure output level first */ 251 chip->set(chip, offset, level); 252 253 base = tegra186_gpio_get_base(gpio, offset); 254 if (WARN_ON(base == NULL)) 255 return -EINVAL; 256 257 /* set the direction */ 258 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); 259 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; 260 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); 261 262 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 263 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; 264 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT; 265 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 266 267 return 0; 268 } 269 270 #define HTE_BOTH_EDGES (HTE_RISING_EDGE_TS | HTE_FALLING_EDGE_TS) 271 272 static int tegra186_gpio_en_hw_ts(struct gpio_chip *gc, u32 offset, 273 unsigned long flags) 274 { 275 struct tegra_gpio *gpio; 276 void __iomem *base; 277 int value; 278 279 if (!gc) 280 return -EINVAL; 281 282 gpio = gpiochip_get_data(gc); 283 if (!gpio) 284 return -ENODEV; 285 286 base = tegra186_gpio_get_base(gpio, offset); 287 if (WARN_ON(base == NULL)) 288 return -EINVAL; 289 290 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 291 value |= TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC; 292 293 if (flags == HTE_BOTH_EDGES) { 294 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; 295 } else if (flags == HTE_RISING_EDGE_TS) { 296 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 297 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 298 } else if (flags == HTE_FALLING_EDGE_TS) { 299 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 300 } 301 302 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 303 304 return 0; 305 } 306 307 static int tegra186_gpio_dis_hw_ts(struct gpio_chip *gc, u32 offset, 308 unsigned long flags) 309 { 310 struct tegra_gpio *gpio; 311 void __iomem *base; 312 int value; 313 314 if (!gc) 315 return -EINVAL; 316 317 gpio = gpiochip_get_data(gc); 318 if (!gpio) 319 return -ENODEV; 320 321 base = tegra186_gpio_get_base(gpio, offset); 322 if (WARN_ON(base == NULL)) 323 return -EINVAL; 324 325 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 326 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC; 327 if (flags == HTE_BOTH_EDGES) { 328 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; 329 } else if (flags == HTE_RISING_EDGE_TS) { 330 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 331 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 332 } else if (flags == HTE_FALLING_EDGE_TS) { 333 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 334 } 335 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 336 337 return 0; 338 } 339 340 static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset) 341 { 342 struct tegra_gpio *gpio = gpiochip_get_data(chip); 343 void __iomem *base; 344 u32 value; 345 346 base = tegra186_gpio_get_base(gpio, offset); 347 if (WARN_ON(base == NULL)) 348 return -ENODEV; 349 350 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 351 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) 352 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); 353 else 354 value = readl(base + TEGRA186_GPIO_INPUT); 355 356 return value & BIT(0); 357 } 358 359 static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset, 360 int level) 361 { 362 struct tegra_gpio *gpio = gpiochip_get_data(chip); 363 void __iomem *base; 364 u32 value; 365 366 base = tegra186_gpio_get_base(gpio, offset); 367 if (WARN_ON(base == NULL)) 368 return; 369 370 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); 371 if (level == 0) 372 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH; 373 else 374 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH; 375 376 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE); 377 } 378 379 static int tegra186_gpio_set_config(struct gpio_chip *chip, 380 unsigned int offset, 381 unsigned long config) 382 { 383 struct tegra_gpio *gpio = gpiochip_get_data(chip); 384 u32 debounce, value; 385 void __iomem *base; 386 387 base = tegra186_gpio_get_base(gpio, offset); 388 if (base == NULL) 389 return -ENXIO; 390 391 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 392 return -ENOTSUPP; 393 394 debounce = pinconf_to_config_argument(config); 395 396 /* 397 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce 398 * time. 399 */ 400 if (debounce > 255000) 401 return -EINVAL; 402 403 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC); 404 405 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce); 406 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL); 407 408 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 409 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE; 410 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 411 412 return 0; 413 } 414 415 static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip) 416 { 417 struct tegra_gpio *gpio = gpiochip_get_data(chip); 418 struct pinctrl_dev *pctldev; 419 struct device_node *np; 420 unsigned int i, j; 421 int err; 422 423 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0) 424 return 0; 425 426 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux); 427 if (!np) 428 return -ENODEV; 429 430 pctldev = of_pinctrl_get(np); 431 of_node_put(np); 432 if (!pctldev) 433 return -EPROBE_DEFER; 434 435 for (i = 0; i < gpio->soc->num_pin_ranges; i++) { 436 unsigned int pin = gpio->soc->pin_ranges[i].offset, port; 437 const char *group = gpio->soc->pin_ranges[i].group; 438 439 port = pin / 8; 440 pin = pin % 8; 441 442 if (port >= gpio->soc->num_ports) { 443 dev_warn(chip->parent, "invalid port %u for %s\n", 444 port, group); 445 continue; 446 } 447 448 for (j = 0; j < port; j++) 449 pin += gpio->soc->ports[j].pins; 450 451 err = gpiochip_add_pingroup_range(chip, pctldev, pin, group); 452 if (err < 0) 453 return err; 454 } 455 456 return 0; 457 } 458 459 static int tegra186_gpio_of_xlate(struct gpio_chip *chip, 460 const struct of_phandle_args *spec, 461 u32 *flags) 462 { 463 struct tegra_gpio *gpio = gpiochip_get_data(chip); 464 unsigned int port, pin, i, offset = 0; 465 466 if (WARN_ON(chip->of_gpio_n_cells < 2)) 467 return -EINVAL; 468 469 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells)) 470 return -EINVAL; 471 472 port = spec->args[0] / 8; 473 pin = spec->args[0] % 8; 474 475 if (port >= gpio->soc->num_ports) { 476 dev_err(chip->parent, "invalid port number: %u\n", port); 477 return -EINVAL; 478 } 479 480 for (i = 0; i < port; i++) 481 offset += gpio->soc->ports[i].pins; 482 483 if (flags) 484 *flags = spec->args[1]; 485 486 return offset + pin; 487 } 488 489 #define to_tegra_gpio(x) container_of((x), struct tegra_gpio, gpio) 490 491 static void tegra186_irq_ack(struct irq_data *data) 492 { 493 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 494 struct tegra_gpio *gpio = to_tegra_gpio(gc); 495 void __iomem *base; 496 497 base = tegra186_gpio_get_base(gpio, data->hwirq); 498 if (WARN_ON(base == NULL)) 499 return; 500 501 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR); 502 } 503 504 static void tegra186_irq_mask(struct irq_data *data) 505 { 506 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 507 struct tegra_gpio *gpio = to_tegra_gpio(gc); 508 void __iomem *base; 509 u32 value; 510 511 base = tegra186_gpio_get_base(gpio, data->hwirq); 512 if (WARN_ON(base == NULL)) 513 return; 514 515 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 516 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; 517 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 518 519 gpiochip_disable_irq(&gpio->gpio, data->hwirq); 520 } 521 522 static void tegra186_irq_unmask(struct irq_data *data) 523 { 524 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 525 struct tegra_gpio *gpio = to_tegra_gpio(gc); 526 void __iomem *base; 527 u32 value; 528 529 base = tegra186_gpio_get_base(gpio, data->hwirq); 530 if (WARN_ON(base == NULL)) 531 return; 532 533 gpiochip_enable_irq(&gpio->gpio, data->hwirq); 534 535 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 536 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; 537 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 538 } 539 540 static int tegra186_irq_set_type(struct irq_data *data, unsigned int type) 541 { 542 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 543 struct tegra_gpio *gpio = to_tegra_gpio(gc); 544 void __iomem *base; 545 u32 value; 546 547 base = tegra186_gpio_get_base(gpio, data->hwirq); 548 if (WARN_ON(base == NULL)) 549 return -ENODEV; 550 551 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 552 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK; 553 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 554 555 switch (type & IRQ_TYPE_SENSE_MASK) { 556 case IRQ_TYPE_NONE: 557 break; 558 559 case IRQ_TYPE_EDGE_RISING: 560 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 561 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 562 break; 563 564 case IRQ_TYPE_EDGE_FALLING: 565 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 566 break; 567 568 case IRQ_TYPE_EDGE_BOTH: 569 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; 570 break; 571 572 case IRQ_TYPE_LEVEL_HIGH: 573 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; 574 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 575 break; 576 577 case IRQ_TYPE_LEVEL_LOW: 578 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; 579 break; 580 581 default: 582 return -EINVAL; 583 } 584 585 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 586 587 if ((type & IRQ_TYPE_EDGE_BOTH) == 0) 588 irq_set_handler_locked(data, handle_level_irq); 589 else 590 irq_set_handler_locked(data, handle_edge_irq); 591 592 if (data->parent_data) 593 return irq_chip_set_type_parent(data, type); 594 595 return 0; 596 } 597 598 static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on) 599 { 600 if (data->parent_data) 601 return irq_chip_set_wake_parent(data, on); 602 603 return 0; 604 } 605 606 static void tegra186_irq_print_chip(struct irq_data *data, struct seq_file *p) 607 { 608 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 609 610 seq_printf(p, dev_name(gc->parent)); 611 } 612 613 static const struct irq_chip tegra186_gpio_irq_chip = { 614 .irq_ack = tegra186_irq_ack, 615 .irq_mask = tegra186_irq_mask, 616 .irq_unmask = tegra186_irq_unmask, 617 .irq_set_type = tegra186_irq_set_type, 618 .irq_set_wake = tegra186_irq_set_wake, 619 .irq_print_chip = tegra186_irq_print_chip, 620 .flags = IRQCHIP_IMMUTABLE, 621 GPIOCHIP_IRQ_RESOURCE_HELPERS, 622 }; 623 624 static void tegra186_gpio_irq(struct irq_desc *desc) 625 { 626 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc); 627 struct irq_domain *domain = gpio->gpio.irq.domain; 628 struct irq_chip *chip = irq_desc_get_chip(desc); 629 unsigned int parent = irq_desc_get_irq(desc); 630 unsigned int i, j, offset = 0; 631 632 chained_irq_enter(chip, desc); 633 634 for (i = 0; i < gpio->soc->num_ports; i++) { 635 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 636 unsigned int pin; 637 unsigned long value; 638 void __iomem *base; 639 640 base = gpio->base + port->bank * 0x1000 + port->port * 0x200; 641 642 /* skip ports that are not associated with this bank */ 643 for (j = 0; j < gpio->num_irqs_per_bank; j++) { 644 if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j]) 645 break; 646 } 647 648 if (j == gpio->num_irqs_per_bank) 649 goto skip; 650 651 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1)); 652 653 for_each_set_bit(pin, &value, port->pins) { 654 int ret = generic_handle_domain_irq(domain, offset + pin); 655 WARN_RATELIMIT(ret, "hwirq = %d", offset + pin); 656 } 657 658 skip: 659 offset += port->pins; 660 } 661 662 chained_irq_exit(chip, desc); 663 } 664 665 static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain, 666 struct irq_fwspec *fwspec, 667 unsigned long *hwirq, 668 unsigned int *type) 669 { 670 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data); 671 unsigned int port, pin, i, offset = 0; 672 673 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2)) 674 return -EINVAL; 675 676 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells)) 677 return -EINVAL; 678 679 port = fwspec->param[0] / 8; 680 pin = fwspec->param[0] % 8; 681 682 if (port >= gpio->soc->num_ports) 683 return -EINVAL; 684 685 for (i = 0; i < port; i++) 686 offset += gpio->soc->ports[i].pins; 687 688 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; 689 *hwirq = offset + pin; 690 691 return 0; 692 } 693 694 static int tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip, 695 union gpio_irq_fwspec *gfwspec, 696 unsigned int parent_hwirq, 697 unsigned int parent_type) 698 { 699 struct tegra_gpio *gpio = gpiochip_get_data(chip); 700 struct irq_fwspec *fwspec = &gfwspec->fwspec; 701 702 fwspec->fwnode = chip->irq.parent_domain->fwnode; 703 fwspec->param_count = 3; 704 fwspec->param[0] = gpio->soc->instance; 705 fwspec->param[1] = parent_hwirq; 706 fwspec->param[2] = parent_type; 707 708 return 0; 709 } 710 711 static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip, 712 unsigned int hwirq, 713 unsigned int type, 714 unsigned int *parent_hwirq, 715 unsigned int *parent_type) 716 { 717 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq); 718 *parent_type = type; 719 720 return 0; 721 } 722 723 static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip, 724 unsigned int offset) 725 { 726 struct tegra_gpio *gpio = gpiochip_get_data(chip); 727 unsigned int i; 728 729 for (i = 0; i < gpio->soc->num_ports; i++) { 730 if (offset < gpio->soc->ports[i].pins) 731 break; 732 733 offset -= gpio->soc->ports[i].pins; 734 } 735 736 return offset + i * 8; 737 } 738 739 static const struct of_device_id tegra186_pmc_of_match[] = { 740 { .compatible = "nvidia,tegra186-pmc" }, 741 { .compatible = "nvidia,tegra194-pmc" }, 742 { .compatible = "nvidia,tegra234-pmc" }, 743 { /* sentinel */ } 744 }; 745 746 static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio) 747 { 748 struct device *dev = gpio->gpio.parent; 749 unsigned int i; 750 u32 value; 751 752 for (i = 0; i < gpio->soc->num_ports; i++) { 753 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 754 unsigned int offset, p = port->port; 755 void __iomem *base; 756 757 base = gpio->secure + port->bank * 0x1000 + 0x800; 758 759 value = readl(base + TEGRA186_GPIO_CTL_SCR); 760 761 /* 762 * For controllers that haven't been locked down yet, make 763 * sure to program the default interrupt route mapping. 764 */ 765 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 && 766 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) { 767 /* 768 * On Tegra194 and later, each pin can be routed to one or more 769 * interrupts. 770 */ 771 dev_dbg(dev, "programming default interrupt routing for port %s\n", 772 port->name); 773 774 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, 0); 775 776 /* 777 * By default we only want to route GPIO pins to IRQ 0. This works 778 * only under the assumption that we're running as the host kernel 779 * and hence all GPIO pins are owned by Linux. 780 * 781 * For cases where Linux is the guest OS, the hypervisor will have 782 * to configure the interrupt routing and pass only the valid 783 * interrupts via device tree. 784 */ 785 value = readl(base + offset); 786 value = BIT(port->pins) - 1; 787 writel(value, base + offset); 788 } 789 } 790 } 791 792 static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio) 793 { 794 struct device *dev = gpio->gpio.parent; 795 796 if (gpio->num_irq > gpio->num_banks) { 797 if (gpio->num_irq % gpio->num_banks != 0) 798 goto error; 799 } 800 801 if (gpio->num_irq < gpio->num_banks) 802 goto error; 803 804 gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks; 805 806 if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank) 807 goto error; 808 809 return 0; 810 811 error: 812 dev_err(dev, "invalid number of interrupts (%u) for %u banks\n", 813 gpio->num_irq, gpio->num_banks); 814 return -EINVAL; 815 } 816 817 static int tegra186_gpio_probe(struct platform_device *pdev) 818 { 819 unsigned int i, j, offset; 820 struct gpio_irq_chip *irq; 821 struct tegra_gpio *gpio; 822 struct device_node *np; 823 char **names; 824 int err; 825 826 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 827 if (!gpio) 828 return -ENOMEM; 829 830 gpio->soc = device_get_match_data(&pdev->dev); 831 gpio->gpio.label = gpio->soc->name; 832 gpio->gpio.parent = &pdev->dev; 833 834 /* count the number of banks in the controller */ 835 for (i = 0; i < gpio->soc->num_ports; i++) 836 if (gpio->soc->ports[i].bank > gpio->num_banks) 837 gpio->num_banks = gpio->soc->ports[i].bank; 838 839 gpio->num_banks++; 840 841 /* get register apertures */ 842 gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security"); 843 if (IS_ERR(gpio->secure)) { 844 gpio->secure = devm_platform_ioremap_resource(pdev, 0); 845 if (IS_ERR(gpio->secure)) 846 return PTR_ERR(gpio->secure); 847 } 848 849 gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio"); 850 if (IS_ERR(gpio->base)) { 851 gpio->base = devm_platform_ioremap_resource(pdev, 1); 852 if (IS_ERR(gpio->base)) 853 return PTR_ERR(gpio->base); 854 } 855 856 err = platform_irq_count(pdev); 857 if (err < 0) 858 return err; 859 860 gpio->num_irq = err; 861 862 err = tegra186_gpio_irqs_per_bank(gpio); 863 if (err < 0) 864 return err; 865 866 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq), 867 GFP_KERNEL); 868 if (!gpio->irq) 869 return -ENOMEM; 870 871 for (i = 0; i < gpio->num_irq; i++) { 872 err = platform_get_irq(pdev, i); 873 if (err < 0) 874 return err; 875 876 gpio->irq[i] = err; 877 } 878 879 gpio->gpio.request = gpiochip_generic_request; 880 gpio->gpio.free = gpiochip_generic_free; 881 gpio->gpio.get_direction = tegra186_gpio_get_direction; 882 gpio->gpio.direction_input = tegra186_gpio_direction_input; 883 gpio->gpio.direction_output = tegra186_gpio_direction_output; 884 gpio->gpio.get = tegra186_gpio_get; 885 gpio->gpio.set = tegra186_gpio_set; 886 gpio->gpio.set_config = tegra186_gpio_set_config; 887 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges; 888 gpio->gpio.init_valid_mask = tegra186_init_valid_mask; 889 if (gpio->soc->has_gte) { 890 gpio->gpio.en_hw_timestamp = tegra186_gpio_en_hw_ts; 891 gpio->gpio.dis_hw_timestamp = tegra186_gpio_dis_hw_ts; 892 } 893 894 gpio->gpio.base = -1; 895 896 for (i = 0; i < gpio->soc->num_ports; i++) 897 gpio->gpio.ngpio += gpio->soc->ports[i].pins; 898 899 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio, 900 sizeof(*names), GFP_KERNEL); 901 if (!names) 902 return -ENOMEM; 903 904 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { 905 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 906 char *name; 907 908 for (j = 0; j < port->pins; j++) { 909 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL, 910 "P%s.%02x", port->name, j); 911 if (!name) 912 return -ENOMEM; 913 914 names[offset + j] = name; 915 } 916 917 offset += port->pins; 918 } 919 920 gpio->gpio.names = (const char * const *)names; 921 922 #if defined(CONFIG_OF_GPIO) 923 gpio->gpio.of_gpio_n_cells = 2; 924 gpio->gpio.of_xlate = tegra186_gpio_of_xlate; 925 #endif /* CONFIG_OF_GPIO */ 926 927 irq = &gpio->gpio.irq; 928 gpio_irq_chip_set_chip(irq, &tegra186_gpio_irq_chip); 929 irq->fwnode = of_node_to_fwnode(pdev->dev.of_node); 930 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq; 931 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec; 932 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq; 933 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate; 934 irq->handler = handle_simple_irq; 935 irq->default_type = IRQ_TYPE_NONE; 936 irq->parent_handler = tegra186_gpio_irq; 937 irq->parent_handler_data = gpio; 938 irq->num_parents = gpio->num_irq; 939 940 /* 941 * To simplify things, use a single interrupt per bank for now. Some 942 * chips support up to 8 interrupts per bank, which can be useful to 943 * distribute the load and decrease the processing latency for GPIOs 944 * but it also requires a more complicated interrupt routing than we 945 * currently program. 946 */ 947 if (gpio->num_irqs_per_bank > 1) { 948 irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks, 949 sizeof(*irq->parents), GFP_KERNEL); 950 if (!irq->parents) 951 return -ENOMEM; 952 953 for (i = 0; i < gpio->num_banks; i++) 954 irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank]; 955 956 irq->num_parents = gpio->num_banks; 957 } else { 958 irq->num_parents = gpio->num_irq; 959 irq->parents = gpio->irq; 960 } 961 962 if (gpio->soc->num_irqs_per_bank > 1) 963 tegra186_gpio_init_route_mapping(gpio); 964 965 np = of_find_matching_node(NULL, tegra186_pmc_of_match); 966 if (np) { 967 if (of_device_is_available(np)) { 968 irq->parent_domain = irq_find_host(np); 969 of_node_put(np); 970 971 if (!irq->parent_domain) 972 return -EPROBE_DEFER; 973 } else { 974 of_node_put(np); 975 } 976 } 977 978 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio, 979 sizeof(*irq->map), GFP_KERNEL); 980 if (!irq->map) 981 return -ENOMEM; 982 983 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { 984 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 985 986 for (j = 0; j < port->pins; j++) 987 irq->map[offset + j] = irq->parents[port->bank]; 988 989 offset += port->pins; 990 } 991 992 return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio); 993 } 994 995 #define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 996 [TEGRA186_MAIN_GPIO_PORT_##_name] = { \ 997 .name = #_name, \ 998 .bank = _bank, \ 999 .port = _port, \ 1000 .pins = _pins, \ 1001 } 1002 1003 static const struct tegra_gpio_port tegra186_main_ports[] = { 1004 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7), 1005 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7), 1006 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7), 1007 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6), 1008 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8), 1009 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6), 1010 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6), 1011 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7), 1012 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8), 1013 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8), 1014 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1), 1015 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8), 1016 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6), 1017 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7), 1018 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4), 1019 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7), 1020 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6), 1021 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6), 1022 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4), 1023 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8), 1024 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7), 1025 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2), 1026 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4), 1027 }; 1028 1029 static const struct tegra_gpio_soc tegra186_main_soc = { 1030 .num_ports = ARRAY_SIZE(tegra186_main_ports), 1031 .ports = tegra186_main_ports, 1032 .name = "tegra186-gpio", 1033 .instance = 0, 1034 .num_irqs_per_bank = 1, 1035 .has_vm_support = false, 1036 }; 1037 1038 #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1039 [TEGRA186_AON_GPIO_PORT_##_name] = { \ 1040 .name = #_name, \ 1041 .bank = _bank, \ 1042 .port = _port, \ 1043 .pins = _pins, \ 1044 } 1045 1046 static const struct tegra_gpio_port tegra186_aon_ports[] = { 1047 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5), 1048 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6), 1049 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8), 1050 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8), 1051 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4), 1052 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8), 1053 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3), 1054 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5), 1055 }; 1056 1057 static const struct tegra_gpio_soc tegra186_aon_soc = { 1058 .num_ports = ARRAY_SIZE(tegra186_aon_ports), 1059 .ports = tegra186_aon_ports, 1060 .name = "tegra186-gpio-aon", 1061 .instance = 1, 1062 .num_irqs_per_bank = 1, 1063 .has_vm_support = false, 1064 }; 1065 1066 #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1067 [TEGRA194_MAIN_GPIO_PORT_##_name] = { \ 1068 .name = #_name, \ 1069 .bank = _bank, \ 1070 .port = _port, \ 1071 .pins = _pins, \ 1072 } 1073 1074 static const struct tegra_gpio_port tegra194_main_ports[] = { 1075 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8), 1076 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2), 1077 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8), 1078 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4), 1079 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8), 1080 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6), 1081 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8), 1082 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8), 1083 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5), 1084 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6), 1085 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8), 1086 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4), 1087 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8), 1088 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3), 1089 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6), 1090 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8), 1091 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8), 1092 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6), 1093 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8), 1094 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8), 1095 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1), 1096 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8), 1097 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2), 1098 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8), 1099 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8), 1100 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8), 1101 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2), 1102 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2) 1103 }; 1104 1105 static const struct tegra186_pin_range tegra194_main_pin_ranges[] = { 1106 { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" }, 1107 { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" }, 1108 }; 1109 1110 static const struct tegra_gpio_soc tegra194_main_soc = { 1111 .num_ports = ARRAY_SIZE(tegra194_main_ports), 1112 .ports = tegra194_main_ports, 1113 .name = "tegra194-gpio", 1114 .instance = 0, 1115 .num_irqs_per_bank = 8, 1116 .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges), 1117 .pin_ranges = tegra194_main_pin_ranges, 1118 .pinmux = "nvidia,tegra194-pinmux", 1119 .has_vm_support = true, 1120 }; 1121 1122 #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1123 [TEGRA194_AON_GPIO_PORT_##_name] = { \ 1124 .name = #_name, \ 1125 .bank = _bank, \ 1126 .port = _port, \ 1127 .pins = _pins, \ 1128 } 1129 1130 static const struct tegra_gpio_port tegra194_aon_ports[] = { 1131 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8), 1132 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4), 1133 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8), 1134 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3), 1135 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7) 1136 }; 1137 1138 static const struct tegra_gpio_soc tegra194_aon_soc = { 1139 .num_ports = ARRAY_SIZE(tegra194_aon_ports), 1140 .ports = tegra194_aon_ports, 1141 .name = "tegra194-gpio-aon", 1142 .instance = 1, 1143 .num_irqs_per_bank = 8, 1144 .has_gte = true, 1145 .has_vm_support = false, 1146 }; 1147 1148 #define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1149 [TEGRA234_MAIN_GPIO_PORT_##_name] = { \ 1150 .name = #_name, \ 1151 .bank = _bank, \ 1152 .port = _port, \ 1153 .pins = _pins, \ 1154 } 1155 1156 static const struct tegra_gpio_port tegra234_main_ports[] = { 1157 TEGRA234_MAIN_GPIO_PORT( A, 0, 0, 8), 1158 TEGRA234_MAIN_GPIO_PORT( B, 0, 3, 1), 1159 TEGRA234_MAIN_GPIO_PORT( C, 5, 1, 8), 1160 TEGRA234_MAIN_GPIO_PORT( D, 5, 2, 4), 1161 TEGRA234_MAIN_GPIO_PORT( E, 5, 3, 8), 1162 TEGRA234_MAIN_GPIO_PORT( F, 5, 4, 6), 1163 TEGRA234_MAIN_GPIO_PORT( G, 4, 0, 8), 1164 TEGRA234_MAIN_GPIO_PORT( H, 4, 1, 8), 1165 TEGRA234_MAIN_GPIO_PORT( I, 4, 2, 7), 1166 TEGRA234_MAIN_GPIO_PORT( J, 5, 0, 6), 1167 TEGRA234_MAIN_GPIO_PORT( K, 3, 0, 8), 1168 TEGRA234_MAIN_GPIO_PORT( L, 3, 1, 4), 1169 TEGRA234_MAIN_GPIO_PORT( M, 2, 0, 8), 1170 TEGRA234_MAIN_GPIO_PORT( N, 2, 1, 8), 1171 TEGRA234_MAIN_GPIO_PORT( P, 2, 2, 8), 1172 TEGRA234_MAIN_GPIO_PORT( Q, 2, 3, 8), 1173 TEGRA234_MAIN_GPIO_PORT( R, 2, 4, 6), 1174 TEGRA234_MAIN_GPIO_PORT( X, 1, 0, 8), 1175 TEGRA234_MAIN_GPIO_PORT( Y, 1, 1, 8), 1176 TEGRA234_MAIN_GPIO_PORT( Z, 1, 2, 8), 1177 TEGRA234_MAIN_GPIO_PORT(AC, 0, 1, 8), 1178 TEGRA234_MAIN_GPIO_PORT(AD, 0, 2, 4), 1179 TEGRA234_MAIN_GPIO_PORT(AE, 3, 3, 2), 1180 TEGRA234_MAIN_GPIO_PORT(AF, 3, 4, 4), 1181 TEGRA234_MAIN_GPIO_PORT(AG, 3, 2, 8), 1182 }; 1183 1184 static const struct tegra_gpio_soc tegra234_main_soc = { 1185 .num_ports = ARRAY_SIZE(tegra234_main_ports), 1186 .ports = tegra234_main_ports, 1187 .name = "tegra234-gpio", 1188 .instance = 0, 1189 .num_irqs_per_bank = 8, 1190 .has_vm_support = true, 1191 }; 1192 1193 #define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1194 [TEGRA234_AON_GPIO_PORT_##_name] = { \ 1195 .name = #_name, \ 1196 .bank = _bank, \ 1197 .port = _port, \ 1198 .pins = _pins, \ 1199 } 1200 1201 static const struct tegra_gpio_port tegra234_aon_ports[] = { 1202 TEGRA234_AON_GPIO_PORT(AA, 0, 4, 8), 1203 TEGRA234_AON_GPIO_PORT(BB, 0, 5, 4), 1204 TEGRA234_AON_GPIO_PORT(CC, 0, 2, 8), 1205 TEGRA234_AON_GPIO_PORT(DD, 0, 3, 3), 1206 TEGRA234_AON_GPIO_PORT(EE, 0, 0, 8), 1207 TEGRA234_AON_GPIO_PORT(GG, 0, 1, 1), 1208 }; 1209 1210 static const struct tegra_gpio_soc tegra234_aon_soc = { 1211 .num_ports = ARRAY_SIZE(tegra234_aon_ports), 1212 .ports = tegra234_aon_ports, 1213 .name = "tegra234-gpio-aon", 1214 .instance = 1, 1215 .num_irqs_per_bank = 8, 1216 .has_gte = true, 1217 .has_vm_support = false, 1218 }; 1219 1220 #define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1221 [TEGRA241_MAIN_GPIO_PORT_##_name] = { \ 1222 .name = #_name, \ 1223 .bank = _bank, \ 1224 .port = _port, \ 1225 .pins = _pins, \ 1226 } 1227 1228 static const struct tegra_gpio_port tegra241_main_ports[] = { 1229 TEGRA241_MAIN_GPIO_PORT(A, 0, 0, 8), 1230 TEGRA241_MAIN_GPIO_PORT(B, 0, 1, 8), 1231 TEGRA241_MAIN_GPIO_PORT(C, 0, 2, 2), 1232 TEGRA241_MAIN_GPIO_PORT(D, 0, 3, 6), 1233 TEGRA241_MAIN_GPIO_PORT(E, 0, 4, 8), 1234 TEGRA241_MAIN_GPIO_PORT(F, 1, 0, 8), 1235 TEGRA241_MAIN_GPIO_PORT(G, 1, 1, 8), 1236 TEGRA241_MAIN_GPIO_PORT(H, 1, 2, 8), 1237 TEGRA241_MAIN_GPIO_PORT(J, 1, 3, 8), 1238 TEGRA241_MAIN_GPIO_PORT(K, 1, 4, 4), 1239 TEGRA241_MAIN_GPIO_PORT(L, 1, 5, 6), 1240 }; 1241 1242 static const struct tegra_gpio_soc tegra241_main_soc = { 1243 .num_ports = ARRAY_SIZE(tegra241_main_ports), 1244 .ports = tegra241_main_ports, 1245 .name = "tegra241-gpio", 1246 .instance = 0, 1247 .num_irqs_per_bank = 8, 1248 .has_vm_support = false, 1249 }; 1250 1251 #define TEGRA241_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1252 [TEGRA241_AON_GPIO_PORT_##_name] = { \ 1253 .name = #_name, \ 1254 .bank = _bank, \ 1255 .port = _port, \ 1256 .pins = _pins, \ 1257 } 1258 1259 static const struct tegra_gpio_port tegra241_aon_ports[] = { 1260 TEGRA241_AON_GPIO_PORT(AA, 0, 0, 8), 1261 TEGRA241_AON_GPIO_PORT(BB, 0, 0, 4), 1262 }; 1263 1264 static const struct tegra_gpio_soc tegra241_aon_soc = { 1265 .num_ports = ARRAY_SIZE(tegra241_aon_ports), 1266 .ports = tegra241_aon_ports, 1267 .name = "tegra241-gpio-aon", 1268 .instance = 1, 1269 .num_irqs_per_bank = 8, 1270 .has_vm_support = false, 1271 }; 1272 1273 static const struct of_device_id tegra186_gpio_of_match[] = { 1274 { 1275 .compatible = "nvidia,tegra186-gpio", 1276 .data = &tegra186_main_soc 1277 }, { 1278 .compatible = "nvidia,tegra186-gpio-aon", 1279 .data = &tegra186_aon_soc 1280 }, { 1281 .compatible = "nvidia,tegra194-gpio", 1282 .data = &tegra194_main_soc 1283 }, { 1284 .compatible = "nvidia,tegra194-gpio-aon", 1285 .data = &tegra194_aon_soc 1286 }, { 1287 .compatible = "nvidia,tegra234-gpio", 1288 .data = &tegra234_main_soc 1289 }, { 1290 .compatible = "nvidia,tegra234-gpio-aon", 1291 .data = &tegra234_aon_soc 1292 }, { 1293 /* sentinel */ 1294 } 1295 }; 1296 MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match); 1297 1298 static const struct acpi_device_id tegra186_gpio_acpi_match[] = { 1299 { .id = "NVDA0108", .driver_data = (kernel_ulong_t)&tegra186_main_soc }, 1300 { .id = "NVDA0208", .driver_data = (kernel_ulong_t)&tegra186_aon_soc }, 1301 { .id = "NVDA0308", .driver_data = (kernel_ulong_t)&tegra194_main_soc }, 1302 { .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc }, 1303 { .id = "NVDA0508", .driver_data = (kernel_ulong_t)&tegra241_main_soc }, 1304 { .id = "NVDA0608", .driver_data = (kernel_ulong_t)&tegra241_aon_soc }, 1305 {} 1306 }; 1307 MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match); 1308 1309 static struct platform_driver tegra186_gpio_driver = { 1310 .driver = { 1311 .name = "tegra186-gpio", 1312 .of_match_table = tegra186_gpio_of_match, 1313 .acpi_match_table = tegra186_gpio_acpi_match, 1314 }, 1315 .probe = tegra186_gpio_probe, 1316 }; 1317 module_platform_driver(tegra186_gpio_driver); 1318 1319 MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver"); 1320 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 1321 MODULE_LICENSE("GPL v2"); 1322