1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016-2022 NVIDIA Corporation 4 * 5 * Author: Thierry Reding <treding@nvidia.com> 6 * Dipen Patel <dpatel@nvidia.com> 7 */ 8 9 #include <linux/gpio/driver.h> 10 #include <linux/interrupt.h> 11 #include <linux/irq.h> 12 #include <linux/module.h> 13 #include <linux/of_device.h> 14 #include <linux/platform_device.h> 15 #include <linux/hte.h> 16 17 #include <dt-bindings/gpio/tegra186-gpio.h> 18 #include <dt-bindings/gpio/tegra194-gpio.h> 19 #include <dt-bindings/gpio/tegra234-gpio.h> 20 #include <dt-bindings/gpio/tegra241-gpio.h> 21 22 /* security registers */ 23 #define TEGRA186_GPIO_CTL_SCR 0x0c 24 #define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28) 25 #define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27) 26 27 #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4) 28 29 /* control registers */ 30 #define TEGRA186_GPIO_ENABLE_CONFIG 0x00 31 #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0) 32 #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1) 33 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2) 34 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2) 35 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2) 36 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2) 37 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2) 38 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4) 39 #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5) 40 #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6) 41 #define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC BIT(7) 42 43 #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04 44 #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff) 45 46 #define TEGRA186_GPIO_INPUT 0x08 47 #define TEGRA186_GPIO_INPUT_HIGH BIT(0) 48 49 #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c 50 #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0) 51 52 #define TEGRA186_GPIO_OUTPUT_VALUE 0x10 53 #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0) 54 55 #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14 56 57 #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4) 58 59 struct tegra_gpio_port { 60 const char *name; 61 unsigned int bank; 62 unsigned int port; 63 unsigned int pins; 64 }; 65 66 struct tegra186_pin_range { 67 unsigned int offset; 68 const char *group; 69 }; 70 71 struct tegra_gpio_soc { 72 const struct tegra_gpio_port *ports; 73 unsigned int num_ports; 74 const char *name; 75 unsigned int instance; 76 77 unsigned int num_irqs_per_bank; 78 79 const struct tegra186_pin_range *pin_ranges; 80 unsigned int num_pin_ranges; 81 const char *pinmux; 82 bool has_gte; 83 }; 84 85 struct tegra_gpio { 86 struct gpio_chip gpio; 87 unsigned int num_irq; 88 unsigned int *irq; 89 90 const struct tegra_gpio_soc *soc; 91 unsigned int num_irqs_per_bank; 92 unsigned int num_banks; 93 94 void __iomem *secure; 95 void __iomem *base; 96 }; 97 98 static const struct tegra_gpio_port * 99 tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin) 100 { 101 unsigned int start = 0, i; 102 103 for (i = 0; i < gpio->soc->num_ports; i++) { 104 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 105 106 if (*pin >= start && *pin < start + port->pins) { 107 *pin -= start; 108 return port; 109 } 110 111 start += port->pins; 112 } 113 114 return NULL; 115 } 116 117 static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio, 118 unsigned int pin) 119 { 120 const struct tegra_gpio_port *port; 121 unsigned int offset; 122 123 port = tegra186_gpio_get_port(gpio, &pin); 124 if (!port) 125 return NULL; 126 127 offset = port->bank * 0x1000 + port->port * 0x200; 128 129 return gpio->base + offset + pin * 0x20; 130 } 131 132 static int tegra186_gpio_get_direction(struct gpio_chip *chip, 133 unsigned int offset) 134 { 135 struct tegra_gpio *gpio = gpiochip_get_data(chip); 136 void __iomem *base; 137 u32 value; 138 139 base = tegra186_gpio_get_base(gpio, offset); 140 if (WARN_ON(base == NULL)) 141 return -ENODEV; 142 143 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 144 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) 145 return GPIO_LINE_DIRECTION_OUT; 146 147 return GPIO_LINE_DIRECTION_IN; 148 } 149 150 static int tegra186_gpio_direction_input(struct gpio_chip *chip, 151 unsigned int offset) 152 { 153 struct tegra_gpio *gpio = gpiochip_get_data(chip); 154 void __iomem *base; 155 u32 value; 156 157 base = tegra186_gpio_get_base(gpio, offset); 158 if (WARN_ON(base == NULL)) 159 return -ENODEV; 160 161 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); 162 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; 163 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); 164 165 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 166 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; 167 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT; 168 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 169 170 return 0; 171 } 172 173 static int tegra186_gpio_direction_output(struct gpio_chip *chip, 174 unsigned int offset, int level) 175 { 176 struct tegra_gpio *gpio = gpiochip_get_data(chip); 177 void __iomem *base; 178 u32 value; 179 180 /* configure output level first */ 181 chip->set(chip, offset, level); 182 183 base = tegra186_gpio_get_base(gpio, offset); 184 if (WARN_ON(base == NULL)) 185 return -EINVAL; 186 187 /* set the direction */ 188 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); 189 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; 190 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); 191 192 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 193 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; 194 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT; 195 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 196 197 return 0; 198 } 199 200 #define HTE_BOTH_EDGES (HTE_RISING_EDGE_TS | HTE_FALLING_EDGE_TS) 201 202 static int tegra186_gpio_en_hw_ts(struct gpio_chip *gc, u32 offset, 203 unsigned long flags) 204 { 205 struct tegra_gpio *gpio; 206 void __iomem *base; 207 int value; 208 209 if (!gc) 210 return -EINVAL; 211 212 gpio = gpiochip_get_data(gc); 213 if (!gpio) 214 return -ENODEV; 215 216 base = tegra186_gpio_get_base(gpio, offset); 217 if (WARN_ON(base == NULL)) 218 return -EINVAL; 219 220 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 221 value |= TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC; 222 223 if (flags == HTE_BOTH_EDGES) { 224 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; 225 } else if (flags == HTE_RISING_EDGE_TS) { 226 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 227 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 228 } else if (flags == HTE_FALLING_EDGE_TS) { 229 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 230 } 231 232 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 233 234 return 0; 235 } 236 237 static int tegra186_gpio_dis_hw_ts(struct gpio_chip *gc, u32 offset, 238 unsigned long flags) 239 { 240 struct tegra_gpio *gpio; 241 void __iomem *base; 242 int value; 243 244 if (!gc) 245 return -EINVAL; 246 247 gpio = gpiochip_get_data(gc); 248 if (!gpio) 249 return -ENODEV; 250 251 base = tegra186_gpio_get_base(gpio, offset); 252 if (WARN_ON(base == NULL)) 253 return -EINVAL; 254 255 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 256 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC; 257 if (flags == HTE_BOTH_EDGES) { 258 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; 259 } else if (flags == HTE_RISING_EDGE_TS) { 260 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 261 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 262 } else if (flags == HTE_FALLING_EDGE_TS) { 263 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 264 } 265 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 266 267 return 0; 268 } 269 270 static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset) 271 { 272 struct tegra_gpio *gpio = gpiochip_get_data(chip); 273 void __iomem *base; 274 u32 value; 275 276 base = tegra186_gpio_get_base(gpio, offset); 277 if (WARN_ON(base == NULL)) 278 return -ENODEV; 279 280 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 281 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) 282 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); 283 else 284 value = readl(base + TEGRA186_GPIO_INPUT); 285 286 return value & BIT(0); 287 } 288 289 static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset, 290 int level) 291 { 292 struct tegra_gpio *gpio = gpiochip_get_data(chip); 293 void __iomem *base; 294 u32 value; 295 296 base = tegra186_gpio_get_base(gpio, offset); 297 if (WARN_ON(base == NULL)) 298 return; 299 300 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); 301 if (level == 0) 302 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH; 303 else 304 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH; 305 306 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE); 307 } 308 309 static int tegra186_gpio_set_config(struct gpio_chip *chip, 310 unsigned int offset, 311 unsigned long config) 312 { 313 struct tegra_gpio *gpio = gpiochip_get_data(chip); 314 u32 debounce, value; 315 void __iomem *base; 316 317 base = tegra186_gpio_get_base(gpio, offset); 318 if (base == NULL) 319 return -ENXIO; 320 321 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 322 return -ENOTSUPP; 323 324 debounce = pinconf_to_config_argument(config); 325 326 /* 327 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce 328 * time. 329 */ 330 if (debounce > 255000) 331 return -EINVAL; 332 333 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC); 334 335 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce); 336 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL); 337 338 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 339 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE; 340 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 341 342 return 0; 343 } 344 345 static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip) 346 { 347 struct tegra_gpio *gpio = gpiochip_get_data(chip); 348 struct pinctrl_dev *pctldev; 349 struct device_node *np; 350 unsigned int i, j; 351 int err; 352 353 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0) 354 return 0; 355 356 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux); 357 if (!np) 358 return -ENODEV; 359 360 pctldev = of_pinctrl_get(np); 361 of_node_put(np); 362 if (!pctldev) 363 return -EPROBE_DEFER; 364 365 for (i = 0; i < gpio->soc->num_pin_ranges; i++) { 366 unsigned int pin = gpio->soc->pin_ranges[i].offset, port; 367 const char *group = gpio->soc->pin_ranges[i].group; 368 369 port = pin / 8; 370 pin = pin % 8; 371 372 if (port >= gpio->soc->num_ports) { 373 dev_warn(chip->parent, "invalid port %u for %s\n", 374 port, group); 375 continue; 376 } 377 378 for (j = 0; j < port; j++) 379 pin += gpio->soc->ports[j].pins; 380 381 err = gpiochip_add_pingroup_range(chip, pctldev, pin, group); 382 if (err < 0) 383 return err; 384 } 385 386 return 0; 387 } 388 389 static int tegra186_gpio_of_xlate(struct gpio_chip *chip, 390 const struct of_phandle_args *spec, 391 u32 *flags) 392 { 393 struct tegra_gpio *gpio = gpiochip_get_data(chip); 394 unsigned int port, pin, i, offset = 0; 395 396 if (WARN_ON(chip->of_gpio_n_cells < 2)) 397 return -EINVAL; 398 399 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells)) 400 return -EINVAL; 401 402 port = spec->args[0] / 8; 403 pin = spec->args[0] % 8; 404 405 if (port >= gpio->soc->num_ports) { 406 dev_err(chip->parent, "invalid port number: %u\n", port); 407 return -EINVAL; 408 } 409 410 for (i = 0; i < port; i++) 411 offset += gpio->soc->ports[i].pins; 412 413 if (flags) 414 *flags = spec->args[1]; 415 416 return offset + pin; 417 } 418 419 #define to_tegra_gpio(x) container_of((x), struct tegra_gpio, gpio) 420 421 static void tegra186_irq_ack(struct irq_data *data) 422 { 423 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 424 struct tegra_gpio *gpio = to_tegra_gpio(gc); 425 void __iomem *base; 426 427 base = tegra186_gpio_get_base(gpio, data->hwirq); 428 if (WARN_ON(base == NULL)) 429 return; 430 431 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR); 432 } 433 434 static void tegra186_irq_mask(struct irq_data *data) 435 { 436 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 437 struct tegra_gpio *gpio = to_tegra_gpio(gc); 438 void __iomem *base; 439 u32 value; 440 441 base = tegra186_gpio_get_base(gpio, data->hwirq); 442 if (WARN_ON(base == NULL)) 443 return; 444 445 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 446 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; 447 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 448 449 gpiochip_disable_irq(&gpio->gpio, data->hwirq); 450 } 451 452 static void tegra186_irq_unmask(struct irq_data *data) 453 { 454 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 455 struct tegra_gpio *gpio = to_tegra_gpio(gc); 456 void __iomem *base; 457 u32 value; 458 459 base = tegra186_gpio_get_base(gpio, data->hwirq); 460 if (WARN_ON(base == NULL)) 461 return; 462 463 gpiochip_enable_irq(&gpio->gpio, data->hwirq); 464 465 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 466 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; 467 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 468 } 469 470 static int tegra186_irq_set_type(struct irq_data *data, unsigned int type) 471 { 472 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 473 struct tegra_gpio *gpio = to_tegra_gpio(gc); 474 void __iomem *base; 475 u32 value; 476 477 base = tegra186_gpio_get_base(gpio, data->hwirq); 478 if (WARN_ON(base == NULL)) 479 return -ENODEV; 480 481 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 482 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK; 483 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 484 485 switch (type & IRQ_TYPE_SENSE_MASK) { 486 case IRQ_TYPE_NONE: 487 break; 488 489 case IRQ_TYPE_EDGE_RISING: 490 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 491 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 492 break; 493 494 case IRQ_TYPE_EDGE_FALLING: 495 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 496 break; 497 498 case IRQ_TYPE_EDGE_BOTH: 499 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; 500 break; 501 502 case IRQ_TYPE_LEVEL_HIGH: 503 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; 504 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 505 break; 506 507 case IRQ_TYPE_LEVEL_LOW: 508 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; 509 break; 510 511 default: 512 return -EINVAL; 513 } 514 515 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 516 517 if ((type & IRQ_TYPE_EDGE_BOTH) == 0) 518 irq_set_handler_locked(data, handle_level_irq); 519 else 520 irq_set_handler_locked(data, handle_edge_irq); 521 522 if (data->parent_data) 523 return irq_chip_set_type_parent(data, type); 524 525 return 0; 526 } 527 528 static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on) 529 { 530 if (data->parent_data) 531 return irq_chip_set_wake_parent(data, on); 532 533 return 0; 534 } 535 536 static void tegra186_irq_print_chip(struct irq_data *data, struct seq_file *p) 537 { 538 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 539 540 seq_printf(p, dev_name(gc->parent)); 541 } 542 543 static const struct irq_chip tegra186_gpio_irq_chip = { 544 .irq_ack = tegra186_irq_ack, 545 .irq_mask = tegra186_irq_mask, 546 .irq_unmask = tegra186_irq_unmask, 547 .irq_set_type = tegra186_irq_set_type, 548 .irq_set_wake = tegra186_irq_set_wake, 549 .irq_print_chip = tegra186_irq_print_chip, 550 .flags = IRQCHIP_IMMUTABLE, 551 GPIOCHIP_IRQ_RESOURCE_HELPERS, 552 }; 553 554 static void tegra186_gpio_irq(struct irq_desc *desc) 555 { 556 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc); 557 struct irq_domain *domain = gpio->gpio.irq.domain; 558 struct irq_chip *chip = irq_desc_get_chip(desc); 559 unsigned int parent = irq_desc_get_irq(desc); 560 unsigned int i, j, offset = 0; 561 562 chained_irq_enter(chip, desc); 563 564 for (i = 0; i < gpio->soc->num_ports; i++) { 565 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 566 unsigned int pin; 567 unsigned long value; 568 void __iomem *base; 569 570 base = gpio->base + port->bank * 0x1000 + port->port * 0x200; 571 572 /* skip ports that are not associated with this bank */ 573 for (j = 0; j < gpio->num_irqs_per_bank; j++) { 574 if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j]) 575 break; 576 } 577 578 if (j == gpio->num_irqs_per_bank) 579 goto skip; 580 581 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1)); 582 583 for_each_set_bit(pin, &value, port->pins) { 584 int ret = generic_handle_domain_irq(domain, offset + pin); 585 WARN_RATELIMIT(ret, "hwirq = %d", offset + pin); 586 } 587 588 skip: 589 offset += port->pins; 590 } 591 592 chained_irq_exit(chip, desc); 593 } 594 595 static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain, 596 struct irq_fwspec *fwspec, 597 unsigned long *hwirq, 598 unsigned int *type) 599 { 600 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data); 601 unsigned int port, pin, i, offset = 0; 602 603 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2)) 604 return -EINVAL; 605 606 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells)) 607 return -EINVAL; 608 609 port = fwspec->param[0] / 8; 610 pin = fwspec->param[0] % 8; 611 612 if (port >= gpio->soc->num_ports) 613 return -EINVAL; 614 615 for (i = 0; i < port; i++) 616 offset += gpio->soc->ports[i].pins; 617 618 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; 619 *hwirq = offset + pin; 620 621 return 0; 622 } 623 624 static void *tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip, 625 unsigned int parent_hwirq, 626 unsigned int parent_type) 627 { 628 struct tegra_gpio *gpio = gpiochip_get_data(chip); 629 struct irq_fwspec *fwspec; 630 631 fwspec = kmalloc(sizeof(*fwspec), GFP_KERNEL); 632 if (!fwspec) 633 return NULL; 634 635 fwspec->fwnode = chip->irq.parent_domain->fwnode; 636 fwspec->param_count = 3; 637 fwspec->param[0] = gpio->soc->instance; 638 fwspec->param[1] = parent_hwirq; 639 fwspec->param[2] = parent_type; 640 641 return fwspec; 642 } 643 644 static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip, 645 unsigned int hwirq, 646 unsigned int type, 647 unsigned int *parent_hwirq, 648 unsigned int *parent_type) 649 { 650 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq); 651 *parent_type = type; 652 653 return 0; 654 } 655 656 static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip, 657 unsigned int offset) 658 { 659 struct tegra_gpio *gpio = gpiochip_get_data(chip); 660 unsigned int i; 661 662 for (i = 0; i < gpio->soc->num_ports; i++) { 663 if (offset < gpio->soc->ports[i].pins) 664 break; 665 666 offset -= gpio->soc->ports[i].pins; 667 } 668 669 return offset + i * 8; 670 } 671 672 static const struct of_device_id tegra186_pmc_of_match[] = { 673 { .compatible = "nvidia,tegra186-pmc" }, 674 { .compatible = "nvidia,tegra194-pmc" }, 675 { /* sentinel */ } 676 }; 677 678 static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio) 679 { 680 struct device *dev = gpio->gpio.parent; 681 unsigned int i, j; 682 u32 value; 683 684 for (i = 0; i < gpio->soc->num_ports; i++) { 685 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 686 unsigned int offset, p = port->port; 687 void __iomem *base; 688 689 base = gpio->secure + port->bank * 0x1000 + 0x800; 690 691 value = readl(base + TEGRA186_GPIO_CTL_SCR); 692 693 /* 694 * For controllers that haven't been locked down yet, make 695 * sure to program the default interrupt route mapping. 696 */ 697 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 && 698 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) { 699 /* 700 * On Tegra194 and later, each pin can be routed to one or more 701 * interrupts. 702 */ 703 for (j = 0; j < gpio->num_irqs_per_bank; j++) { 704 dev_dbg(dev, "programming default interrupt routing for port %s\n", 705 port->name); 706 707 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, j); 708 709 /* 710 * By default we only want to route GPIO pins to IRQ 0. This works 711 * only under the assumption that we're running as the host kernel 712 * and hence all GPIO pins are owned by Linux. 713 * 714 * For cases where Linux is the guest OS, the hypervisor will have 715 * to configure the interrupt routing and pass only the valid 716 * interrupts via device tree. 717 */ 718 if (j == 0) { 719 value = readl(base + offset); 720 value = BIT(port->pins) - 1; 721 writel(value, base + offset); 722 } 723 } 724 } 725 } 726 } 727 728 static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio) 729 { 730 struct device *dev = gpio->gpio.parent; 731 732 if (gpio->num_irq > gpio->num_banks) { 733 if (gpio->num_irq % gpio->num_banks != 0) 734 goto error; 735 } 736 737 if (gpio->num_irq < gpio->num_banks) 738 goto error; 739 740 gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks; 741 742 if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank) 743 goto error; 744 745 return 0; 746 747 error: 748 dev_err(dev, "invalid number of interrupts (%u) for %u banks\n", 749 gpio->num_irq, gpio->num_banks); 750 return -EINVAL; 751 } 752 753 static int tegra186_gpio_probe(struct platform_device *pdev) 754 { 755 unsigned int i, j, offset; 756 struct gpio_irq_chip *irq; 757 struct tegra_gpio *gpio; 758 struct device_node *np; 759 char **names; 760 int err; 761 762 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 763 if (!gpio) 764 return -ENOMEM; 765 766 gpio->soc = device_get_match_data(&pdev->dev); 767 gpio->gpio.label = gpio->soc->name; 768 gpio->gpio.parent = &pdev->dev; 769 770 /* count the number of banks in the controller */ 771 for (i = 0; i < gpio->soc->num_ports; i++) 772 if (gpio->soc->ports[i].bank > gpio->num_banks) 773 gpio->num_banks = gpio->soc->ports[i].bank; 774 775 gpio->num_banks++; 776 777 /* get register apertures */ 778 gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security"); 779 if (IS_ERR(gpio->secure)) { 780 gpio->secure = devm_platform_ioremap_resource(pdev, 0); 781 if (IS_ERR(gpio->secure)) 782 return PTR_ERR(gpio->secure); 783 } 784 785 gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio"); 786 if (IS_ERR(gpio->base)) { 787 gpio->base = devm_platform_ioremap_resource(pdev, 1); 788 if (IS_ERR(gpio->base)) 789 return PTR_ERR(gpio->base); 790 } 791 792 err = platform_irq_count(pdev); 793 if (err < 0) 794 return err; 795 796 gpio->num_irq = err; 797 798 err = tegra186_gpio_irqs_per_bank(gpio); 799 if (err < 0) 800 return err; 801 802 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq), 803 GFP_KERNEL); 804 if (!gpio->irq) 805 return -ENOMEM; 806 807 for (i = 0; i < gpio->num_irq; i++) { 808 err = platform_get_irq(pdev, i); 809 if (err < 0) 810 return err; 811 812 gpio->irq[i] = err; 813 } 814 815 gpio->gpio.request = gpiochip_generic_request; 816 gpio->gpio.free = gpiochip_generic_free; 817 gpio->gpio.get_direction = tegra186_gpio_get_direction; 818 gpio->gpio.direction_input = tegra186_gpio_direction_input; 819 gpio->gpio.direction_output = tegra186_gpio_direction_output; 820 gpio->gpio.get = tegra186_gpio_get; 821 gpio->gpio.set = tegra186_gpio_set; 822 gpio->gpio.set_config = tegra186_gpio_set_config; 823 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges; 824 if (gpio->soc->has_gte) { 825 gpio->gpio.en_hw_timestamp = tegra186_gpio_en_hw_ts; 826 gpio->gpio.dis_hw_timestamp = tegra186_gpio_dis_hw_ts; 827 } 828 829 gpio->gpio.base = -1; 830 831 for (i = 0; i < gpio->soc->num_ports; i++) 832 gpio->gpio.ngpio += gpio->soc->ports[i].pins; 833 834 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio, 835 sizeof(*names), GFP_KERNEL); 836 if (!names) 837 return -ENOMEM; 838 839 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { 840 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 841 char *name; 842 843 for (j = 0; j < port->pins; j++) { 844 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL, 845 "P%s.%02x", port->name, j); 846 if (!name) 847 return -ENOMEM; 848 849 names[offset + j] = name; 850 } 851 852 offset += port->pins; 853 } 854 855 gpio->gpio.names = (const char * const *)names; 856 857 #if defined(CONFIG_OF_GPIO) 858 gpio->gpio.of_gpio_n_cells = 2; 859 gpio->gpio.of_xlate = tegra186_gpio_of_xlate; 860 #endif /* CONFIG_OF_GPIO */ 861 862 irq = &gpio->gpio.irq; 863 gpio_irq_chip_set_chip(irq, &tegra186_gpio_irq_chip); 864 irq->fwnode = of_node_to_fwnode(pdev->dev.of_node); 865 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq; 866 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec; 867 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq; 868 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate; 869 irq->handler = handle_simple_irq; 870 irq->default_type = IRQ_TYPE_NONE; 871 irq->parent_handler = tegra186_gpio_irq; 872 irq->parent_handler_data = gpio; 873 irq->num_parents = gpio->num_irq; 874 875 /* 876 * To simplify things, use a single interrupt per bank for now. Some 877 * chips support up to 8 interrupts per bank, which can be useful to 878 * distribute the load and decrease the processing latency for GPIOs 879 * but it also requires a more complicated interrupt routing than we 880 * currently program. 881 */ 882 if (gpio->num_irqs_per_bank > 1) { 883 irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks, 884 sizeof(*irq->parents), GFP_KERNEL); 885 if (!irq->parents) 886 return -ENOMEM; 887 888 for (i = 0; i < gpio->num_banks; i++) 889 irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank]; 890 891 irq->num_parents = gpio->num_banks; 892 } else { 893 irq->num_parents = gpio->num_irq; 894 irq->parents = gpio->irq; 895 } 896 897 if (gpio->soc->num_irqs_per_bank > 1) 898 tegra186_gpio_init_route_mapping(gpio); 899 900 np = of_find_matching_node(NULL, tegra186_pmc_of_match); 901 if (np) { 902 irq->parent_domain = irq_find_host(np); 903 of_node_put(np); 904 905 if (!irq->parent_domain) 906 return -EPROBE_DEFER; 907 } 908 909 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio, 910 sizeof(*irq->map), GFP_KERNEL); 911 if (!irq->map) 912 return -ENOMEM; 913 914 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { 915 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 916 917 for (j = 0; j < port->pins; j++) 918 irq->map[offset + j] = irq->parents[port->bank]; 919 920 offset += port->pins; 921 } 922 923 return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio); 924 } 925 926 #define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 927 [TEGRA186_MAIN_GPIO_PORT_##_name] = { \ 928 .name = #_name, \ 929 .bank = _bank, \ 930 .port = _port, \ 931 .pins = _pins, \ 932 } 933 934 static const struct tegra_gpio_port tegra186_main_ports[] = { 935 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7), 936 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7), 937 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7), 938 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6), 939 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8), 940 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6), 941 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6), 942 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7), 943 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8), 944 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8), 945 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1), 946 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8), 947 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6), 948 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7), 949 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4), 950 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7), 951 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6), 952 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6), 953 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4), 954 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8), 955 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7), 956 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2), 957 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4), 958 }; 959 960 static const struct tegra_gpio_soc tegra186_main_soc = { 961 .num_ports = ARRAY_SIZE(tegra186_main_ports), 962 .ports = tegra186_main_ports, 963 .name = "tegra186-gpio", 964 .instance = 0, 965 .num_irqs_per_bank = 1, 966 }; 967 968 #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 969 [TEGRA186_AON_GPIO_PORT_##_name] = { \ 970 .name = #_name, \ 971 .bank = _bank, \ 972 .port = _port, \ 973 .pins = _pins, \ 974 } 975 976 static const struct tegra_gpio_port tegra186_aon_ports[] = { 977 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5), 978 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6), 979 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8), 980 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8), 981 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4), 982 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8), 983 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3), 984 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5), 985 }; 986 987 static const struct tegra_gpio_soc tegra186_aon_soc = { 988 .num_ports = ARRAY_SIZE(tegra186_aon_ports), 989 .ports = tegra186_aon_ports, 990 .name = "tegra186-gpio-aon", 991 .instance = 1, 992 .num_irqs_per_bank = 1, 993 }; 994 995 #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 996 [TEGRA194_MAIN_GPIO_PORT_##_name] = { \ 997 .name = #_name, \ 998 .bank = _bank, \ 999 .port = _port, \ 1000 .pins = _pins, \ 1001 } 1002 1003 static const struct tegra_gpio_port tegra194_main_ports[] = { 1004 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8), 1005 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2), 1006 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8), 1007 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4), 1008 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8), 1009 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6), 1010 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8), 1011 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8), 1012 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5), 1013 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6), 1014 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8), 1015 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4), 1016 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8), 1017 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3), 1018 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6), 1019 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8), 1020 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8), 1021 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6), 1022 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8), 1023 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8), 1024 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1), 1025 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8), 1026 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2), 1027 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8), 1028 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8), 1029 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8), 1030 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2), 1031 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2) 1032 }; 1033 1034 static const struct tegra186_pin_range tegra194_main_pin_ranges[] = { 1035 { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" }, 1036 { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" }, 1037 }; 1038 1039 static const struct tegra_gpio_soc tegra194_main_soc = { 1040 .num_ports = ARRAY_SIZE(tegra194_main_ports), 1041 .ports = tegra194_main_ports, 1042 .name = "tegra194-gpio", 1043 .instance = 0, 1044 .num_irqs_per_bank = 8, 1045 .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges), 1046 .pin_ranges = tegra194_main_pin_ranges, 1047 .pinmux = "nvidia,tegra194-pinmux", 1048 }; 1049 1050 #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1051 [TEGRA194_AON_GPIO_PORT_##_name] = { \ 1052 .name = #_name, \ 1053 .bank = _bank, \ 1054 .port = _port, \ 1055 .pins = _pins, \ 1056 } 1057 1058 static const struct tegra_gpio_port tegra194_aon_ports[] = { 1059 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8), 1060 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4), 1061 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8), 1062 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3), 1063 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7) 1064 }; 1065 1066 static const struct tegra_gpio_soc tegra194_aon_soc = { 1067 .num_ports = ARRAY_SIZE(tegra194_aon_ports), 1068 .ports = tegra194_aon_ports, 1069 .name = "tegra194-gpio-aon", 1070 .instance = 1, 1071 .num_irqs_per_bank = 8, 1072 .has_gte = true, 1073 }; 1074 1075 #define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1076 [TEGRA234_MAIN_GPIO_PORT_##_name] = { \ 1077 .name = #_name, \ 1078 .bank = _bank, \ 1079 .port = _port, \ 1080 .pins = _pins, \ 1081 } 1082 1083 static const struct tegra_gpio_port tegra234_main_ports[] = { 1084 TEGRA234_MAIN_GPIO_PORT( A, 0, 0, 8), 1085 TEGRA234_MAIN_GPIO_PORT( B, 0, 3, 1), 1086 TEGRA234_MAIN_GPIO_PORT( C, 5, 1, 8), 1087 TEGRA234_MAIN_GPIO_PORT( D, 5, 2, 4), 1088 TEGRA234_MAIN_GPIO_PORT( E, 5, 3, 8), 1089 TEGRA234_MAIN_GPIO_PORT( F, 5, 4, 6), 1090 TEGRA234_MAIN_GPIO_PORT( G, 4, 0, 8), 1091 TEGRA234_MAIN_GPIO_PORT( H, 4, 1, 8), 1092 TEGRA234_MAIN_GPIO_PORT( I, 4, 2, 7), 1093 TEGRA234_MAIN_GPIO_PORT( J, 5, 0, 6), 1094 TEGRA234_MAIN_GPIO_PORT( K, 3, 0, 8), 1095 TEGRA234_MAIN_GPIO_PORT( L, 3, 1, 4), 1096 TEGRA234_MAIN_GPIO_PORT( M, 2, 0, 8), 1097 TEGRA234_MAIN_GPIO_PORT( N, 2, 1, 8), 1098 TEGRA234_MAIN_GPIO_PORT( P, 2, 2, 8), 1099 TEGRA234_MAIN_GPIO_PORT( Q, 2, 3, 8), 1100 TEGRA234_MAIN_GPIO_PORT( R, 2, 4, 6), 1101 TEGRA234_MAIN_GPIO_PORT( X, 1, 0, 8), 1102 TEGRA234_MAIN_GPIO_PORT( Y, 1, 1, 8), 1103 TEGRA234_MAIN_GPIO_PORT( Z, 1, 2, 8), 1104 TEGRA234_MAIN_GPIO_PORT(AC, 0, 1, 8), 1105 TEGRA234_MAIN_GPIO_PORT(AD, 0, 2, 4), 1106 TEGRA234_MAIN_GPIO_PORT(AE, 3, 3, 2), 1107 TEGRA234_MAIN_GPIO_PORT(AF, 3, 4, 4), 1108 TEGRA234_MAIN_GPIO_PORT(AG, 3, 2, 8), 1109 }; 1110 1111 static const struct tegra_gpio_soc tegra234_main_soc = { 1112 .num_ports = ARRAY_SIZE(tegra234_main_ports), 1113 .ports = tegra234_main_ports, 1114 .name = "tegra234-gpio", 1115 .instance = 0, 1116 .num_irqs_per_bank = 8, 1117 }; 1118 1119 #define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1120 [TEGRA234_AON_GPIO_PORT_##_name] = { \ 1121 .name = #_name, \ 1122 .bank = _bank, \ 1123 .port = _port, \ 1124 .pins = _pins, \ 1125 } 1126 1127 static const struct tegra_gpio_port tegra234_aon_ports[] = { 1128 TEGRA234_AON_GPIO_PORT(AA, 0, 4, 8), 1129 TEGRA234_AON_GPIO_PORT(BB, 0, 5, 4), 1130 TEGRA234_AON_GPIO_PORT(CC, 0, 2, 8), 1131 TEGRA234_AON_GPIO_PORT(DD, 0, 3, 3), 1132 TEGRA234_AON_GPIO_PORT(EE, 0, 0, 8), 1133 TEGRA234_AON_GPIO_PORT(GG, 0, 1, 1), 1134 }; 1135 1136 static const struct tegra_gpio_soc tegra234_aon_soc = { 1137 .num_ports = ARRAY_SIZE(tegra234_aon_ports), 1138 .ports = tegra234_aon_ports, 1139 .name = "tegra234-gpio-aon", 1140 .instance = 1, 1141 .num_irqs_per_bank = 8, 1142 }; 1143 1144 #define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1145 [TEGRA241_MAIN_GPIO_PORT_##_name] = { \ 1146 .name = #_name, \ 1147 .bank = _bank, \ 1148 .port = _port, \ 1149 .pins = _pins, \ 1150 } 1151 1152 static const struct tegra_gpio_port tegra241_main_ports[] = { 1153 TEGRA241_MAIN_GPIO_PORT(A, 0, 0, 8), 1154 TEGRA241_MAIN_GPIO_PORT(B, 0, 1, 8), 1155 TEGRA241_MAIN_GPIO_PORT(C, 0, 2, 2), 1156 TEGRA241_MAIN_GPIO_PORT(D, 0, 3, 6), 1157 TEGRA241_MAIN_GPIO_PORT(E, 0, 4, 8), 1158 TEGRA241_MAIN_GPIO_PORT(F, 1, 0, 8), 1159 TEGRA241_MAIN_GPIO_PORT(G, 1, 1, 8), 1160 TEGRA241_MAIN_GPIO_PORT(H, 1, 2, 8), 1161 TEGRA241_MAIN_GPIO_PORT(J, 1, 3, 8), 1162 TEGRA241_MAIN_GPIO_PORT(K, 1, 4, 4), 1163 TEGRA241_MAIN_GPIO_PORT(L, 1, 5, 6), 1164 }; 1165 1166 static const struct tegra_gpio_soc tegra241_main_soc = { 1167 .num_ports = ARRAY_SIZE(tegra241_main_ports), 1168 .ports = tegra241_main_ports, 1169 .name = "tegra241-gpio", 1170 .instance = 0, 1171 .num_irqs_per_bank = 8, 1172 }; 1173 1174 #define TEGRA241_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1175 [TEGRA241_AON_GPIO_PORT_##_name] = { \ 1176 .name = #_name, \ 1177 .bank = _bank, \ 1178 .port = _port, \ 1179 .pins = _pins, \ 1180 } 1181 1182 static const struct tegra_gpio_port tegra241_aon_ports[] = { 1183 TEGRA241_AON_GPIO_PORT(AA, 0, 0, 8), 1184 TEGRA241_AON_GPIO_PORT(BB, 0, 0, 4), 1185 }; 1186 1187 static const struct tegra_gpio_soc tegra241_aon_soc = { 1188 .num_ports = ARRAY_SIZE(tegra241_aon_ports), 1189 .ports = tegra241_aon_ports, 1190 .name = "tegra241-gpio-aon", 1191 .instance = 1, 1192 .num_irqs_per_bank = 8, 1193 }; 1194 1195 static const struct of_device_id tegra186_gpio_of_match[] = { 1196 { 1197 .compatible = "nvidia,tegra186-gpio", 1198 .data = &tegra186_main_soc 1199 }, { 1200 .compatible = "nvidia,tegra186-gpio-aon", 1201 .data = &tegra186_aon_soc 1202 }, { 1203 .compatible = "nvidia,tegra194-gpio", 1204 .data = &tegra194_main_soc 1205 }, { 1206 .compatible = "nvidia,tegra194-gpio-aon", 1207 .data = &tegra194_aon_soc 1208 }, { 1209 .compatible = "nvidia,tegra234-gpio", 1210 .data = &tegra234_main_soc 1211 }, { 1212 .compatible = "nvidia,tegra234-gpio-aon", 1213 .data = &tegra234_aon_soc 1214 }, { 1215 /* sentinel */ 1216 } 1217 }; 1218 MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match); 1219 1220 static const struct acpi_device_id tegra186_gpio_acpi_match[] = { 1221 { .id = "NVDA0108", .driver_data = (kernel_ulong_t)&tegra186_main_soc }, 1222 { .id = "NVDA0208", .driver_data = (kernel_ulong_t)&tegra186_aon_soc }, 1223 { .id = "NVDA0308", .driver_data = (kernel_ulong_t)&tegra194_main_soc }, 1224 { .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc }, 1225 { .id = "NVDA0508", .driver_data = (kernel_ulong_t)&tegra241_main_soc }, 1226 { .id = "NVDA0608", .driver_data = (kernel_ulong_t)&tegra241_aon_soc }, 1227 {} 1228 }; 1229 MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match); 1230 1231 static struct platform_driver tegra186_gpio_driver = { 1232 .driver = { 1233 .name = "tegra186-gpio", 1234 .of_match_table = tegra186_gpio_of_match, 1235 .acpi_match_table = tegra186_gpio_acpi_match, 1236 }, 1237 .probe = tegra186_gpio_probe, 1238 }; 1239 module_platform_driver(tegra186_gpio_driver); 1240 1241 MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver"); 1242 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 1243 MODULE_LICENSE("GPL v2"); 1244