1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016-2017 NVIDIA Corporation 4 * 5 * Author: Thierry Reding <treding@nvidia.com> 6 */ 7 8 #include <linux/gpio/driver.h> 9 #include <linux/interrupt.h> 10 #include <linux/irq.h> 11 #include <linux/module.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 15 #include <dt-bindings/gpio/tegra186-gpio.h> 16 #include <dt-bindings/gpio/tegra194-gpio.h> 17 18 /* security registers */ 19 #define TEGRA186_GPIO_CTL_SCR 0x0c 20 #define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28) 21 #define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27) 22 23 #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4) 24 25 /* control registers */ 26 #define TEGRA186_GPIO_ENABLE_CONFIG 0x00 27 #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0) 28 #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1) 29 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2) 30 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2) 31 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2) 32 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2) 33 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2) 34 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4) 35 #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5) 36 #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6) 37 38 #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04 39 #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff) 40 41 #define TEGRA186_GPIO_INPUT 0x08 42 #define TEGRA186_GPIO_INPUT_HIGH BIT(0) 43 44 #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c 45 #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0) 46 47 #define TEGRA186_GPIO_OUTPUT_VALUE 0x10 48 #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0) 49 50 #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14 51 52 #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4) 53 54 struct tegra_gpio_port { 55 const char *name; 56 unsigned int bank; 57 unsigned int port; 58 unsigned int pins; 59 }; 60 61 struct tegra186_pin_range { 62 unsigned int offset; 63 const char *group; 64 }; 65 66 struct tegra_gpio_soc { 67 const struct tegra_gpio_port *ports; 68 unsigned int num_ports; 69 const char *name; 70 unsigned int instance; 71 72 const struct tegra186_pin_range *pin_ranges; 73 unsigned int num_pin_ranges; 74 const char *pinmux; 75 }; 76 77 struct tegra_gpio { 78 struct gpio_chip gpio; 79 struct irq_chip intc; 80 unsigned int num_irq; 81 unsigned int *irq; 82 83 const struct tegra_gpio_soc *soc; 84 85 void __iomem *secure; 86 void __iomem *base; 87 }; 88 89 static const struct tegra_gpio_port * 90 tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin) 91 { 92 unsigned int start = 0, i; 93 94 for (i = 0; i < gpio->soc->num_ports; i++) { 95 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 96 97 if (*pin >= start && *pin < start + port->pins) { 98 *pin -= start; 99 return port; 100 } 101 102 start += port->pins; 103 } 104 105 return NULL; 106 } 107 108 static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio, 109 unsigned int pin) 110 { 111 const struct tegra_gpio_port *port; 112 unsigned int offset; 113 114 port = tegra186_gpio_get_port(gpio, &pin); 115 if (!port) 116 return NULL; 117 118 offset = port->bank * 0x1000 + port->port * 0x200; 119 120 return gpio->base + offset + pin * 0x20; 121 } 122 123 static int tegra186_gpio_get_direction(struct gpio_chip *chip, 124 unsigned int offset) 125 { 126 struct tegra_gpio *gpio = gpiochip_get_data(chip); 127 void __iomem *base; 128 u32 value; 129 130 base = tegra186_gpio_get_base(gpio, offset); 131 if (WARN_ON(base == NULL)) 132 return -ENODEV; 133 134 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 135 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) 136 return GPIO_LINE_DIRECTION_OUT; 137 138 return GPIO_LINE_DIRECTION_IN; 139 } 140 141 static int tegra186_gpio_direction_input(struct gpio_chip *chip, 142 unsigned int offset) 143 { 144 struct tegra_gpio *gpio = gpiochip_get_data(chip); 145 void __iomem *base; 146 u32 value; 147 148 base = tegra186_gpio_get_base(gpio, offset); 149 if (WARN_ON(base == NULL)) 150 return -ENODEV; 151 152 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); 153 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; 154 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); 155 156 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 157 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; 158 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT; 159 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 160 161 return 0; 162 } 163 164 static int tegra186_gpio_direction_output(struct gpio_chip *chip, 165 unsigned int offset, int level) 166 { 167 struct tegra_gpio *gpio = gpiochip_get_data(chip); 168 void __iomem *base; 169 u32 value; 170 171 /* configure output level first */ 172 chip->set(chip, offset, level); 173 174 base = tegra186_gpio_get_base(gpio, offset); 175 if (WARN_ON(base == NULL)) 176 return -EINVAL; 177 178 /* set the direction */ 179 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); 180 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; 181 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); 182 183 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 184 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; 185 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT; 186 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 187 188 return 0; 189 } 190 191 static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset) 192 { 193 struct tegra_gpio *gpio = gpiochip_get_data(chip); 194 void __iomem *base; 195 u32 value; 196 197 base = tegra186_gpio_get_base(gpio, offset); 198 if (WARN_ON(base == NULL)) 199 return -ENODEV; 200 201 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 202 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) 203 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); 204 else 205 value = readl(base + TEGRA186_GPIO_INPUT); 206 207 return value & BIT(0); 208 } 209 210 static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset, 211 int level) 212 { 213 struct tegra_gpio *gpio = gpiochip_get_data(chip); 214 void __iomem *base; 215 u32 value; 216 217 base = tegra186_gpio_get_base(gpio, offset); 218 if (WARN_ON(base == NULL)) 219 return; 220 221 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); 222 if (level == 0) 223 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH; 224 else 225 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH; 226 227 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE); 228 } 229 230 static int tegra186_gpio_set_config(struct gpio_chip *chip, 231 unsigned int offset, 232 unsigned long config) 233 { 234 struct tegra_gpio *gpio = gpiochip_get_data(chip); 235 u32 debounce, value; 236 void __iomem *base; 237 238 base = tegra186_gpio_get_base(gpio, offset); 239 if (base == NULL) 240 return -ENXIO; 241 242 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 243 return -ENOTSUPP; 244 245 debounce = pinconf_to_config_argument(config); 246 247 /* 248 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce 249 * time. 250 */ 251 if (debounce > 255000) 252 return -EINVAL; 253 254 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC); 255 256 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce); 257 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL); 258 259 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 260 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE; 261 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 262 263 return 0; 264 } 265 266 static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip) 267 { 268 struct tegra_gpio *gpio = gpiochip_get_data(chip); 269 struct pinctrl_dev *pctldev; 270 struct device_node *np; 271 unsigned int i, j; 272 int err; 273 274 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0) 275 return 0; 276 277 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux); 278 if (!np) 279 return -ENODEV; 280 281 pctldev = of_pinctrl_get(np); 282 of_node_put(np); 283 if (!pctldev) 284 return -EPROBE_DEFER; 285 286 for (i = 0; i < gpio->soc->num_pin_ranges; i++) { 287 unsigned int pin = gpio->soc->pin_ranges[i].offset, port; 288 const char *group = gpio->soc->pin_ranges[i].group; 289 290 port = pin / 8; 291 pin = pin % 8; 292 293 if (port >= gpio->soc->num_ports) { 294 dev_warn(chip->parent, "invalid port %u for %s\n", 295 port, group); 296 continue; 297 } 298 299 for (j = 0; j < port; j++) 300 pin += gpio->soc->ports[j].pins; 301 302 err = gpiochip_add_pingroup_range(chip, pctldev, pin, group); 303 if (err < 0) 304 return err; 305 } 306 307 return 0; 308 } 309 310 static int tegra186_gpio_of_xlate(struct gpio_chip *chip, 311 const struct of_phandle_args *spec, 312 u32 *flags) 313 { 314 struct tegra_gpio *gpio = gpiochip_get_data(chip); 315 unsigned int port, pin, i, offset = 0; 316 317 if (WARN_ON(chip->of_gpio_n_cells < 2)) 318 return -EINVAL; 319 320 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells)) 321 return -EINVAL; 322 323 port = spec->args[0] / 8; 324 pin = spec->args[0] % 8; 325 326 if (port >= gpio->soc->num_ports) { 327 dev_err(chip->parent, "invalid port number: %u\n", port); 328 return -EINVAL; 329 } 330 331 for (i = 0; i < port; i++) 332 offset += gpio->soc->ports[i].pins; 333 334 if (flags) 335 *flags = spec->args[1]; 336 337 return offset + pin; 338 } 339 340 static void tegra186_irq_ack(struct irq_data *data) 341 { 342 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); 343 void __iomem *base; 344 345 base = tegra186_gpio_get_base(gpio, data->hwirq); 346 if (WARN_ON(base == NULL)) 347 return; 348 349 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR); 350 } 351 352 static void tegra186_irq_mask(struct irq_data *data) 353 { 354 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); 355 void __iomem *base; 356 u32 value; 357 358 base = tegra186_gpio_get_base(gpio, data->hwirq); 359 if (WARN_ON(base == NULL)) 360 return; 361 362 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 363 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; 364 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 365 } 366 367 static void tegra186_irq_unmask(struct irq_data *data) 368 { 369 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); 370 void __iomem *base; 371 u32 value; 372 373 base = tegra186_gpio_get_base(gpio, data->hwirq); 374 if (WARN_ON(base == NULL)) 375 return; 376 377 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 378 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; 379 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 380 } 381 382 static int tegra186_irq_set_type(struct irq_data *data, unsigned int type) 383 { 384 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); 385 void __iomem *base; 386 u32 value; 387 388 base = tegra186_gpio_get_base(gpio, data->hwirq); 389 if (WARN_ON(base == NULL)) 390 return -ENODEV; 391 392 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 393 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK; 394 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 395 396 switch (type & IRQ_TYPE_SENSE_MASK) { 397 case IRQ_TYPE_NONE: 398 break; 399 400 case IRQ_TYPE_EDGE_RISING: 401 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 402 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 403 break; 404 405 case IRQ_TYPE_EDGE_FALLING: 406 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 407 break; 408 409 case IRQ_TYPE_EDGE_BOTH: 410 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; 411 break; 412 413 case IRQ_TYPE_LEVEL_HIGH: 414 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; 415 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 416 break; 417 418 case IRQ_TYPE_LEVEL_LOW: 419 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; 420 break; 421 422 default: 423 return -EINVAL; 424 } 425 426 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 427 428 if ((type & IRQ_TYPE_EDGE_BOTH) == 0) 429 irq_set_handler_locked(data, handle_level_irq); 430 else 431 irq_set_handler_locked(data, handle_edge_irq); 432 433 return irq_chip_set_type_parent(data, type); 434 } 435 436 static void tegra186_gpio_irq(struct irq_desc *desc) 437 { 438 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc); 439 struct irq_domain *domain = gpio->gpio.irq.domain; 440 struct irq_chip *chip = irq_desc_get_chip(desc); 441 unsigned int parent = irq_desc_get_irq(desc); 442 unsigned int i, offset = 0; 443 444 chained_irq_enter(chip, desc); 445 446 for (i = 0; i < gpio->soc->num_ports; i++) { 447 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 448 unsigned int pin, irq; 449 unsigned long value; 450 void __iomem *base; 451 452 base = gpio->base + port->bank * 0x1000 + port->port * 0x200; 453 454 /* skip ports that are not associated with this bank */ 455 if (parent != gpio->irq[port->bank]) 456 goto skip; 457 458 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1)); 459 460 for_each_set_bit(pin, &value, port->pins) { 461 irq = irq_find_mapping(domain, offset + pin); 462 if (WARN_ON(irq == 0)) 463 continue; 464 465 generic_handle_irq(irq); 466 } 467 468 skip: 469 offset += port->pins; 470 } 471 472 chained_irq_exit(chip, desc); 473 } 474 475 static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain, 476 struct irq_fwspec *fwspec, 477 unsigned long *hwirq, 478 unsigned int *type) 479 { 480 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data); 481 unsigned int port, pin, i, offset = 0; 482 483 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2)) 484 return -EINVAL; 485 486 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells)) 487 return -EINVAL; 488 489 port = fwspec->param[0] / 8; 490 pin = fwspec->param[0] % 8; 491 492 if (port >= gpio->soc->num_ports) 493 return -EINVAL; 494 495 for (i = 0; i < port; i++) 496 offset += gpio->soc->ports[i].pins; 497 498 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; 499 *hwirq = offset + pin; 500 501 return 0; 502 } 503 504 static void *tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip, 505 unsigned int parent_hwirq, 506 unsigned int parent_type) 507 { 508 struct tegra_gpio *gpio = gpiochip_get_data(chip); 509 struct irq_fwspec *fwspec; 510 511 fwspec = kmalloc(sizeof(*fwspec), GFP_KERNEL); 512 if (!fwspec) 513 return NULL; 514 515 fwspec->fwnode = chip->irq.parent_domain->fwnode; 516 fwspec->param_count = 3; 517 fwspec->param[0] = gpio->soc->instance; 518 fwspec->param[1] = parent_hwirq; 519 fwspec->param[2] = parent_type; 520 521 return fwspec; 522 } 523 524 static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip, 525 unsigned int hwirq, 526 unsigned int type, 527 unsigned int *parent_hwirq, 528 unsigned int *parent_type) 529 { 530 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq); 531 *parent_type = type; 532 533 return 0; 534 } 535 536 static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip, 537 unsigned int offset) 538 { 539 struct tegra_gpio *gpio = gpiochip_get_data(chip); 540 unsigned int i; 541 542 for (i = 0; i < gpio->soc->num_ports; i++) { 543 if (offset < gpio->soc->ports[i].pins) 544 break; 545 546 offset -= gpio->soc->ports[i].pins; 547 } 548 549 return offset + i * 8; 550 } 551 552 static const struct of_device_id tegra186_pmc_of_match[] = { 553 { .compatible = "nvidia,tegra186-pmc" }, 554 { .compatible = "nvidia,tegra194-pmc" }, 555 { /* sentinel */ } 556 }; 557 558 static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio) 559 { 560 unsigned int i, j; 561 u32 value; 562 563 for (i = 0; i < gpio->soc->num_ports; i++) { 564 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 565 unsigned int offset, p = port->port; 566 void __iomem *base; 567 568 base = gpio->secure + port->bank * 0x1000 + 0x800; 569 570 value = readl(base + TEGRA186_GPIO_CTL_SCR); 571 572 /* 573 * For controllers that haven't been locked down yet, make 574 * sure to program the default interrupt route mapping. 575 */ 576 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 && 577 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) { 578 for (j = 0; j < 8; j++) { 579 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, j); 580 581 value = readl(base + offset); 582 value = BIT(port->pins) - 1; 583 writel(value, base + offset); 584 } 585 } 586 } 587 } 588 589 static int tegra186_gpio_probe(struct platform_device *pdev) 590 { 591 unsigned int i, j, offset; 592 struct gpio_irq_chip *irq; 593 struct tegra_gpio *gpio; 594 struct device_node *np; 595 char **names; 596 int err; 597 598 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 599 if (!gpio) 600 return -ENOMEM; 601 602 gpio->soc = of_device_get_match_data(&pdev->dev); 603 604 gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security"); 605 if (IS_ERR(gpio->secure)) 606 return PTR_ERR(gpio->secure); 607 608 gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio"); 609 if (IS_ERR(gpio->base)) 610 return PTR_ERR(gpio->base); 611 612 err = platform_irq_count(pdev); 613 if (err < 0) 614 return err; 615 616 gpio->num_irq = err; 617 618 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq), 619 GFP_KERNEL); 620 if (!gpio->irq) 621 return -ENOMEM; 622 623 for (i = 0; i < gpio->num_irq; i++) { 624 err = platform_get_irq(pdev, i); 625 if (err < 0) 626 return err; 627 628 gpio->irq[i] = err; 629 } 630 631 gpio->gpio.label = gpio->soc->name; 632 gpio->gpio.parent = &pdev->dev; 633 634 gpio->gpio.request = gpiochip_generic_request; 635 gpio->gpio.free = gpiochip_generic_free; 636 gpio->gpio.get_direction = tegra186_gpio_get_direction; 637 gpio->gpio.direction_input = tegra186_gpio_direction_input; 638 gpio->gpio.direction_output = tegra186_gpio_direction_output; 639 gpio->gpio.get = tegra186_gpio_get, 640 gpio->gpio.set = tegra186_gpio_set; 641 gpio->gpio.set_config = tegra186_gpio_set_config; 642 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges; 643 644 gpio->gpio.base = -1; 645 646 for (i = 0; i < gpio->soc->num_ports; i++) 647 gpio->gpio.ngpio += gpio->soc->ports[i].pins; 648 649 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio, 650 sizeof(*names), GFP_KERNEL); 651 if (!names) 652 return -ENOMEM; 653 654 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { 655 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 656 char *name; 657 658 for (j = 0; j < port->pins; j++) { 659 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL, 660 "P%s.%02x", port->name, j); 661 if (!name) 662 return -ENOMEM; 663 664 names[offset + j] = name; 665 } 666 667 offset += port->pins; 668 } 669 670 gpio->gpio.names = (const char * const *)names; 671 672 gpio->gpio.of_node = pdev->dev.of_node; 673 gpio->gpio.of_gpio_n_cells = 2; 674 gpio->gpio.of_xlate = tegra186_gpio_of_xlate; 675 676 gpio->intc.name = pdev->dev.of_node->name; 677 gpio->intc.irq_ack = tegra186_irq_ack; 678 gpio->intc.irq_mask = tegra186_irq_mask; 679 gpio->intc.irq_unmask = tegra186_irq_unmask; 680 gpio->intc.irq_set_type = tegra186_irq_set_type; 681 gpio->intc.irq_set_wake = irq_chip_set_wake_parent; 682 683 irq = &gpio->gpio.irq; 684 irq->chip = &gpio->intc; 685 irq->fwnode = of_node_to_fwnode(pdev->dev.of_node); 686 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq; 687 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec; 688 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq; 689 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate; 690 irq->handler = handle_simple_irq; 691 irq->default_type = IRQ_TYPE_NONE; 692 irq->parent_handler = tegra186_gpio_irq; 693 irq->parent_handler_data = gpio; 694 irq->num_parents = gpio->num_irq; 695 irq->parents = gpio->irq; 696 697 np = of_find_matching_node(NULL, tegra186_pmc_of_match); 698 if (np) { 699 irq->parent_domain = irq_find_host(np); 700 of_node_put(np); 701 702 if (!irq->parent_domain) 703 return -EPROBE_DEFER; 704 } 705 706 tegra186_gpio_init_route_mapping(gpio); 707 708 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio, 709 sizeof(*irq->map), GFP_KERNEL); 710 if (!irq->map) 711 return -ENOMEM; 712 713 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { 714 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 715 716 for (j = 0; j < port->pins; j++) 717 irq->map[offset + j] = irq->parents[port->bank]; 718 719 offset += port->pins; 720 } 721 722 platform_set_drvdata(pdev, gpio); 723 724 err = devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio); 725 if (err < 0) 726 return err; 727 728 return 0; 729 } 730 731 static int tegra186_gpio_remove(struct platform_device *pdev) 732 { 733 return 0; 734 } 735 736 #define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 737 [TEGRA186_MAIN_GPIO_PORT_##_name] = { \ 738 .name = #_name, \ 739 .bank = _bank, \ 740 .port = _port, \ 741 .pins = _pins, \ 742 } 743 744 static const struct tegra_gpio_port tegra186_main_ports[] = { 745 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7), 746 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7), 747 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7), 748 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6), 749 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8), 750 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6), 751 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6), 752 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7), 753 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8), 754 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8), 755 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1), 756 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8), 757 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6), 758 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7), 759 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4), 760 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7), 761 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6), 762 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6), 763 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4), 764 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8), 765 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7), 766 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2), 767 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4), 768 }; 769 770 static const struct tegra_gpio_soc tegra186_main_soc = { 771 .num_ports = ARRAY_SIZE(tegra186_main_ports), 772 .ports = tegra186_main_ports, 773 .name = "tegra186-gpio", 774 .instance = 0, 775 }; 776 777 #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 778 [TEGRA186_AON_GPIO_PORT_##_name] = { \ 779 .name = #_name, \ 780 .bank = _bank, \ 781 .port = _port, \ 782 .pins = _pins, \ 783 } 784 785 static const struct tegra_gpio_port tegra186_aon_ports[] = { 786 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5), 787 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6), 788 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8), 789 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8), 790 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4), 791 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8), 792 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3), 793 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5), 794 }; 795 796 static const struct tegra_gpio_soc tegra186_aon_soc = { 797 .num_ports = ARRAY_SIZE(tegra186_aon_ports), 798 .ports = tegra186_aon_ports, 799 .name = "tegra186-gpio-aon", 800 .instance = 1, 801 }; 802 803 #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 804 [TEGRA194_MAIN_GPIO_PORT_##_name] = { \ 805 .name = #_name, \ 806 .bank = _bank, \ 807 .port = _port, \ 808 .pins = _pins, \ 809 } 810 811 static const struct tegra_gpio_port tegra194_main_ports[] = { 812 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8), 813 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2), 814 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8), 815 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4), 816 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8), 817 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6), 818 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8), 819 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8), 820 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5), 821 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6), 822 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8), 823 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4), 824 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8), 825 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3), 826 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6), 827 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8), 828 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8), 829 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6), 830 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8), 831 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8), 832 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1), 833 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8), 834 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2), 835 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8), 836 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8), 837 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8), 838 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2), 839 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2) 840 }; 841 842 static const struct tegra186_pin_range tegra194_main_pin_ranges[] = { 843 { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" }, 844 { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" }, 845 }; 846 847 static const struct tegra_gpio_soc tegra194_main_soc = { 848 .num_ports = ARRAY_SIZE(tegra194_main_ports), 849 .ports = tegra194_main_ports, 850 .name = "tegra194-gpio", 851 .instance = 0, 852 .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges), 853 .pin_ranges = tegra194_main_pin_ranges, 854 .pinmux = "nvidia,tegra194-pinmux", 855 }; 856 857 #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 858 [TEGRA194_AON_GPIO_PORT_##_name] = { \ 859 .name = #_name, \ 860 .bank = _bank, \ 861 .port = _port, \ 862 .pins = _pins, \ 863 } 864 865 static const struct tegra_gpio_port tegra194_aon_ports[] = { 866 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8), 867 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4), 868 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8), 869 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3), 870 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7) 871 }; 872 873 static const struct tegra_gpio_soc tegra194_aon_soc = { 874 .num_ports = ARRAY_SIZE(tegra194_aon_ports), 875 .ports = tegra194_aon_ports, 876 .name = "tegra194-gpio-aon", 877 .instance = 1, 878 }; 879 880 static const struct of_device_id tegra186_gpio_of_match[] = { 881 { 882 .compatible = "nvidia,tegra186-gpio", 883 .data = &tegra186_main_soc 884 }, { 885 .compatible = "nvidia,tegra186-gpio-aon", 886 .data = &tegra186_aon_soc 887 }, { 888 .compatible = "nvidia,tegra194-gpio", 889 .data = &tegra194_main_soc 890 }, { 891 .compatible = "nvidia,tegra194-gpio-aon", 892 .data = &tegra194_aon_soc 893 }, { 894 /* sentinel */ 895 } 896 }; 897 MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match); 898 899 static struct platform_driver tegra186_gpio_driver = { 900 .driver = { 901 .name = "tegra186-gpio", 902 .of_match_table = tegra186_gpio_of_match, 903 }, 904 .probe = tegra186_gpio_probe, 905 .remove = tegra186_gpio_remove, 906 }; 907 module_platform_driver(tegra186_gpio_driver); 908 909 MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver"); 910 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 911 MODULE_LICENSE("GPL v2"); 912