1 /* 2 * arch/arm/mach-tegra/gpio.c 3 * 4 * Copyright (c) 2010 Google, Inc 5 * 6 * Author: 7 * Erik Gilling <konkers@google.com> 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 */ 19 20 #include <linux/init.h> 21 #include <linux/irq.h> 22 #include <linux/interrupt.h> 23 #include <linux/io.h> 24 #include <linux/gpio.h> 25 #include <linux/of_device.h> 26 #include <linux/platform_device.h> 27 #include <linux/module.h> 28 #include <linux/irqdomain.h> 29 30 #include <asm/mach/irq.h> 31 32 #include <mach/gpio-tegra.h> 33 #include <mach/iomap.h> 34 #include <mach/suspend.h> 35 36 #define GPIO_BANK(x) ((x) >> 5) 37 #define GPIO_PORT(x) (((x) >> 3) & 0x3) 38 #define GPIO_BIT(x) ((x) & 0x7) 39 40 #define GPIO_REG(x) (GPIO_BANK(x) * tegra_gpio_bank_stride + \ 41 GPIO_PORT(x) * 4) 42 43 #define GPIO_CNF(x) (GPIO_REG(x) + 0x00) 44 #define GPIO_OE(x) (GPIO_REG(x) + 0x10) 45 #define GPIO_OUT(x) (GPIO_REG(x) + 0X20) 46 #define GPIO_IN(x) (GPIO_REG(x) + 0x30) 47 #define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40) 48 #define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50) 49 #define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60) 50 #define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70) 51 52 #define GPIO_MSK_CNF(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x00) 53 #define GPIO_MSK_OE(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x10) 54 #define GPIO_MSK_OUT(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0X20) 55 #define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x40) 56 #define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x50) 57 #define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x60) 58 59 #define GPIO_INT_LVL_MASK 0x010101 60 #define GPIO_INT_LVL_EDGE_RISING 0x000101 61 #define GPIO_INT_LVL_EDGE_FALLING 0x000100 62 #define GPIO_INT_LVL_EDGE_BOTH 0x010100 63 #define GPIO_INT_LVL_LEVEL_HIGH 0x000001 64 #define GPIO_INT_LVL_LEVEL_LOW 0x000000 65 66 struct tegra_gpio_bank { 67 int bank; 68 int irq; 69 spinlock_t lvl_lock[4]; 70 #ifdef CONFIG_PM 71 u32 cnf[4]; 72 u32 out[4]; 73 u32 oe[4]; 74 u32 int_enb[4]; 75 u32 int_lvl[4]; 76 #endif 77 }; 78 79 static struct irq_domain *irq_domain; 80 static void __iomem *regs; 81 static u32 tegra_gpio_bank_count; 82 static u32 tegra_gpio_bank_stride; 83 static u32 tegra_gpio_upper_offset; 84 static struct tegra_gpio_bank *tegra_gpio_banks; 85 86 static inline void tegra_gpio_writel(u32 val, u32 reg) 87 { 88 __raw_writel(val, regs + reg); 89 } 90 91 static inline u32 tegra_gpio_readl(u32 reg) 92 { 93 return __raw_readl(regs + reg); 94 } 95 96 static int tegra_gpio_compose(int bank, int port, int bit) 97 { 98 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); 99 } 100 101 static void tegra_gpio_mask_write(u32 reg, int gpio, int value) 102 { 103 u32 val; 104 105 val = 0x100 << GPIO_BIT(gpio); 106 if (value) 107 val |= 1 << GPIO_BIT(gpio); 108 tegra_gpio_writel(val, reg); 109 } 110 111 void tegra_gpio_enable(int gpio) 112 { 113 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1); 114 } 115 EXPORT_SYMBOL_GPL(tegra_gpio_enable); 116 117 void tegra_gpio_disable(int gpio) 118 { 119 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0); 120 } 121 EXPORT_SYMBOL_GPL(tegra_gpio_disable); 122 123 static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 124 { 125 tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value); 126 } 127 128 static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset) 129 { 130 return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1; 131 } 132 133 static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 134 { 135 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0); 136 return 0; 137 } 138 139 static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 140 int value) 141 { 142 tegra_gpio_set(chip, offset, value); 143 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1); 144 return 0; 145 } 146 147 static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 148 { 149 return irq_find_mapping(irq_domain, offset); 150 } 151 152 static struct gpio_chip tegra_gpio_chip = { 153 .label = "tegra-gpio", 154 .direction_input = tegra_gpio_direction_input, 155 .get = tegra_gpio_get, 156 .direction_output = tegra_gpio_direction_output, 157 .set = tegra_gpio_set, 158 .to_irq = tegra_gpio_to_irq, 159 .base = 0, 160 .ngpio = TEGRA_NR_GPIOS, 161 }; 162 163 static void tegra_gpio_irq_ack(struct irq_data *d) 164 { 165 int gpio = d->hwirq; 166 167 tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio)); 168 } 169 170 static void tegra_gpio_irq_mask(struct irq_data *d) 171 { 172 int gpio = d->hwirq; 173 174 tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0); 175 } 176 177 static void tegra_gpio_irq_unmask(struct irq_data *d) 178 { 179 int gpio = d->hwirq; 180 181 tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1); 182 } 183 184 static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) 185 { 186 int gpio = d->hwirq; 187 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 188 int port = GPIO_PORT(gpio); 189 int lvl_type; 190 int val; 191 unsigned long flags; 192 193 switch (type & IRQ_TYPE_SENSE_MASK) { 194 case IRQ_TYPE_EDGE_RISING: 195 lvl_type = GPIO_INT_LVL_EDGE_RISING; 196 break; 197 198 case IRQ_TYPE_EDGE_FALLING: 199 lvl_type = GPIO_INT_LVL_EDGE_FALLING; 200 break; 201 202 case IRQ_TYPE_EDGE_BOTH: 203 lvl_type = GPIO_INT_LVL_EDGE_BOTH; 204 break; 205 206 case IRQ_TYPE_LEVEL_HIGH: 207 lvl_type = GPIO_INT_LVL_LEVEL_HIGH; 208 break; 209 210 case IRQ_TYPE_LEVEL_LOW: 211 lvl_type = GPIO_INT_LVL_LEVEL_LOW; 212 break; 213 214 default: 215 return -EINVAL; 216 } 217 218 spin_lock_irqsave(&bank->lvl_lock[port], flags); 219 220 val = tegra_gpio_readl(GPIO_INT_LVL(gpio)); 221 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio)); 222 val |= lvl_type << GPIO_BIT(gpio); 223 tegra_gpio_writel(val, GPIO_INT_LVL(gpio)); 224 225 spin_unlock_irqrestore(&bank->lvl_lock[port], flags); 226 227 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 228 __irq_set_handler_locked(d->irq, handle_level_irq); 229 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 230 __irq_set_handler_locked(d->irq, handle_edge_irq); 231 232 return 0; 233 } 234 235 static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 236 { 237 struct tegra_gpio_bank *bank; 238 int port; 239 int pin; 240 int unmasked = 0; 241 struct irq_chip *chip = irq_desc_get_chip(desc); 242 243 chained_irq_enter(chip, desc); 244 245 bank = irq_get_handler_data(irq); 246 247 for (port = 0; port < 4; port++) { 248 int gpio = tegra_gpio_compose(bank->bank, port, 0); 249 unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) & 250 tegra_gpio_readl(GPIO_INT_ENB(gpio)); 251 u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio)); 252 253 for_each_set_bit(pin, &sta, 8) { 254 tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio)); 255 256 /* if gpio is edge triggered, clear condition 257 * before executing the hander so that we don't 258 * miss edges 259 */ 260 if (lvl & (0x100 << pin)) { 261 unmasked = 1; 262 chained_irq_exit(chip, desc); 263 } 264 265 generic_handle_irq(gpio_to_irq(gpio + pin)); 266 } 267 } 268 269 if (!unmasked) 270 chained_irq_exit(chip, desc); 271 272 } 273 274 #ifdef CONFIG_PM 275 void tegra_gpio_resume(void) 276 { 277 unsigned long flags; 278 int b; 279 int p; 280 281 local_irq_save(flags); 282 283 for (b = 0; b < tegra_gpio_bank_count; b++) { 284 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; 285 286 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { 287 unsigned int gpio = (b<<5) | (p<<3); 288 tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio)); 289 tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio)); 290 tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio)); 291 tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio)); 292 tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio)); 293 } 294 } 295 296 local_irq_restore(flags); 297 } 298 299 void tegra_gpio_suspend(void) 300 { 301 unsigned long flags; 302 int b; 303 int p; 304 305 local_irq_save(flags); 306 for (b = 0; b < tegra_gpio_bank_count; b++) { 307 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; 308 309 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { 310 unsigned int gpio = (b<<5) | (p<<3); 311 bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio)); 312 bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio)); 313 bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio)); 314 bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio)); 315 bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio)); 316 } 317 } 318 local_irq_restore(flags); 319 } 320 321 static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable) 322 { 323 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 324 return irq_set_irq_wake(bank->irq, enable); 325 } 326 #endif 327 328 static struct irq_chip tegra_gpio_irq_chip = { 329 .name = "GPIO", 330 .irq_ack = tegra_gpio_irq_ack, 331 .irq_mask = tegra_gpio_irq_mask, 332 .irq_unmask = tegra_gpio_irq_unmask, 333 .irq_set_type = tegra_gpio_irq_set_type, 334 #ifdef CONFIG_PM 335 .irq_set_wake = tegra_gpio_wake_enable, 336 #endif 337 }; 338 339 struct tegra_gpio_soc_config { 340 u32 bank_stride; 341 u32 upper_offset; 342 }; 343 344 static struct tegra_gpio_soc_config tegra20_gpio_config = { 345 .bank_stride = 0x80, 346 .upper_offset = 0x800, 347 }; 348 349 static struct tegra_gpio_soc_config tegra30_gpio_config = { 350 .bank_stride = 0x100, 351 .upper_offset = 0x80, 352 }; 353 354 static struct of_device_id tegra_gpio_of_match[] __devinitdata = { 355 { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config }, 356 { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config }, 357 { }, 358 }; 359 360 /* This lock class tells lockdep that GPIO irqs are in a different 361 * category than their parents, so it won't report false recursion. 362 */ 363 static struct lock_class_key gpio_lock_class; 364 365 static int __devinit tegra_gpio_probe(struct platform_device *pdev) 366 { 367 const struct of_device_id *match; 368 struct tegra_gpio_soc_config *config; 369 int irq_base; 370 struct resource *res; 371 struct tegra_gpio_bank *bank; 372 int gpio; 373 int i; 374 int j; 375 376 match = of_match_device(tegra_gpio_of_match, &pdev->dev); 377 if (match) 378 config = (struct tegra_gpio_soc_config *)match->data; 379 else 380 config = &tegra20_gpio_config; 381 382 tegra_gpio_bank_stride = config->bank_stride; 383 tegra_gpio_upper_offset = config->upper_offset; 384 385 for (;;) { 386 res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count); 387 if (!res) 388 break; 389 tegra_gpio_bank_count++; 390 } 391 if (!tegra_gpio_bank_count) { 392 dev_err(&pdev->dev, "Missing IRQ resource\n"); 393 return -ENODEV; 394 } 395 396 tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32; 397 398 tegra_gpio_banks = devm_kzalloc(&pdev->dev, 399 tegra_gpio_bank_count * sizeof(*tegra_gpio_banks), 400 GFP_KERNEL); 401 if (!tegra_gpio_banks) { 402 dev_err(&pdev->dev, "Couldn't allocate bank structure\n"); 403 return -ENODEV; 404 } 405 406 irq_base = irq_alloc_descs(-1, 0, tegra_gpio_chip.ngpio, 0); 407 if (irq_base < 0) { 408 dev_err(&pdev->dev, "Couldn't allocate IRQ numbers\n"); 409 return -ENODEV; 410 } 411 irq_domain = irq_domain_add_legacy(pdev->dev.of_node, 412 tegra_gpio_chip.ngpio, irq_base, 0, 413 &irq_domain_simple_ops, NULL); 414 415 for (i = 0; i < tegra_gpio_bank_count; i++) { 416 res = platform_get_resource(pdev, IORESOURCE_IRQ, i); 417 if (!res) { 418 dev_err(&pdev->dev, "Missing IRQ resource\n"); 419 return -ENODEV; 420 } 421 422 bank = &tegra_gpio_banks[i]; 423 bank->bank = i; 424 bank->irq = res->start; 425 } 426 427 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 428 if (!res) { 429 dev_err(&pdev->dev, "Missing MEM resource\n"); 430 return -ENODEV; 431 } 432 433 regs = devm_request_and_ioremap(&pdev->dev, res); 434 if (!regs) { 435 dev_err(&pdev->dev, "Couldn't ioremap regs\n"); 436 return -ENODEV; 437 } 438 439 for (i = 0; i < tegra_gpio_bank_count; i++) { 440 for (j = 0; j < 4; j++) { 441 int gpio = tegra_gpio_compose(i, j, 0); 442 tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio)); 443 } 444 } 445 446 #ifdef CONFIG_OF_GPIO 447 tegra_gpio_chip.of_node = pdev->dev.of_node; 448 #endif 449 450 gpiochip_add(&tegra_gpio_chip); 451 452 for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) { 453 int irq = irq_find_mapping(irq_domain, gpio); 454 /* No validity check; all Tegra GPIOs are valid IRQs */ 455 456 bank = &tegra_gpio_banks[GPIO_BANK(gpio)]; 457 458 irq_set_lockdep_class(irq, &gpio_lock_class); 459 irq_set_chip_data(irq, bank); 460 irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip, 461 handle_simple_irq); 462 set_irq_flags(irq, IRQF_VALID); 463 } 464 465 for (i = 0; i < tegra_gpio_bank_count; i++) { 466 bank = &tegra_gpio_banks[i]; 467 468 irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler); 469 irq_set_handler_data(bank->irq, bank); 470 471 for (j = 0; j < 4; j++) 472 spin_lock_init(&bank->lvl_lock[j]); 473 } 474 475 return 0; 476 } 477 478 static struct platform_driver tegra_gpio_driver = { 479 .driver = { 480 .name = "tegra-gpio", 481 .owner = THIS_MODULE, 482 .of_match_table = tegra_gpio_of_match, 483 }, 484 .probe = tegra_gpio_probe, 485 }; 486 487 static int __init tegra_gpio_init(void) 488 { 489 return platform_driver_register(&tegra_gpio_driver); 490 } 491 postcore_initcall(tegra_gpio_init); 492 493 void tegra_gpio_config(struct tegra_gpio_table *table, int num) 494 { 495 int i; 496 497 for (i = 0; i < num; i++) { 498 int gpio = table[i].gpio; 499 500 if (table[i].enable) 501 tegra_gpio_enable(gpio); 502 else 503 tegra_gpio_disable(gpio); 504 } 505 } 506 507 #ifdef CONFIG_DEBUG_FS 508 509 #include <linux/debugfs.h> 510 #include <linux/seq_file.h> 511 512 static int dbg_gpio_show(struct seq_file *s, void *unused) 513 { 514 int i; 515 int j; 516 517 for (i = 0; i < tegra_gpio_bank_count; i++) { 518 for (j = 0; j < 4; j++) { 519 int gpio = tegra_gpio_compose(i, j, 0); 520 seq_printf(s, 521 "%d:%d %02x %02x %02x %02x %02x %02x %06x\n", 522 i, j, 523 tegra_gpio_readl(GPIO_CNF(gpio)), 524 tegra_gpio_readl(GPIO_OE(gpio)), 525 tegra_gpio_readl(GPIO_OUT(gpio)), 526 tegra_gpio_readl(GPIO_IN(gpio)), 527 tegra_gpio_readl(GPIO_INT_STA(gpio)), 528 tegra_gpio_readl(GPIO_INT_ENB(gpio)), 529 tegra_gpio_readl(GPIO_INT_LVL(gpio))); 530 } 531 } 532 return 0; 533 } 534 535 static int dbg_gpio_open(struct inode *inode, struct file *file) 536 { 537 return single_open(file, dbg_gpio_show, &inode->i_private); 538 } 539 540 static const struct file_operations debug_fops = { 541 .open = dbg_gpio_open, 542 .read = seq_read, 543 .llseek = seq_lseek, 544 .release = single_release, 545 }; 546 547 static int __init tegra_gpio_debuginit(void) 548 { 549 (void) debugfs_create_file("tegra_gpio", S_IRUGO, 550 NULL, NULL, &debug_fops); 551 return 0; 552 } 553 late_initcall(tegra_gpio_debuginit); 554 #endif 555