1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * arch/arm/mach-tegra/gpio.c 4 * 5 * Copyright (c) 2010 Google, Inc 6 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. 7 * 8 * Author: 9 * Erik Gilling <konkers@google.com> 10 */ 11 12 #include <linux/err.h> 13 #include <linux/init.h> 14 #include <linux/irq.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/of_device.h> 19 #include <linux/platform_device.h> 20 #include <linux/module.h> 21 #include <linux/irqdomain.h> 22 #include <linux/irqchip/chained_irq.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pm.h> 25 26 #define GPIO_BANK(x) ((x) >> 5) 27 #define GPIO_PORT(x) (((x) >> 3) & 0x3) 28 #define GPIO_BIT(x) ((x) & 0x7) 29 30 #define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \ 31 GPIO_PORT(x) * 4) 32 33 #define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00) 34 #define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10) 35 #define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20) 36 #define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30) 37 #define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40) 38 #define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50) 39 #define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60) 40 #define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70) 41 #define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0) 42 43 44 #define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00) 45 #define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10) 46 #define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20) 47 #define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30) 48 #define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40) 49 #define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50) 50 #define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60) 51 52 #define GPIO_INT_LVL_MASK 0x010101 53 #define GPIO_INT_LVL_EDGE_RISING 0x000101 54 #define GPIO_INT_LVL_EDGE_FALLING 0x000100 55 #define GPIO_INT_LVL_EDGE_BOTH 0x010100 56 #define GPIO_INT_LVL_LEVEL_HIGH 0x000001 57 #define GPIO_INT_LVL_LEVEL_LOW 0x000000 58 59 struct tegra_gpio_info; 60 61 struct tegra_gpio_bank { 62 unsigned int bank; 63 unsigned int irq; 64 spinlock_t lvl_lock[4]; 65 spinlock_t dbc_lock[4]; /* Lock for updating debounce count register */ 66 #ifdef CONFIG_PM_SLEEP 67 u32 cnf[4]; 68 u32 out[4]; 69 u32 oe[4]; 70 u32 int_enb[4]; 71 u32 int_lvl[4]; 72 u32 wake_enb[4]; 73 u32 dbc_enb[4]; 74 #endif 75 u32 dbc_cnt[4]; 76 struct tegra_gpio_info *tgi; 77 }; 78 79 struct tegra_gpio_soc_config { 80 bool debounce_supported; 81 u32 bank_stride; 82 u32 upper_offset; 83 }; 84 85 struct tegra_gpio_info { 86 struct device *dev; 87 void __iomem *regs; 88 struct irq_domain *irq_domain; 89 struct tegra_gpio_bank *bank_info; 90 const struct tegra_gpio_soc_config *soc; 91 struct gpio_chip gc; 92 struct irq_chip ic; 93 u32 bank_count; 94 }; 95 96 static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi, 97 u32 val, u32 reg) 98 { 99 writel_relaxed(val, tgi->regs + reg); 100 } 101 102 static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg) 103 { 104 return readl_relaxed(tgi->regs + reg); 105 } 106 107 static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port, 108 unsigned int bit) 109 { 110 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); 111 } 112 113 static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg, 114 unsigned int gpio, u32 value) 115 { 116 u32 val; 117 118 val = 0x100 << GPIO_BIT(gpio); 119 if (value) 120 val |= 1 << GPIO_BIT(gpio); 121 tegra_gpio_writel(tgi, val, reg); 122 } 123 124 static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio) 125 { 126 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1); 127 } 128 129 static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio) 130 { 131 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0); 132 } 133 134 static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset) 135 { 136 return pinctrl_gpio_request(chip->base + offset); 137 } 138 139 static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset) 140 { 141 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 142 143 pinctrl_gpio_free(chip->base + offset); 144 tegra_gpio_disable(tgi, offset); 145 } 146 147 static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset, 148 int value) 149 { 150 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 151 152 tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value); 153 } 154 155 static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset) 156 { 157 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 158 unsigned int bval = BIT(GPIO_BIT(offset)); 159 160 /* If gpio is in output mode then read from the out value */ 161 if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval) 162 return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval); 163 164 return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval); 165 } 166 167 static int tegra_gpio_direction_input(struct gpio_chip *chip, 168 unsigned int offset) 169 { 170 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 171 int ret; 172 173 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0); 174 tegra_gpio_enable(tgi, offset); 175 176 ret = pinctrl_gpio_direction_input(chip->base + offset); 177 if (ret < 0) 178 dev_err(tgi->dev, 179 "Failed to set pinctrl input direction of GPIO %d: %d", 180 chip->base + offset, ret); 181 182 return ret; 183 } 184 185 static int tegra_gpio_direction_output(struct gpio_chip *chip, 186 unsigned int offset, 187 int value) 188 { 189 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 190 int ret; 191 192 tegra_gpio_set(chip, offset, value); 193 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1); 194 tegra_gpio_enable(tgi, offset); 195 196 ret = pinctrl_gpio_direction_output(chip->base + offset); 197 if (ret < 0) 198 dev_err(tgi->dev, 199 "Failed to set pinctrl output direction of GPIO %d: %d", 200 chip->base + offset, ret); 201 202 return ret; 203 } 204 205 static int tegra_gpio_get_direction(struct gpio_chip *chip, 206 unsigned int offset) 207 { 208 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 209 u32 pin_mask = BIT(GPIO_BIT(offset)); 210 u32 cnf, oe; 211 212 cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset)); 213 if (!(cnf & pin_mask)) 214 return -EINVAL; 215 216 oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)); 217 218 if (oe & pin_mask) 219 return GPIO_LINE_DIRECTION_OUT; 220 221 return GPIO_LINE_DIRECTION_IN; 222 } 223 224 static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset, 225 unsigned int debounce) 226 { 227 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 228 struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)]; 229 unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000); 230 unsigned long flags; 231 unsigned int port; 232 233 if (!debounce_ms) { 234 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), 235 offset, 0); 236 return 0; 237 } 238 239 debounce_ms = min(debounce_ms, 255U); 240 port = GPIO_PORT(offset); 241 242 /* There is only one debounce count register per port and hence 243 * set the maximum of current and requested debounce time. 244 */ 245 spin_lock_irqsave(&bank->dbc_lock[port], flags); 246 if (bank->dbc_cnt[port] < debounce_ms) { 247 tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset)); 248 bank->dbc_cnt[port] = debounce_ms; 249 } 250 spin_unlock_irqrestore(&bank->dbc_lock[port], flags); 251 252 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1); 253 254 return 0; 255 } 256 257 static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 258 unsigned long config) 259 { 260 u32 debounce; 261 262 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 263 return -ENOTSUPP; 264 265 debounce = pinconf_to_config_argument(config); 266 return tegra_gpio_set_debounce(chip, offset, debounce); 267 } 268 269 static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) 270 { 271 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 272 273 return irq_find_mapping(tgi->irq_domain, offset); 274 } 275 276 static void tegra_gpio_irq_ack(struct irq_data *d) 277 { 278 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 279 struct tegra_gpio_info *tgi = bank->tgi; 280 unsigned int gpio = d->hwirq; 281 282 tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio)); 283 } 284 285 static void tegra_gpio_irq_mask(struct irq_data *d) 286 { 287 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 288 struct tegra_gpio_info *tgi = bank->tgi; 289 unsigned int gpio = d->hwirq; 290 291 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0); 292 } 293 294 static void tegra_gpio_irq_unmask(struct irq_data *d) 295 { 296 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 297 struct tegra_gpio_info *tgi = bank->tgi; 298 unsigned int gpio = d->hwirq; 299 300 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1); 301 } 302 303 static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) 304 { 305 unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type; 306 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 307 struct tegra_gpio_info *tgi = bank->tgi; 308 unsigned long flags; 309 u32 val; 310 int ret; 311 312 switch (type & IRQ_TYPE_SENSE_MASK) { 313 case IRQ_TYPE_EDGE_RISING: 314 lvl_type = GPIO_INT_LVL_EDGE_RISING; 315 break; 316 317 case IRQ_TYPE_EDGE_FALLING: 318 lvl_type = GPIO_INT_LVL_EDGE_FALLING; 319 break; 320 321 case IRQ_TYPE_EDGE_BOTH: 322 lvl_type = GPIO_INT_LVL_EDGE_BOTH; 323 break; 324 325 case IRQ_TYPE_LEVEL_HIGH: 326 lvl_type = GPIO_INT_LVL_LEVEL_HIGH; 327 break; 328 329 case IRQ_TYPE_LEVEL_LOW: 330 lvl_type = GPIO_INT_LVL_LEVEL_LOW; 331 break; 332 333 default: 334 return -EINVAL; 335 } 336 337 spin_lock_irqsave(&bank->lvl_lock[port], flags); 338 339 val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)); 340 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio)); 341 val |= lvl_type << GPIO_BIT(gpio); 342 tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio)); 343 344 spin_unlock_irqrestore(&bank->lvl_lock[port], flags); 345 346 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0); 347 tegra_gpio_enable(tgi, gpio); 348 349 ret = gpiochip_lock_as_irq(&tgi->gc, gpio); 350 if (ret) { 351 dev_err(tgi->dev, 352 "unable to lock Tegra GPIO %u as IRQ\n", gpio); 353 tegra_gpio_disable(tgi, gpio); 354 return ret; 355 } 356 357 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 358 irq_set_handler_locked(d, handle_level_irq); 359 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 360 irq_set_handler_locked(d, handle_edge_irq); 361 362 return 0; 363 } 364 365 static void tegra_gpio_irq_shutdown(struct irq_data *d) 366 { 367 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 368 struct tegra_gpio_info *tgi = bank->tgi; 369 unsigned int gpio = d->hwirq; 370 371 gpiochip_unlock_as_irq(&tgi->gc, gpio); 372 } 373 374 static void tegra_gpio_irq_handler(struct irq_desc *desc) 375 { 376 unsigned int port, pin, gpio; 377 bool unmasked = false; 378 u32 lvl; 379 unsigned long sta; 380 struct irq_chip *chip = irq_desc_get_chip(desc); 381 struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc); 382 struct tegra_gpio_info *tgi = bank->tgi; 383 384 chained_irq_enter(chip, desc); 385 386 for (port = 0; port < 4; port++) { 387 gpio = tegra_gpio_compose(bank->bank, port, 0); 388 sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) & 389 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)); 390 lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)); 391 392 for_each_set_bit(pin, &sta, 8) { 393 tegra_gpio_writel(tgi, 1 << pin, 394 GPIO_INT_CLR(tgi, gpio)); 395 396 /* if gpio is edge triggered, clear condition 397 * before executing the handler so that we don't 398 * miss edges 399 */ 400 if (!unmasked && lvl & (0x100 << pin)) { 401 unmasked = true; 402 chained_irq_exit(chip, desc); 403 } 404 405 generic_handle_irq(irq_find_mapping(tgi->irq_domain, 406 gpio + pin)); 407 } 408 } 409 410 if (!unmasked) 411 chained_irq_exit(chip, desc); 412 413 } 414 415 #ifdef CONFIG_PM_SLEEP 416 static int tegra_gpio_resume(struct device *dev) 417 { 418 struct tegra_gpio_info *tgi = dev_get_drvdata(dev); 419 unsigned long flags; 420 unsigned int b, p; 421 422 local_irq_save(flags); 423 424 for (b = 0; b < tgi->bank_count; b++) { 425 struct tegra_gpio_bank *bank = &tgi->bank_info[b]; 426 427 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { 428 unsigned int gpio = (b << 5) | (p << 3); 429 430 tegra_gpio_writel(tgi, bank->cnf[p], 431 GPIO_CNF(tgi, gpio)); 432 433 if (tgi->soc->debounce_supported) { 434 tegra_gpio_writel(tgi, bank->dbc_cnt[p], 435 GPIO_DBC_CNT(tgi, gpio)); 436 tegra_gpio_writel(tgi, bank->dbc_enb[p], 437 GPIO_MSK_DBC_EN(tgi, gpio)); 438 } 439 440 tegra_gpio_writel(tgi, bank->out[p], 441 GPIO_OUT(tgi, gpio)); 442 tegra_gpio_writel(tgi, bank->oe[p], 443 GPIO_OE(tgi, gpio)); 444 tegra_gpio_writel(tgi, bank->int_lvl[p], 445 GPIO_INT_LVL(tgi, gpio)); 446 tegra_gpio_writel(tgi, bank->int_enb[p], 447 GPIO_INT_ENB(tgi, gpio)); 448 } 449 } 450 451 local_irq_restore(flags); 452 return 0; 453 } 454 455 static int tegra_gpio_suspend(struct device *dev) 456 { 457 struct tegra_gpio_info *tgi = dev_get_drvdata(dev); 458 unsigned long flags; 459 unsigned int b, p; 460 461 local_irq_save(flags); 462 for (b = 0; b < tgi->bank_count; b++) { 463 struct tegra_gpio_bank *bank = &tgi->bank_info[b]; 464 465 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { 466 unsigned int gpio = (b << 5) | (p << 3); 467 468 bank->cnf[p] = tegra_gpio_readl(tgi, 469 GPIO_CNF(tgi, gpio)); 470 bank->out[p] = tegra_gpio_readl(tgi, 471 GPIO_OUT(tgi, gpio)); 472 bank->oe[p] = tegra_gpio_readl(tgi, 473 GPIO_OE(tgi, gpio)); 474 if (tgi->soc->debounce_supported) { 475 bank->dbc_enb[p] = tegra_gpio_readl(tgi, 476 GPIO_MSK_DBC_EN(tgi, gpio)); 477 bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) | 478 bank->dbc_enb[p]; 479 } 480 481 bank->int_enb[p] = tegra_gpio_readl(tgi, 482 GPIO_INT_ENB(tgi, gpio)); 483 bank->int_lvl[p] = tegra_gpio_readl(tgi, 484 GPIO_INT_LVL(tgi, gpio)); 485 486 /* Enable gpio irq for wake up source */ 487 tegra_gpio_writel(tgi, bank->wake_enb[p], 488 GPIO_INT_ENB(tgi, gpio)); 489 } 490 } 491 local_irq_restore(flags); 492 return 0; 493 } 494 495 static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable) 496 { 497 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 498 unsigned int gpio = d->hwirq; 499 u32 port, bit, mask; 500 501 port = GPIO_PORT(gpio); 502 bit = GPIO_BIT(gpio); 503 mask = BIT(bit); 504 505 if (enable) 506 bank->wake_enb[port] |= mask; 507 else 508 bank->wake_enb[port] &= ~mask; 509 510 return irq_set_irq_wake(bank->irq, enable); 511 } 512 #endif 513 514 #ifdef CONFIG_DEBUG_FS 515 516 #include <linux/debugfs.h> 517 #include <linux/seq_file.h> 518 519 static int tegra_dbg_gpio_show(struct seq_file *s, void *unused) 520 { 521 struct tegra_gpio_info *tgi = s->private; 522 unsigned int i, j; 523 524 for (i = 0; i < tgi->bank_count; i++) { 525 for (j = 0; j < 4; j++) { 526 unsigned int gpio = tegra_gpio_compose(i, j, 0); 527 528 seq_printf(s, 529 "%u:%u %02x %02x %02x %02x %02x %02x %06x\n", 530 i, j, 531 tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)), 532 tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)), 533 tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)), 534 tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)), 535 tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)), 536 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)), 537 tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio))); 538 } 539 } 540 return 0; 541 } 542 543 DEFINE_SHOW_ATTRIBUTE(tegra_dbg_gpio); 544 545 static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi) 546 { 547 debugfs_create_file("tegra_gpio", 0444, NULL, tgi, 548 &tegra_dbg_gpio_fops); 549 } 550 551 #else 552 553 static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi) 554 { 555 } 556 557 #endif 558 559 static const struct dev_pm_ops tegra_gpio_pm_ops = { 560 SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume) 561 }; 562 563 static int tegra_gpio_probe(struct platform_device *pdev) 564 { 565 struct tegra_gpio_info *tgi; 566 struct tegra_gpio_bank *bank; 567 unsigned int gpio, i, j; 568 int ret; 569 570 tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL); 571 if (!tgi) 572 return -ENODEV; 573 574 tgi->soc = of_device_get_match_data(&pdev->dev); 575 tgi->dev = &pdev->dev; 576 577 ret = platform_irq_count(pdev); 578 if (ret < 0) 579 return ret; 580 581 tgi->bank_count = ret; 582 583 if (!tgi->bank_count) { 584 dev_err(&pdev->dev, "Missing IRQ resource\n"); 585 return -ENODEV; 586 } 587 588 tgi->gc.label = "tegra-gpio"; 589 tgi->gc.request = tegra_gpio_request; 590 tgi->gc.free = tegra_gpio_free; 591 tgi->gc.direction_input = tegra_gpio_direction_input; 592 tgi->gc.get = tegra_gpio_get; 593 tgi->gc.direction_output = tegra_gpio_direction_output; 594 tgi->gc.set = tegra_gpio_set; 595 tgi->gc.get_direction = tegra_gpio_get_direction; 596 tgi->gc.to_irq = tegra_gpio_to_irq; 597 tgi->gc.base = 0; 598 tgi->gc.ngpio = tgi->bank_count * 32; 599 tgi->gc.parent = &pdev->dev; 600 tgi->gc.of_node = pdev->dev.of_node; 601 602 tgi->ic.name = "GPIO"; 603 tgi->ic.irq_ack = tegra_gpio_irq_ack; 604 tgi->ic.irq_mask = tegra_gpio_irq_mask; 605 tgi->ic.irq_unmask = tegra_gpio_irq_unmask; 606 tgi->ic.irq_set_type = tegra_gpio_irq_set_type; 607 tgi->ic.irq_shutdown = tegra_gpio_irq_shutdown; 608 #ifdef CONFIG_PM_SLEEP 609 tgi->ic.irq_set_wake = tegra_gpio_irq_set_wake; 610 #endif 611 612 platform_set_drvdata(pdev, tgi); 613 614 if (tgi->soc->debounce_supported) 615 tgi->gc.set_config = tegra_gpio_set_config; 616 617 tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count, 618 sizeof(*tgi->bank_info), GFP_KERNEL); 619 if (!tgi->bank_info) 620 return -ENOMEM; 621 622 tgi->irq_domain = irq_domain_add_linear(pdev->dev.of_node, 623 tgi->gc.ngpio, 624 &irq_domain_simple_ops, NULL); 625 if (!tgi->irq_domain) 626 return -ENODEV; 627 628 for (i = 0; i < tgi->bank_count; i++) { 629 ret = platform_get_irq(pdev, i); 630 if (ret < 0) 631 return ret; 632 633 bank = &tgi->bank_info[i]; 634 bank->bank = i; 635 bank->irq = ret; 636 bank->tgi = tgi; 637 } 638 639 tgi->regs = devm_platform_ioremap_resource(pdev, 0); 640 if (IS_ERR(tgi->regs)) 641 return PTR_ERR(tgi->regs); 642 643 for (i = 0; i < tgi->bank_count; i++) { 644 for (j = 0; j < 4; j++) { 645 int gpio = tegra_gpio_compose(i, j, 0); 646 647 tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio)); 648 } 649 } 650 651 ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi); 652 if (ret < 0) { 653 irq_domain_remove(tgi->irq_domain); 654 return ret; 655 } 656 657 for (gpio = 0; gpio < tgi->gc.ngpio; gpio++) { 658 int irq = irq_create_mapping(tgi->irq_domain, gpio); 659 /* No validity check; all Tegra GPIOs are valid IRQs */ 660 661 bank = &tgi->bank_info[GPIO_BANK(gpio)]; 662 663 irq_set_chip_data(irq, bank); 664 irq_set_chip_and_handler(irq, &tgi->ic, handle_simple_irq); 665 } 666 667 for (i = 0; i < tgi->bank_count; i++) { 668 bank = &tgi->bank_info[i]; 669 670 irq_set_chained_handler_and_data(bank->irq, 671 tegra_gpio_irq_handler, bank); 672 673 for (j = 0; j < 4; j++) { 674 spin_lock_init(&bank->lvl_lock[j]); 675 spin_lock_init(&bank->dbc_lock[j]); 676 } 677 } 678 679 tegra_gpio_debuginit(tgi); 680 681 return 0; 682 } 683 684 static const struct tegra_gpio_soc_config tegra20_gpio_config = { 685 .bank_stride = 0x80, 686 .upper_offset = 0x800, 687 }; 688 689 static const struct tegra_gpio_soc_config tegra30_gpio_config = { 690 .bank_stride = 0x100, 691 .upper_offset = 0x80, 692 }; 693 694 static const struct tegra_gpio_soc_config tegra210_gpio_config = { 695 .debounce_supported = true, 696 .bank_stride = 0x100, 697 .upper_offset = 0x80, 698 }; 699 700 static const struct of_device_id tegra_gpio_of_match[] = { 701 { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config }, 702 { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config }, 703 { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config }, 704 { }, 705 }; 706 707 static struct platform_driver tegra_gpio_driver = { 708 .driver = { 709 .name = "tegra-gpio", 710 .pm = &tegra_gpio_pm_ops, 711 .of_match_table = tegra_gpio_of_match, 712 }, 713 .probe = tegra_gpio_probe, 714 }; 715 716 static int __init tegra_gpio_init(void) 717 { 718 return platform_driver_register(&tegra_gpio_driver); 719 } 720 subsys_initcall(tegra_gpio_init); 721