1 /* 2 * arch/arm/mach-tegra/gpio.c 3 * 4 * Copyright (c) 2010 Google, Inc 5 * 6 * Author: 7 * Erik Gilling <konkers@google.com> 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 */ 19 20 #include <linux/err.h> 21 #include <linux/init.h> 22 #include <linux/irq.h> 23 #include <linux/interrupt.h> 24 #include <linux/io.h> 25 #include <linux/gpio/driver.h> 26 #include <linux/of_device.h> 27 #include <linux/platform_device.h> 28 #include <linux/module.h> 29 #include <linux/irqdomain.h> 30 #include <linux/irqchip/chained_irq.h> 31 #include <linux/pinctrl/consumer.h> 32 #include <linux/pm.h> 33 34 #define GPIO_BANK(x) ((x) >> 5) 35 #define GPIO_PORT(x) (((x) >> 3) & 0x3) 36 #define GPIO_BIT(x) ((x) & 0x7) 37 38 #define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \ 39 GPIO_PORT(x) * 4) 40 41 #define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00) 42 #define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10) 43 #define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20) 44 #define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30) 45 #define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40) 46 #define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50) 47 #define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60) 48 #define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70) 49 #define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0) 50 51 52 #define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00) 53 #define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10) 54 #define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20) 55 #define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30) 56 #define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40) 57 #define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50) 58 #define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60) 59 60 #define GPIO_INT_LVL_MASK 0x010101 61 #define GPIO_INT_LVL_EDGE_RISING 0x000101 62 #define GPIO_INT_LVL_EDGE_FALLING 0x000100 63 #define GPIO_INT_LVL_EDGE_BOTH 0x010100 64 #define GPIO_INT_LVL_LEVEL_HIGH 0x000001 65 #define GPIO_INT_LVL_LEVEL_LOW 0x000000 66 67 struct tegra_gpio_info; 68 69 struct tegra_gpio_bank { 70 unsigned int bank; 71 unsigned int irq; 72 spinlock_t lvl_lock[4]; 73 spinlock_t dbc_lock[4]; /* Lock for updating debounce count register */ 74 #ifdef CONFIG_PM_SLEEP 75 u32 cnf[4]; 76 u32 out[4]; 77 u32 oe[4]; 78 u32 int_enb[4]; 79 u32 int_lvl[4]; 80 u32 wake_enb[4]; 81 u32 dbc_enb[4]; 82 #endif 83 u32 dbc_cnt[4]; 84 struct tegra_gpio_info *tgi; 85 }; 86 87 struct tegra_gpio_soc_config { 88 bool debounce_supported; 89 u32 bank_stride; 90 u32 upper_offset; 91 }; 92 93 struct tegra_gpio_info { 94 struct device *dev; 95 void __iomem *regs; 96 struct irq_domain *irq_domain; 97 struct tegra_gpio_bank *bank_info; 98 const struct tegra_gpio_soc_config *soc; 99 struct gpio_chip gc; 100 struct irq_chip ic; 101 u32 bank_count; 102 }; 103 104 static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi, 105 u32 val, u32 reg) 106 { 107 __raw_writel(val, tgi->regs + reg); 108 } 109 110 static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg) 111 { 112 return __raw_readl(tgi->regs + reg); 113 } 114 115 static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port, 116 unsigned int bit) 117 { 118 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); 119 } 120 121 static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg, 122 unsigned int gpio, u32 value) 123 { 124 u32 val; 125 126 val = 0x100 << GPIO_BIT(gpio); 127 if (value) 128 val |= 1 << GPIO_BIT(gpio); 129 tegra_gpio_writel(tgi, val, reg); 130 } 131 132 static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio) 133 { 134 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1); 135 } 136 137 static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio) 138 { 139 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0); 140 } 141 142 static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset) 143 { 144 return pinctrl_gpio_request(offset); 145 } 146 147 static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset) 148 { 149 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 150 151 pinctrl_gpio_free(offset); 152 tegra_gpio_disable(tgi, offset); 153 } 154 155 static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset, 156 int value) 157 { 158 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 159 160 tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value); 161 } 162 163 static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset) 164 { 165 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 166 unsigned int bval = BIT(GPIO_BIT(offset)); 167 168 /* If gpio is in output mode then read from the out value */ 169 if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval) 170 return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval); 171 172 return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval); 173 } 174 175 static int tegra_gpio_direction_input(struct gpio_chip *chip, 176 unsigned int offset) 177 { 178 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 179 180 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0); 181 tegra_gpio_enable(tgi, offset); 182 return 0; 183 } 184 185 static int tegra_gpio_direction_output(struct gpio_chip *chip, 186 unsigned int offset, 187 int value) 188 { 189 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 190 191 tegra_gpio_set(chip, offset, value); 192 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1); 193 tegra_gpio_enable(tgi, offset); 194 return 0; 195 } 196 197 static int tegra_gpio_get_direction(struct gpio_chip *chip, 198 unsigned int offset) 199 { 200 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 201 u32 pin_mask = BIT(GPIO_BIT(offset)); 202 u32 cnf, oe; 203 204 cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset)); 205 if (!(cnf & pin_mask)) 206 return -EINVAL; 207 208 oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)); 209 210 return !(oe & pin_mask); 211 } 212 213 static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset, 214 unsigned int debounce) 215 { 216 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 217 struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)]; 218 unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000); 219 unsigned long flags; 220 unsigned int port; 221 222 if (!debounce_ms) { 223 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), 224 offset, 0); 225 return 0; 226 } 227 228 debounce_ms = min(debounce_ms, 255U); 229 port = GPIO_PORT(offset); 230 231 /* There is only one debounce count register per port and hence 232 * set the maximum of current and requested debounce time. 233 */ 234 spin_lock_irqsave(&bank->dbc_lock[port], flags); 235 if (bank->dbc_cnt[port] < debounce_ms) { 236 tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset)); 237 bank->dbc_cnt[port] = debounce_ms; 238 } 239 spin_unlock_irqrestore(&bank->dbc_lock[port], flags); 240 241 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1); 242 243 return 0; 244 } 245 246 static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 247 unsigned long config) 248 { 249 u32 debounce; 250 251 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 252 return -ENOTSUPP; 253 254 debounce = pinconf_to_config_argument(config); 255 return tegra_gpio_set_debounce(chip, offset, debounce); 256 } 257 258 static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) 259 { 260 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 261 262 return irq_find_mapping(tgi->irq_domain, offset); 263 } 264 265 static void tegra_gpio_irq_ack(struct irq_data *d) 266 { 267 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 268 struct tegra_gpio_info *tgi = bank->tgi; 269 unsigned int gpio = d->hwirq; 270 271 tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio)); 272 } 273 274 static void tegra_gpio_irq_mask(struct irq_data *d) 275 { 276 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 277 struct tegra_gpio_info *tgi = bank->tgi; 278 unsigned int gpio = d->hwirq; 279 280 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0); 281 } 282 283 static void tegra_gpio_irq_unmask(struct irq_data *d) 284 { 285 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 286 struct tegra_gpio_info *tgi = bank->tgi; 287 unsigned int gpio = d->hwirq; 288 289 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1); 290 } 291 292 static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) 293 { 294 unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type; 295 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 296 struct tegra_gpio_info *tgi = bank->tgi; 297 unsigned long flags; 298 u32 val; 299 int ret; 300 301 switch (type & IRQ_TYPE_SENSE_MASK) { 302 case IRQ_TYPE_EDGE_RISING: 303 lvl_type = GPIO_INT_LVL_EDGE_RISING; 304 break; 305 306 case IRQ_TYPE_EDGE_FALLING: 307 lvl_type = GPIO_INT_LVL_EDGE_FALLING; 308 break; 309 310 case IRQ_TYPE_EDGE_BOTH: 311 lvl_type = GPIO_INT_LVL_EDGE_BOTH; 312 break; 313 314 case IRQ_TYPE_LEVEL_HIGH: 315 lvl_type = GPIO_INT_LVL_LEVEL_HIGH; 316 break; 317 318 case IRQ_TYPE_LEVEL_LOW: 319 lvl_type = GPIO_INT_LVL_LEVEL_LOW; 320 break; 321 322 default: 323 return -EINVAL; 324 } 325 326 spin_lock_irqsave(&bank->lvl_lock[port], flags); 327 328 val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)); 329 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio)); 330 val |= lvl_type << GPIO_BIT(gpio); 331 tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio)); 332 333 spin_unlock_irqrestore(&bank->lvl_lock[port], flags); 334 335 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0); 336 tegra_gpio_enable(tgi, gpio); 337 338 ret = gpiochip_lock_as_irq(&tgi->gc, gpio); 339 if (ret) { 340 dev_err(tgi->dev, 341 "unable to lock Tegra GPIO %u as IRQ\n", gpio); 342 tegra_gpio_disable(tgi, gpio); 343 return ret; 344 } 345 346 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 347 irq_set_handler_locked(d, handle_level_irq); 348 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 349 irq_set_handler_locked(d, handle_edge_irq); 350 351 return 0; 352 } 353 354 static void tegra_gpio_irq_shutdown(struct irq_data *d) 355 { 356 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 357 struct tegra_gpio_info *tgi = bank->tgi; 358 unsigned int gpio = d->hwirq; 359 360 gpiochip_unlock_as_irq(&tgi->gc, gpio); 361 } 362 363 static void tegra_gpio_irq_handler(struct irq_desc *desc) 364 { 365 unsigned int port, pin, gpio; 366 bool unmasked = false; 367 u32 lvl; 368 unsigned long sta; 369 struct irq_chip *chip = irq_desc_get_chip(desc); 370 struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc); 371 struct tegra_gpio_info *tgi = bank->tgi; 372 373 chained_irq_enter(chip, desc); 374 375 for (port = 0; port < 4; port++) { 376 gpio = tegra_gpio_compose(bank->bank, port, 0); 377 sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) & 378 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)); 379 lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)); 380 381 for_each_set_bit(pin, &sta, 8) { 382 tegra_gpio_writel(tgi, 1 << pin, 383 GPIO_INT_CLR(tgi, gpio)); 384 385 /* if gpio is edge triggered, clear condition 386 * before executing the handler so that we don't 387 * miss edges 388 */ 389 if (!unmasked && lvl & (0x100 << pin)) { 390 unmasked = true; 391 chained_irq_exit(chip, desc); 392 } 393 394 generic_handle_irq(irq_find_mapping(tgi->irq_domain, 395 gpio + pin)); 396 } 397 } 398 399 if (!unmasked) 400 chained_irq_exit(chip, desc); 401 402 } 403 404 #ifdef CONFIG_PM_SLEEP 405 static int tegra_gpio_resume(struct device *dev) 406 { 407 struct platform_device *pdev = to_platform_device(dev); 408 struct tegra_gpio_info *tgi = platform_get_drvdata(pdev); 409 unsigned long flags; 410 unsigned int b, p; 411 412 local_irq_save(flags); 413 414 for (b = 0; b < tgi->bank_count; b++) { 415 struct tegra_gpio_bank *bank = &tgi->bank_info[b]; 416 417 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { 418 unsigned int gpio = (b << 5) | (p << 3); 419 420 tegra_gpio_writel(tgi, bank->cnf[p], 421 GPIO_CNF(tgi, gpio)); 422 423 if (tgi->soc->debounce_supported) { 424 tegra_gpio_writel(tgi, bank->dbc_cnt[p], 425 GPIO_DBC_CNT(tgi, gpio)); 426 tegra_gpio_writel(tgi, bank->dbc_enb[p], 427 GPIO_MSK_DBC_EN(tgi, gpio)); 428 } 429 430 tegra_gpio_writel(tgi, bank->out[p], 431 GPIO_OUT(tgi, gpio)); 432 tegra_gpio_writel(tgi, bank->oe[p], 433 GPIO_OE(tgi, gpio)); 434 tegra_gpio_writel(tgi, bank->int_lvl[p], 435 GPIO_INT_LVL(tgi, gpio)); 436 tegra_gpio_writel(tgi, bank->int_enb[p], 437 GPIO_INT_ENB(tgi, gpio)); 438 } 439 } 440 441 local_irq_restore(flags); 442 return 0; 443 } 444 445 static int tegra_gpio_suspend(struct device *dev) 446 { 447 struct platform_device *pdev = to_platform_device(dev); 448 struct tegra_gpio_info *tgi = platform_get_drvdata(pdev); 449 unsigned long flags; 450 unsigned int b, p; 451 452 local_irq_save(flags); 453 for (b = 0; b < tgi->bank_count; b++) { 454 struct tegra_gpio_bank *bank = &tgi->bank_info[b]; 455 456 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { 457 unsigned int gpio = (b << 5) | (p << 3); 458 459 bank->cnf[p] = tegra_gpio_readl(tgi, 460 GPIO_CNF(tgi, gpio)); 461 bank->out[p] = tegra_gpio_readl(tgi, 462 GPIO_OUT(tgi, gpio)); 463 bank->oe[p] = tegra_gpio_readl(tgi, 464 GPIO_OE(tgi, gpio)); 465 if (tgi->soc->debounce_supported) { 466 bank->dbc_enb[p] = tegra_gpio_readl(tgi, 467 GPIO_MSK_DBC_EN(tgi, gpio)); 468 bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) | 469 bank->dbc_enb[p]; 470 } 471 472 bank->int_enb[p] = tegra_gpio_readl(tgi, 473 GPIO_INT_ENB(tgi, gpio)); 474 bank->int_lvl[p] = tegra_gpio_readl(tgi, 475 GPIO_INT_LVL(tgi, gpio)); 476 477 /* Enable gpio irq for wake up source */ 478 tegra_gpio_writel(tgi, bank->wake_enb[p], 479 GPIO_INT_ENB(tgi, gpio)); 480 } 481 } 482 local_irq_restore(flags); 483 return 0; 484 } 485 486 static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable) 487 { 488 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 489 unsigned int gpio = d->hwirq; 490 u32 port, bit, mask; 491 492 port = GPIO_PORT(gpio); 493 bit = GPIO_BIT(gpio); 494 mask = BIT(bit); 495 496 if (enable) 497 bank->wake_enb[port] |= mask; 498 else 499 bank->wake_enb[port] &= ~mask; 500 501 return irq_set_irq_wake(bank->irq, enable); 502 } 503 #endif 504 505 #ifdef CONFIG_DEBUG_FS 506 507 #include <linux/debugfs.h> 508 #include <linux/seq_file.h> 509 510 static int tegra_dbg_gpio_show(struct seq_file *s, void *unused) 511 { 512 struct tegra_gpio_info *tgi = s->private; 513 unsigned int i, j; 514 515 for (i = 0; i < tgi->bank_count; i++) { 516 for (j = 0; j < 4; j++) { 517 unsigned int gpio = tegra_gpio_compose(i, j, 0); 518 519 seq_printf(s, 520 "%u:%u %02x %02x %02x %02x %02x %02x %06x\n", 521 i, j, 522 tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)), 523 tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)), 524 tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)), 525 tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)), 526 tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)), 527 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)), 528 tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio))); 529 } 530 } 531 return 0; 532 } 533 534 DEFINE_SHOW_ATTRIBUTE(tegra_dbg_gpio); 535 536 static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi) 537 { 538 (void) debugfs_create_file("tegra_gpio", 0444, 539 NULL, tgi, &tegra_dbg_gpio_fops); 540 } 541 542 #else 543 544 static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi) 545 { 546 } 547 548 #endif 549 550 static const struct dev_pm_ops tegra_gpio_pm_ops = { 551 SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume) 552 }; 553 554 static int tegra_gpio_probe(struct platform_device *pdev) 555 { 556 struct tegra_gpio_info *tgi; 557 struct resource *res; 558 struct tegra_gpio_bank *bank; 559 unsigned int gpio, i, j; 560 int ret; 561 562 tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL); 563 if (!tgi) 564 return -ENODEV; 565 566 tgi->soc = of_device_get_match_data(&pdev->dev); 567 tgi->dev = &pdev->dev; 568 569 ret = platform_irq_count(pdev); 570 if (ret < 0) 571 return ret; 572 573 tgi->bank_count = ret; 574 575 if (!tgi->bank_count) { 576 dev_err(&pdev->dev, "Missing IRQ resource\n"); 577 return -ENODEV; 578 } 579 580 tgi->gc.label = "tegra-gpio"; 581 tgi->gc.request = tegra_gpio_request; 582 tgi->gc.free = tegra_gpio_free; 583 tgi->gc.direction_input = tegra_gpio_direction_input; 584 tgi->gc.get = tegra_gpio_get; 585 tgi->gc.direction_output = tegra_gpio_direction_output; 586 tgi->gc.set = tegra_gpio_set; 587 tgi->gc.get_direction = tegra_gpio_get_direction; 588 tgi->gc.to_irq = tegra_gpio_to_irq; 589 tgi->gc.base = 0; 590 tgi->gc.ngpio = tgi->bank_count * 32; 591 tgi->gc.parent = &pdev->dev; 592 tgi->gc.of_node = pdev->dev.of_node; 593 594 tgi->ic.name = "GPIO"; 595 tgi->ic.irq_ack = tegra_gpio_irq_ack; 596 tgi->ic.irq_mask = tegra_gpio_irq_mask; 597 tgi->ic.irq_unmask = tegra_gpio_irq_unmask; 598 tgi->ic.irq_set_type = tegra_gpio_irq_set_type; 599 tgi->ic.irq_shutdown = tegra_gpio_irq_shutdown; 600 #ifdef CONFIG_PM_SLEEP 601 tgi->ic.irq_set_wake = tegra_gpio_irq_set_wake; 602 #endif 603 604 platform_set_drvdata(pdev, tgi); 605 606 if (tgi->soc->debounce_supported) 607 tgi->gc.set_config = tegra_gpio_set_config; 608 609 tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count, 610 sizeof(*tgi->bank_info), GFP_KERNEL); 611 if (!tgi->bank_info) 612 return -ENOMEM; 613 614 tgi->irq_domain = irq_domain_add_linear(pdev->dev.of_node, 615 tgi->gc.ngpio, 616 &irq_domain_simple_ops, NULL); 617 if (!tgi->irq_domain) 618 return -ENODEV; 619 620 for (i = 0; i < tgi->bank_count; i++) { 621 ret = platform_get_irq(pdev, i); 622 if (ret < 0) { 623 dev_err(&pdev->dev, "Missing IRQ resource: %d\n", ret); 624 return ret; 625 } 626 627 bank = &tgi->bank_info[i]; 628 bank->bank = i; 629 bank->irq = ret; 630 bank->tgi = tgi; 631 } 632 633 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 634 tgi->regs = devm_ioremap_resource(&pdev->dev, res); 635 if (IS_ERR(tgi->regs)) 636 return PTR_ERR(tgi->regs); 637 638 for (i = 0; i < tgi->bank_count; i++) { 639 for (j = 0; j < 4; j++) { 640 int gpio = tegra_gpio_compose(i, j, 0); 641 642 tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio)); 643 } 644 } 645 646 ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi); 647 if (ret < 0) { 648 irq_domain_remove(tgi->irq_domain); 649 return ret; 650 } 651 652 for (gpio = 0; gpio < tgi->gc.ngpio; gpio++) { 653 int irq = irq_create_mapping(tgi->irq_domain, gpio); 654 /* No validity check; all Tegra GPIOs are valid IRQs */ 655 656 bank = &tgi->bank_info[GPIO_BANK(gpio)]; 657 658 irq_set_chip_data(irq, bank); 659 irq_set_chip_and_handler(irq, &tgi->ic, handle_simple_irq); 660 } 661 662 for (i = 0; i < tgi->bank_count; i++) { 663 bank = &tgi->bank_info[i]; 664 665 irq_set_chained_handler_and_data(bank->irq, 666 tegra_gpio_irq_handler, bank); 667 668 for (j = 0; j < 4; j++) { 669 spin_lock_init(&bank->lvl_lock[j]); 670 spin_lock_init(&bank->dbc_lock[j]); 671 } 672 } 673 674 tegra_gpio_debuginit(tgi); 675 676 return 0; 677 } 678 679 static const struct tegra_gpio_soc_config tegra20_gpio_config = { 680 .bank_stride = 0x80, 681 .upper_offset = 0x800, 682 }; 683 684 static const struct tegra_gpio_soc_config tegra30_gpio_config = { 685 .bank_stride = 0x100, 686 .upper_offset = 0x80, 687 }; 688 689 static const struct tegra_gpio_soc_config tegra210_gpio_config = { 690 .debounce_supported = true, 691 .bank_stride = 0x100, 692 .upper_offset = 0x80, 693 }; 694 695 static const struct of_device_id tegra_gpio_of_match[] = { 696 { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config }, 697 { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config }, 698 { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config }, 699 { }, 700 }; 701 702 static struct platform_driver tegra_gpio_driver = { 703 .driver = { 704 .name = "tegra-gpio", 705 .pm = &tegra_gpio_pm_ops, 706 .of_match_table = tegra_gpio_of_match, 707 }, 708 .probe = tegra_gpio_probe, 709 }; 710 711 static int __init tegra_gpio_init(void) 712 { 713 return platform_driver_register(&tegra_gpio_driver); 714 } 715 subsys_initcall(tegra_gpio_init); 716