1 /* 2 * arch/arm/mach-tegra/gpio.c 3 * 4 * Copyright (c) 2010 Google, Inc 5 * 6 * Author: 7 * Erik Gilling <konkers@google.com> 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 */ 19 20 #include <linux/err.h> 21 #include <linux/init.h> 22 #include <linux/irq.h> 23 #include <linux/interrupt.h> 24 #include <linux/io.h> 25 #include <linux/gpio.h> 26 #include <linux/of_device.h> 27 #include <linux/platform_device.h> 28 #include <linux/module.h> 29 #include <linux/irqdomain.h> 30 #include <linux/irqchip/chained_irq.h> 31 #include <linux/pinctrl/consumer.h> 32 #include <linux/pm.h> 33 34 #define GPIO_BANK(x) ((x) >> 5) 35 #define GPIO_PORT(x) (((x) >> 3) & 0x3) 36 #define GPIO_BIT(x) ((x) & 0x7) 37 38 #define GPIO_REG(x) (GPIO_BANK(x) * tegra_gpio_bank_stride + \ 39 GPIO_PORT(x) * 4) 40 41 #define GPIO_CNF(x) (GPIO_REG(x) + 0x00) 42 #define GPIO_OE(x) (GPIO_REG(x) + 0x10) 43 #define GPIO_OUT(x) (GPIO_REG(x) + 0X20) 44 #define GPIO_IN(x) (GPIO_REG(x) + 0x30) 45 #define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40) 46 #define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50) 47 #define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60) 48 #define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70) 49 50 #define GPIO_MSK_CNF(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x00) 51 #define GPIO_MSK_OE(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x10) 52 #define GPIO_MSK_OUT(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0X20) 53 #define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x40) 54 #define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x50) 55 #define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x60) 56 57 #define GPIO_INT_LVL_MASK 0x010101 58 #define GPIO_INT_LVL_EDGE_RISING 0x000101 59 #define GPIO_INT_LVL_EDGE_FALLING 0x000100 60 #define GPIO_INT_LVL_EDGE_BOTH 0x010100 61 #define GPIO_INT_LVL_LEVEL_HIGH 0x000001 62 #define GPIO_INT_LVL_LEVEL_LOW 0x000000 63 64 struct tegra_gpio_bank { 65 int bank; 66 int irq; 67 spinlock_t lvl_lock[4]; 68 #ifdef CONFIG_PM_SLEEP 69 u32 cnf[4]; 70 u32 out[4]; 71 u32 oe[4]; 72 u32 int_enb[4]; 73 u32 int_lvl[4]; 74 u32 wake_enb[4]; 75 #endif 76 }; 77 78 static struct device *dev; 79 static struct irq_domain *irq_domain; 80 static void __iomem *regs; 81 static u32 tegra_gpio_bank_count; 82 static u32 tegra_gpio_bank_stride; 83 static u32 tegra_gpio_upper_offset; 84 static struct tegra_gpio_bank *tegra_gpio_banks; 85 86 static inline void tegra_gpio_writel(u32 val, u32 reg) 87 { 88 __raw_writel(val, regs + reg); 89 } 90 91 static inline u32 tegra_gpio_readl(u32 reg) 92 { 93 return __raw_readl(regs + reg); 94 } 95 96 static int tegra_gpio_compose(int bank, int port, int bit) 97 { 98 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); 99 } 100 101 static void tegra_gpio_mask_write(u32 reg, int gpio, int value) 102 { 103 u32 val; 104 105 val = 0x100 << GPIO_BIT(gpio); 106 if (value) 107 val |= 1 << GPIO_BIT(gpio); 108 tegra_gpio_writel(val, reg); 109 } 110 111 static void tegra_gpio_enable(int gpio) 112 { 113 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1); 114 } 115 116 static void tegra_gpio_disable(int gpio) 117 { 118 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0); 119 } 120 121 static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset) 122 { 123 return pinctrl_request_gpio(offset); 124 } 125 126 static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset) 127 { 128 pinctrl_free_gpio(offset); 129 tegra_gpio_disable(offset); 130 } 131 132 static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 133 { 134 tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value); 135 } 136 137 static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset) 138 { 139 /* If gpio is in output mode then read from the out value */ 140 if ((tegra_gpio_readl(GPIO_OE(offset)) >> GPIO_BIT(offset)) & 1) 141 return (tegra_gpio_readl(GPIO_OUT(offset)) >> 142 GPIO_BIT(offset)) & 0x1; 143 144 return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1; 145 } 146 147 static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 148 { 149 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0); 150 tegra_gpio_enable(offset); 151 return 0; 152 } 153 154 static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 155 int value) 156 { 157 tegra_gpio_set(chip, offset, value); 158 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1); 159 tegra_gpio_enable(offset); 160 return 0; 161 } 162 163 static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 164 { 165 return irq_find_mapping(irq_domain, offset); 166 } 167 168 static struct gpio_chip tegra_gpio_chip = { 169 .label = "tegra-gpio", 170 .request = tegra_gpio_request, 171 .free = tegra_gpio_free, 172 .direction_input = tegra_gpio_direction_input, 173 .get = tegra_gpio_get, 174 .direction_output = tegra_gpio_direction_output, 175 .set = tegra_gpio_set, 176 .to_irq = tegra_gpio_to_irq, 177 .base = 0, 178 }; 179 180 static void tegra_gpio_irq_ack(struct irq_data *d) 181 { 182 int gpio = d->hwirq; 183 184 tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio)); 185 } 186 187 static void tegra_gpio_irq_mask(struct irq_data *d) 188 { 189 int gpio = d->hwirq; 190 191 tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0); 192 } 193 194 static void tegra_gpio_irq_unmask(struct irq_data *d) 195 { 196 int gpio = d->hwirq; 197 198 tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1); 199 } 200 201 static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) 202 { 203 int gpio = d->hwirq; 204 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 205 int port = GPIO_PORT(gpio); 206 int lvl_type; 207 int val; 208 unsigned long flags; 209 int ret; 210 211 switch (type & IRQ_TYPE_SENSE_MASK) { 212 case IRQ_TYPE_EDGE_RISING: 213 lvl_type = GPIO_INT_LVL_EDGE_RISING; 214 break; 215 216 case IRQ_TYPE_EDGE_FALLING: 217 lvl_type = GPIO_INT_LVL_EDGE_FALLING; 218 break; 219 220 case IRQ_TYPE_EDGE_BOTH: 221 lvl_type = GPIO_INT_LVL_EDGE_BOTH; 222 break; 223 224 case IRQ_TYPE_LEVEL_HIGH: 225 lvl_type = GPIO_INT_LVL_LEVEL_HIGH; 226 break; 227 228 case IRQ_TYPE_LEVEL_LOW: 229 lvl_type = GPIO_INT_LVL_LEVEL_LOW; 230 break; 231 232 default: 233 return -EINVAL; 234 } 235 236 ret = gpiochip_lock_as_irq(&tegra_gpio_chip, gpio); 237 if (ret) { 238 dev_err(dev, "unable to lock Tegra GPIO %d as IRQ\n", gpio); 239 return ret; 240 } 241 242 spin_lock_irqsave(&bank->lvl_lock[port], flags); 243 244 val = tegra_gpio_readl(GPIO_INT_LVL(gpio)); 245 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio)); 246 val |= lvl_type << GPIO_BIT(gpio); 247 tegra_gpio_writel(val, GPIO_INT_LVL(gpio)); 248 249 spin_unlock_irqrestore(&bank->lvl_lock[port], flags); 250 251 tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0); 252 tegra_gpio_enable(gpio); 253 254 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 255 __irq_set_handler_locked(d->irq, handle_level_irq); 256 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 257 __irq_set_handler_locked(d->irq, handle_edge_irq); 258 259 return 0; 260 } 261 262 static void tegra_gpio_irq_shutdown(struct irq_data *d) 263 { 264 int gpio = d->hwirq; 265 266 gpiochip_unlock_as_irq(&tegra_gpio_chip, gpio); 267 } 268 269 static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 270 { 271 struct tegra_gpio_bank *bank; 272 int port; 273 int pin; 274 int unmasked = 0; 275 struct irq_chip *chip = irq_desc_get_chip(desc); 276 277 chained_irq_enter(chip, desc); 278 279 bank = irq_get_handler_data(irq); 280 281 for (port = 0; port < 4; port++) { 282 int gpio = tegra_gpio_compose(bank->bank, port, 0); 283 unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) & 284 tegra_gpio_readl(GPIO_INT_ENB(gpio)); 285 u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio)); 286 287 for_each_set_bit(pin, &sta, 8) { 288 tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio)); 289 290 /* if gpio is edge triggered, clear condition 291 * before executing the handler so that we don't 292 * miss edges 293 */ 294 if (lvl & (0x100 << pin)) { 295 unmasked = 1; 296 chained_irq_exit(chip, desc); 297 } 298 299 generic_handle_irq(gpio_to_irq(gpio + pin)); 300 } 301 } 302 303 if (!unmasked) 304 chained_irq_exit(chip, desc); 305 306 } 307 308 #ifdef CONFIG_PM_SLEEP 309 static int tegra_gpio_resume(struct device *dev) 310 { 311 unsigned long flags; 312 int b; 313 int p; 314 315 local_irq_save(flags); 316 317 for (b = 0; b < tegra_gpio_bank_count; b++) { 318 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; 319 320 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { 321 unsigned int gpio = (b<<5) | (p<<3); 322 tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio)); 323 tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio)); 324 tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio)); 325 tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio)); 326 tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio)); 327 } 328 } 329 330 local_irq_restore(flags); 331 return 0; 332 } 333 334 static int tegra_gpio_suspend(struct device *dev) 335 { 336 unsigned long flags; 337 int b; 338 int p; 339 340 local_irq_save(flags); 341 for (b = 0; b < tegra_gpio_bank_count; b++) { 342 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; 343 344 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { 345 unsigned int gpio = (b<<5) | (p<<3); 346 bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio)); 347 bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio)); 348 bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio)); 349 bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio)); 350 bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio)); 351 352 /* Enable gpio irq for wake up source */ 353 tegra_gpio_writel(bank->wake_enb[p], 354 GPIO_INT_ENB(gpio)); 355 } 356 } 357 local_irq_restore(flags); 358 return 0; 359 } 360 361 static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable) 362 { 363 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 364 int gpio = d->hwirq; 365 u32 port, bit, mask; 366 367 port = GPIO_PORT(gpio); 368 bit = GPIO_BIT(gpio); 369 mask = BIT(bit); 370 371 if (enable) 372 bank->wake_enb[port] |= mask; 373 else 374 bank->wake_enb[port] &= ~mask; 375 376 return irq_set_irq_wake(bank->irq, enable); 377 } 378 #endif 379 380 static struct irq_chip tegra_gpio_irq_chip = { 381 .name = "GPIO", 382 .irq_ack = tegra_gpio_irq_ack, 383 .irq_mask = tegra_gpio_irq_mask, 384 .irq_unmask = tegra_gpio_irq_unmask, 385 .irq_set_type = tegra_gpio_irq_set_type, 386 .irq_shutdown = tegra_gpio_irq_shutdown, 387 #ifdef CONFIG_PM_SLEEP 388 .irq_set_wake = tegra_gpio_irq_set_wake, 389 #endif 390 }; 391 392 static const struct dev_pm_ops tegra_gpio_pm_ops = { 393 SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume) 394 }; 395 396 struct tegra_gpio_soc_config { 397 u32 bank_stride; 398 u32 upper_offset; 399 }; 400 401 static struct tegra_gpio_soc_config tegra20_gpio_config = { 402 .bank_stride = 0x80, 403 .upper_offset = 0x800, 404 }; 405 406 static struct tegra_gpio_soc_config tegra30_gpio_config = { 407 .bank_stride = 0x100, 408 .upper_offset = 0x80, 409 }; 410 411 static const struct of_device_id tegra_gpio_of_match[] = { 412 { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config }, 413 { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config }, 414 { }, 415 }; 416 417 /* This lock class tells lockdep that GPIO irqs are in a different 418 * category than their parents, so it won't report false recursion. 419 */ 420 static struct lock_class_key gpio_lock_class; 421 422 static int tegra_gpio_probe(struct platform_device *pdev) 423 { 424 const struct of_device_id *match; 425 struct tegra_gpio_soc_config *config; 426 struct resource *res; 427 struct tegra_gpio_bank *bank; 428 int ret; 429 int gpio; 430 int i; 431 int j; 432 433 dev = &pdev->dev; 434 435 match = of_match_device(tegra_gpio_of_match, &pdev->dev); 436 if (!match) { 437 dev_err(&pdev->dev, "Error: No device match found\n"); 438 return -ENODEV; 439 } 440 config = (struct tegra_gpio_soc_config *)match->data; 441 442 tegra_gpio_bank_stride = config->bank_stride; 443 tegra_gpio_upper_offset = config->upper_offset; 444 445 for (;;) { 446 res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count); 447 if (!res) 448 break; 449 tegra_gpio_bank_count++; 450 } 451 if (!tegra_gpio_bank_count) { 452 dev_err(&pdev->dev, "Missing IRQ resource\n"); 453 return -ENODEV; 454 } 455 456 tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32; 457 458 tegra_gpio_banks = devm_kzalloc(&pdev->dev, 459 tegra_gpio_bank_count * sizeof(*tegra_gpio_banks), 460 GFP_KERNEL); 461 if (!tegra_gpio_banks) 462 return -ENODEV; 463 464 irq_domain = irq_domain_add_linear(pdev->dev.of_node, 465 tegra_gpio_chip.ngpio, 466 &irq_domain_simple_ops, NULL); 467 if (!irq_domain) 468 return -ENODEV; 469 470 for (i = 0; i < tegra_gpio_bank_count; i++) { 471 res = platform_get_resource(pdev, IORESOURCE_IRQ, i); 472 if (!res) { 473 dev_err(&pdev->dev, "Missing IRQ resource\n"); 474 return -ENODEV; 475 } 476 477 bank = &tegra_gpio_banks[i]; 478 bank->bank = i; 479 bank->irq = res->start; 480 } 481 482 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 483 regs = devm_ioremap_resource(&pdev->dev, res); 484 if (IS_ERR(regs)) 485 return PTR_ERR(regs); 486 487 for (i = 0; i < tegra_gpio_bank_count; i++) { 488 for (j = 0; j < 4; j++) { 489 int gpio = tegra_gpio_compose(i, j, 0); 490 tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio)); 491 } 492 } 493 494 tegra_gpio_chip.of_node = pdev->dev.of_node; 495 496 ret = gpiochip_add(&tegra_gpio_chip); 497 if (ret < 0) { 498 irq_domain_remove(irq_domain); 499 return ret; 500 } 501 502 for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) { 503 int irq = irq_create_mapping(irq_domain, gpio); 504 /* No validity check; all Tegra GPIOs are valid IRQs */ 505 506 bank = &tegra_gpio_banks[GPIO_BANK(gpio)]; 507 508 irq_set_lockdep_class(irq, &gpio_lock_class); 509 irq_set_chip_data(irq, bank); 510 irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip, 511 handle_simple_irq); 512 set_irq_flags(irq, IRQF_VALID); 513 } 514 515 for (i = 0; i < tegra_gpio_bank_count; i++) { 516 bank = &tegra_gpio_banks[i]; 517 518 irq_set_chained_handler_and_data(bank->irq, 519 tegra_gpio_irq_handler, bank); 520 521 for (j = 0; j < 4; j++) 522 spin_lock_init(&bank->lvl_lock[j]); 523 } 524 525 return 0; 526 } 527 528 static struct platform_driver tegra_gpio_driver = { 529 .driver = { 530 .name = "tegra-gpio", 531 .pm = &tegra_gpio_pm_ops, 532 .of_match_table = tegra_gpio_of_match, 533 }, 534 .probe = tegra_gpio_probe, 535 }; 536 537 static int __init tegra_gpio_init(void) 538 { 539 return platform_driver_register(&tegra_gpio_driver); 540 } 541 postcore_initcall(tegra_gpio_init); 542 543 #ifdef CONFIG_DEBUG_FS 544 545 #include <linux/debugfs.h> 546 #include <linux/seq_file.h> 547 548 static int dbg_gpio_show(struct seq_file *s, void *unused) 549 { 550 int i; 551 int j; 552 553 for (i = 0; i < tegra_gpio_bank_count; i++) { 554 for (j = 0; j < 4; j++) { 555 int gpio = tegra_gpio_compose(i, j, 0); 556 seq_printf(s, 557 "%d:%d %02x %02x %02x %02x %02x %02x %06x\n", 558 i, j, 559 tegra_gpio_readl(GPIO_CNF(gpio)), 560 tegra_gpio_readl(GPIO_OE(gpio)), 561 tegra_gpio_readl(GPIO_OUT(gpio)), 562 tegra_gpio_readl(GPIO_IN(gpio)), 563 tegra_gpio_readl(GPIO_INT_STA(gpio)), 564 tegra_gpio_readl(GPIO_INT_ENB(gpio)), 565 tegra_gpio_readl(GPIO_INT_LVL(gpio))); 566 } 567 } 568 return 0; 569 } 570 571 static int dbg_gpio_open(struct inode *inode, struct file *file) 572 { 573 return single_open(file, dbg_gpio_show, &inode->i_private); 574 } 575 576 static const struct file_operations debug_fops = { 577 .open = dbg_gpio_open, 578 .read = seq_read, 579 .llseek = seq_lseek, 580 .release = single_release, 581 }; 582 583 static int __init tegra_gpio_debuginit(void) 584 { 585 (void) debugfs_create_file("tegra_gpio", S_IRUGO, 586 NULL, NULL, &debug_fops); 587 return 0; 588 } 589 late_initcall(tegra_gpio_debuginit); 590 #endif 591