1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * arch/arm/mach-tegra/gpio.c 4 * 5 * Copyright (c) 2010 Google, Inc 6 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. 7 * 8 * Author: 9 * Erik Gilling <konkers@google.com> 10 */ 11 12 #include <linux/err.h> 13 #include <linux/init.h> 14 #include <linux/irq.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/of_device.h> 19 #include <linux/platform_device.h> 20 #include <linux/module.h> 21 #include <linux/irqdomain.h> 22 #include <linux/irqchip/chained_irq.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pm.h> 25 26 #define GPIO_BANK(x) ((x) >> 5) 27 #define GPIO_PORT(x) (((x) >> 3) & 0x3) 28 #define GPIO_BIT(x) ((x) & 0x7) 29 30 #define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \ 31 GPIO_PORT(x) * 4) 32 33 #define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00) 34 #define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10) 35 #define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20) 36 #define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30) 37 #define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40) 38 #define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50) 39 #define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60) 40 #define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70) 41 #define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0) 42 43 44 #define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00) 45 #define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10) 46 #define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20) 47 #define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30) 48 #define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40) 49 #define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50) 50 #define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60) 51 52 #define GPIO_INT_LVL_MASK 0x010101 53 #define GPIO_INT_LVL_EDGE_RISING 0x000101 54 #define GPIO_INT_LVL_EDGE_FALLING 0x000100 55 #define GPIO_INT_LVL_EDGE_BOTH 0x010100 56 #define GPIO_INT_LVL_LEVEL_HIGH 0x000001 57 #define GPIO_INT_LVL_LEVEL_LOW 0x000000 58 59 struct tegra_gpio_info; 60 61 struct tegra_gpio_bank { 62 unsigned int bank; 63 unsigned int irq; 64 65 /* 66 * IRQ-core code uses raw locking, and thus, nested locking also 67 * should be raw in order not to trip spinlock debug warnings. 68 */ 69 raw_spinlock_t lvl_lock[4]; 70 71 /* Lock for updating debounce count register */ 72 spinlock_t dbc_lock[4]; 73 74 #ifdef CONFIG_PM_SLEEP 75 u32 cnf[4]; 76 u32 out[4]; 77 u32 oe[4]; 78 u32 int_enb[4]; 79 u32 int_lvl[4]; 80 u32 wake_enb[4]; 81 u32 dbc_enb[4]; 82 #endif 83 u32 dbc_cnt[4]; 84 struct tegra_gpio_info *tgi; 85 }; 86 87 struct tegra_gpio_soc_config { 88 bool debounce_supported; 89 u32 bank_stride; 90 u32 upper_offset; 91 }; 92 93 struct tegra_gpio_info { 94 struct device *dev; 95 void __iomem *regs; 96 struct irq_domain *irq_domain; 97 struct tegra_gpio_bank *bank_info; 98 const struct tegra_gpio_soc_config *soc; 99 struct gpio_chip gc; 100 struct irq_chip ic; 101 u32 bank_count; 102 }; 103 104 static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi, 105 u32 val, u32 reg) 106 { 107 writel_relaxed(val, tgi->regs + reg); 108 } 109 110 static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg) 111 { 112 return readl_relaxed(tgi->regs + reg); 113 } 114 115 static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port, 116 unsigned int bit) 117 { 118 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); 119 } 120 121 static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg, 122 unsigned int gpio, u32 value) 123 { 124 u32 val; 125 126 val = 0x100 << GPIO_BIT(gpio); 127 if (value) 128 val |= 1 << GPIO_BIT(gpio); 129 tegra_gpio_writel(tgi, val, reg); 130 } 131 132 static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio) 133 { 134 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1); 135 } 136 137 static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio) 138 { 139 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0); 140 } 141 142 static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset) 143 { 144 return pinctrl_gpio_request(chip->base + offset); 145 } 146 147 static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset) 148 { 149 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 150 151 pinctrl_gpio_free(chip->base + offset); 152 tegra_gpio_disable(tgi, offset); 153 } 154 155 static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset, 156 int value) 157 { 158 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 159 160 tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value); 161 } 162 163 static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset) 164 { 165 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 166 unsigned int bval = BIT(GPIO_BIT(offset)); 167 168 /* If gpio is in output mode then read from the out value */ 169 if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval) 170 return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval); 171 172 return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval); 173 } 174 175 static int tegra_gpio_direction_input(struct gpio_chip *chip, 176 unsigned int offset) 177 { 178 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 179 int ret; 180 181 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0); 182 tegra_gpio_enable(tgi, offset); 183 184 ret = pinctrl_gpio_direction_input(chip->base + offset); 185 if (ret < 0) 186 dev_err(tgi->dev, 187 "Failed to set pinctrl input direction of GPIO %d: %d", 188 chip->base + offset, ret); 189 190 return ret; 191 } 192 193 static int tegra_gpio_direction_output(struct gpio_chip *chip, 194 unsigned int offset, 195 int value) 196 { 197 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 198 int ret; 199 200 tegra_gpio_set(chip, offset, value); 201 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1); 202 tegra_gpio_enable(tgi, offset); 203 204 ret = pinctrl_gpio_direction_output(chip->base + offset); 205 if (ret < 0) 206 dev_err(tgi->dev, 207 "Failed to set pinctrl output direction of GPIO %d: %d", 208 chip->base + offset, ret); 209 210 return ret; 211 } 212 213 static int tegra_gpio_get_direction(struct gpio_chip *chip, 214 unsigned int offset) 215 { 216 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 217 u32 pin_mask = BIT(GPIO_BIT(offset)); 218 u32 cnf, oe; 219 220 cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset)); 221 if (!(cnf & pin_mask)) 222 return -EINVAL; 223 224 oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)); 225 226 if (oe & pin_mask) 227 return GPIO_LINE_DIRECTION_OUT; 228 229 return GPIO_LINE_DIRECTION_IN; 230 } 231 232 static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset, 233 unsigned int debounce) 234 { 235 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 236 struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)]; 237 unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000); 238 unsigned long flags; 239 unsigned int port; 240 241 if (!debounce_ms) { 242 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), 243 offset, 0); 244 return 0; 245 } 246 247 debounce_ms = min(debounce_ms, 255U); 248 port = GPIO_PORT(offset); 249 250 /* There is only one debounce count register per port and hence 251 * set the maximum of current and requested debounce time. 252 */ 253 spin_lock_irqsave(&bank->dbc_lock[port], flags); 254 if (bank->dbc_cnt[port] < debounce_ms) { 255 tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset)); 256 bank->dbc_cnt[port] = debounce_ms; 257 } 258 spin_unlock_irqrestore(&bank->dbc_lock[port], flags); 259 260 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1); 261 262 return 0; 263 } 264 265 static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 266 unsigned long config) 267 { 268 u32 debounce; 269 270 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 271 return -ENOTSUPP; 272 273 debounce = pinconf_to_config_argument(config); 274 return tegra_gpio_set_debounce(chip, offset, debounce); 275 } 276 277 static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) 278 { 279 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 280 281 return irq_find_mapping(tgi->irq_domain, offset); 282 } 283 284 static void tegra_gpio_irq_ack(struct irq_data *d) 285 { 286 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 287 struct tegra_gpio_info *tgi = bank->tgi; 288 unsigned int gpio = d->hwirq; 289 290 tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio)); 291 } 292 293 static void tegra_gpio_irq_mask(struct irq_data *d) 294 { 295 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 296 struct tegra_gpio_info *tgi = bank->tgi; 297 unsigned int gpio = d->hwirq; 298 299 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0); 300 } 301 302 static void tegra_gpio_irq_unmask(struct irq_data *d) 303 { 304 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 305 struct tegra_gpio_info *tgi = bank->tgi; 306 unsigned int gpio = d->hwirq; 307 308 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1); 309 } 310 311 static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) 312 { 313 unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type; 314 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 315 struct tegra_gpio_info *tgi = bank->tgi; 316 unsigned long flags; 317 u32 val; 318 int ret; 319 320 switch (type & IRQ_TYPE_SENSE_MASK) { 321 case IRQ_TYPE_EDGE_RISING: 322 lvl_type = GPIO_INT_LVL_EDGE_RISING; 323 break; 324 325 case IRQ_TYPE_EDGE_FALLING: 326 lvl_type = GPIO_INT_LVL_EDGE_FALLING; 327 break; 328 329 case IRQ_TYPE_EDGE_BOTH: 330 lvl_type = GPIO_INT_LVL_EDGE_BOTH; 331 break; 332 333 case IRQ_TYPE_LEVEL_HIGH: 334 lvl_type = GPIO_INT_LVL_LEVEL_HIGH; 335 break; 336 337 case IRQ_TYPE_LEVEL_LOW: 338 lvl_type = GPIO_INT_LVL_LEVEL_LOW; 339 break; 340 341 default: 342 return -EINVAL; 343 } 344 345 raw_spin_lock_irqsave(&bank->lvl_lock[port], flags); 346 347 val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)); 348 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio)); 349 val |= lvl_type << GPIO_BIT(gpio); 350 tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio)); 351 352 raw_spin_unlock_irqrestore(&bank->lvl_lock[port], flags); 353 354 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0); 355 tegra_gpio_enable(tgi, gpio); 356 357 ret = gpiochip_lock_as_irq(&tgi->gc, gpio); 358 if (ret) { 359 dev_err(tgi->dev, 360 "unable to lock Tegra GPIO %u as IRQ\n", gpio); 361 tegra_gpio_disable(tgi, gpio); 362 return ret; 363 } 364 365 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 366 irq_set_handler_locked(d, handle_level_irq); 367 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 368 irq_set_handler_locked(d, handle_edge_irq); 369 370 return 0; 371 } 372 373 static void tegra_gpio_irq_shutdown(struct irq_data *d) 374 { 375 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 376 struct tegra_gpio_info *tgi = bank->tgi; 377 unsigned int gpio = d->hwirq; 378 379 tegra_gpio_irq_mask(d); 380 gpiochip_unlock_as_irq(&tgi->gc, gpio); 381 } 382 383 static void tegra_gpio_irq_handler(struct irq_desc *desc) 384 { 385 unsigned int port, pin, gpio; 386 bool unmasked = false; 387 u32 lvl; 388 unsigned long sta; 389 struct irq_chip *chip = irq_desc_get_chip(desc); 390 struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc); 391 struct tegra_gpio_info *tgi = bank->tgi; 392 393 chained_irq_enter(chip, desc); 394 395 for (port = 0; port < 4; port++) { 396 gpio = tegra_gpio_compose(bank->bank, port, 0); 397 sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) & 398 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)); 399 lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)); 400 401 for_each_set_bit(pin, &sta, 8) { 402 tegra_gpio_writel(tgi, 1 << pin, 403 GPIO_INT_CLR(tgi, gpio)); 404 405 /* if gpio is edge triggered, clear condition 406 * before executing the handler so that we don't 407 * miss edges 408 */ 409 if (!unmasked && lvl & (0x100 << pin)) { 410 unmasked = true; 411 chained_irq_exit(chip, desc); 412 } 413 414 generic_handle_irq(irq_find_mapping(tgi->irq_domain, 415 gpio + pin)); 416 } 417 } 418 419 if (!unmasked) 420 chained_irq_exit(chip, desc); 421 422 } 423 424 #ifdef CONFIG_PM_SLEEP 425 static int tegra_gpio_resume(struct device *dev) 426 { 427 struct tegra_gpio_info *tgi = dev_get_drvdata(dev); 428 unsigned int b, p; 429 430 for (b = 0; b < tgi->bank_count; b++) { 431 struct tegra_gpio_bank *bank = &tgi->bank_info[b]; 432 433 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { 434 unsigned int gpio = (b << 5) | (p << 3); 435 436 tegra_gpio_writel(tgi, bank->cnf[p], 437 GPIO_CNF(tgi, gpio)); 438 439 if (tgi->soc->debounce_supported) { 440 tegra_gpio_writel(tgi, bank->dbc_cnt[p], 441 GPIO_DBC_CNT(tgi, gpio)); 442 tegra_gpio_writel(tgi, bank->dbc_enb[p], 443 GPIO_MSK_DBC_EN(tgi, gpio)); 444 } 445 446 tegra_gpio_writel(tgi, bank->out[p], 447 GPIO_OUT(tgi, gpio)); 448 tegra_gpio_writel(tgi, bank->oe[p], 449 GPIO_OE(tgi, gpio)); 450 tegra_gpio_writel(tgi, bank->int_lvl[p], 451 GPIO_INT_LVL(tgi, gpio)); 452 tegra_gpio_writel(tgi, bank->int_enb[p], 453 GPIO_INT_ENB(tgi, gpio)); 454 } 455 } 456 457 return 0; 458 } 459 460 static int tegra_gpio_suspend(struct device *dev) 461 { 462 struct tegra_gpio_info *tgi = dev_get_drvdata(dev); 463 unsigned int b, p; 464 465 for (b = 0; b < tgi->bank_count; b++) { 466 struct tegra_gpio_bank *bank = &tgi->bank_info[b]; 467 468 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { 469 unsigned int gpio = (b << 5) | (p << 3); 470 471 bank->cnf[p] = tegra_gpio_readl(tgi, 472 GPIO_CNF(tgi, gpio)); 473 bank->out[p] = tegra_gpio_readl(tgi, 474 GPIO_OUT(tgi, gpio)); 475 bank->oe[p] = tegra_gpio_readl(tgi, 476 GPIO_OE(tgi, gpio)); 477 if (tgi->soc->debounce_supported) { 478 bank->dbc_enb[p] = tegra_gpio_readl(tgi, 479 GPIO_MSK_DBC_EN(tgi, gpio)); 480 bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) | 481 bank->dbc_enb[p]; 482 } 483 484 bank->int_enb[p] = tegra_gpio_readl(tgi, 485 GPIO_INT_ENB(tgi, gpio)); 486 bank->int_lvl[p] = tegra_gpio_readl(tgi, 487 GPIO_INT_LVL(tgi, gpio)); 488 489 /* Enable gpio irq for wake up source */ 490 tegra_gpio_writel(tgi, bank->wake_enb[p], 491 GPIO_INT_ENB(tgi, gpio)); 492 } 493 } 494 495 return 0; 496 } 497 498 static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable) 499 { 500 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 501 unsigned int gpio = d->hwirq; 502 u32 port, bit, mask; 503 int err; 504 505 err = irq_set_irq_wake(bank->irq, enable); 506 if (err) 507 return err; 508 509 port = GPIO_PORT(gpio); 510 bit = GPIO_BIT(gpio); 511 mask = BIT(bit); 512 513 if (enable) 514 bank->wake_enb[port] |= mask; 515 else 516 bank->wake_enb[port] &= ~mask; 517 518 return 0; 519 } 520 #endif 521 522 #ifdef CONFIG_DEBUG_FS 523 524 #include <linux/debugfs.h> 525 #include <linux/seq_file.h> 526 527 static int tegra_dbg_gpio_show(struct seq_file *s, void *unused) 528 { 529 struct tegra_gpio_info *tgi = s->private; 530 unsigned int i, j; 531 532 for (i = 0; i < tgi->bank_count; i++) { 533 for (j = 0; j < 4; j++) { 534 unsigned int gpio = tegra_gpio_compose(i, j, 0); 535 536 seq_printf(s, 537 "%u:%u %02x %02x %02x %02x %02x %02x %06x\n", 538 i, j, 539 tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)), 540 tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)), 541 tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)), 542 tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)), 543 tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)), 544 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)), 545 tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio))); 546 } 547 } 548 return 0; 549 } 550 551 DEFINE_SHOW_ATTRIBUTE(tegra_dbg_gpio); 552 553 static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi) 554 { 555 debugfs_create_file("tegra_gpio", 0444, NULL, tgi, 556 &tegra_dbg_gpio_fops); 557 } 558 559 #else 560 561 static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi) 562 { 563 } 564 565 #endif 566 567 static const struct dev_pm_ops tegra_gpio_pm_ops = { 568 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume) 569 }; 570 571 static struct lock_class_key gpio_lock_class; 572 static struct lock_class_key gpio_request_class; 573 574 static int tegra_gpio_probe(struct platform_device *pdev) 575 { 576 struct tegra_gpio_info *tgi; 577 struct tegra_gpio_bank *bank; 578 unsigned int gpio, i, j; 579 int ret; 580 581 tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL); 582 if (!tgi) 583 return -ENODEV; 584 585 tgi->soc = of_device_get_match_data(&pdev->dev); 586 tgi->dev = &pdev->dev; 587 588 ret = platform_irq_count(pdev); 589 if (ret < 0) 590 return ret; 591 592 tgi->bank_count = ret; 593 594 if (!tgi->bank_count) { 595 dev_err(&pdev->dev, "Missing IRQ resource\n"); 596 return -ENODEV; 597 } 598 599 tgi->gc.label = "tegra-gpio"; 600 tgi->gc.request = tegra_gpio_request; 601 tgi->gc.free = tegra_gpio_free; 602 tgi->gc.direction_input = tegra_gpio_direction_input; 603 tgi->gc.get = tegra_gpio_get; 604 tgi->gc.direction_output = tegra_gpio_direction_output; 605 tgi->gc.set = tegra_gpio_set; 606 tgi->gc.get_direction = tegra_gpio_get_direction; 607 tgi->gc.to_irq = tegra_gpio_to_irq; 608 tgi->gc.base = 0; 609 tgi->gc.ngpio = tgi->bank_count * 32; 610 tgi->gc.parent = &pdev->dev; 611 tgi->gc.of_node = pdev->dev.of_node; 612 613 tgi->ic.name = "GPIO"; 614 tgi->ic.irq_ack = tegra_gpio_irq_ack; 615 tgi->ic.irq_mask = tegra_gpio_irq_mask; 616 tgi->ic.irq_unmask = tegra_gpio_irq_unmask; 617 tgi->ic.irq_set_type = tegra_gpio_irq_set_type; 618 tgi->ic.irq_shutdown = tegra_gpio_irq_shutdown; 619 #ifdef CONFIG_PM_SLEEP 620 tgi->ic.irq_set_wake = tegra_gpio_irq_set_wake; 621 #endif 622 623 platform_set_drvdata(pdev, tgi); 624 625 if (tgi->soc->debounce_supported) 626 tgi->gc.set_config = tegra_gpio_set_config; 627 628 tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count, 629 sizeof(*tgi->bank_info), GFP_KERNEL); 630 if (!tgi->bank_info) 631 return -ENOMEM; 632 633 tgi->irq_domain = irq_domain_add_linear(pdev->dev.of_node, 634 tgi->gc.ngpio, 635 &irq_domain_simple_ops, NULL); 636 if (!tgi->irq_domain) 637 return -ENODEV; 638 639 for (i = 0; i < tgi->bank_count; i++) { 640 ret = platform_get_irq(pdev, i); 641 if (ret < 0) 642 return ret; 643 644 bank = &tgi->bank_info[i]; 645 bank->bank = i; 646 bank->irq = ret; 647 bank->tgi = tgi; 648 } 649 650 tgi->regs = devm_platform_ioremap_resource(pdev, 0); 651 if (IS_ERR(tgi->regs)) 652 return PTR_ERR(tgi->regs); 653 654 for (i = 0; i < tgi->bank_count; i++) { 655 for (j = 0; j < 4; j++) { 656 int gpio = tegra_gpio_compose(i, j, 0); 657 658 tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio)); 659 } 660 } 661 662 ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi); 663 if (ret < 0) { 664 irq_domain_remove(tgi->irq_domain); 665 return ret; 666 } 667 668 for (gpio = 0; gpio < tgi->gc.ngpio; gpio++) { 669 int irq = irq_create_mapping(tgi->irq_domain, gpio); 670 /* No validity check; all Tegra GPIOs are valid IRQs */ 671 672 bank = &tgi->bank_info[GPIO_BANK(gpio)]; 673 674 irq_set_chip_data(irq, bank); 675 irq_set_lockdep_class(irq, &gpio_lock_class, &gpio_request_class); 676 irq_set_chip_and_handler(irq, &tgi->ic, handle_simple_irq); 677 } 678 679 for (i = 0; i < tgi->bank_count; i++) { 680 bank = &tgi->bank_info[i]; 681 682 irq_set_chained_handler_and_data(bank->irq, 683 tegra_gpio_irq_handler, bank); 684 685 for (j = 0; j < 4; j++) { 686 raw_spin_lock_init(&bank->lvl_lock[j]); 687 spin_lock_init(&bank->dbc_lock[j]); 688 } 689 } 690 691 tegra_gpio_debuginit(tgi); 692 693 return 0; 694 } 695 696 static const struct tegra_gpio_soc_config tegra20_gpio_config = { 697 .bank_stride = 0x80, 698 .upper_offset = 0x800, 699 }; 700 701 static const struct tegra_gpio_soc_config tegra30_gpio_config = { 702 .bank_stride = 0x100, 703 .upper_offset = 0x80, 704 }; 705 706 static const struct tegra_gpio_soc_config tegra210_gpio_config = { 707 .debounce_supported = true, 708 .bank_stride = 0x100, 709 .upper_offset = 0x80, 710 }; 711 712 static const struct of_device_id tegra_gpio_of_match[] = { 713 { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config }, 714 { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config }, 715 { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config }, 716 { }, 717 }; 718 719 static struct platform_driver tegra_gpio_driver = { 720 .driver = { 721 .name = "tegra-gpio", 722 .pm = &tegra_gpio_pm_ops, 723 .of_match_table = tegra_gpio_of_match, 724 }, 725 .probe = tegra_gpio_probe, 726 }; 727 728 static int __init tegra_gpio_init(void) 729 { 730 return platform_driver_register(&tegra_gpio_driver); 731 } 732 subsys_initcall(tegra_gpio_init); 733