1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * arch/arm/mach-tegra/gpio.c 4 * 5 * Copyright (c) 2010 Google, Inc 6 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. 7 * 8 * Author: 9 * Erik Gilling <konkers@google.com> 10 */ 11 12 #include <linux/err.h> 13 #include <linux/init.h> 14 #include <linux/irq.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/of_device.h> 19 #include <linux/platform_device.h> 20 #include <linux/module.h> 21 #include <linux/seq_file.h> 22 #include <linux/irqdomain.h> 23 #include <linux/irqchip/chained_irq.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/pm.h> 26 27 #define GPIO_BANK(x) ((x) >> 5) 28 #define GPIO_PORT(x) (((x) >> 3) & 0x3) 29 #define GPIO_BIT(x) ((x) & 0x7) 30 31 #define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \ 32 GPIO_PORT(x) * 4) 33 34 #define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00) 35 #define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10) 36 #define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20) 37 #define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30) 38 #define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40) 39 #define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50) 40 #define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60) 41 #define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70) 42 #define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0) 43 44 45 #define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00) 46 #define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10) 47 #define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20) 48 #define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30) 49 #define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40) 50 #define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50) 51 #define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60) 52 53 #define GPIO_INT_LVL_MASK 0x010101 54 #define GPIO_INT_LVL_EDGE_RISING 0x000101 55 #define GPIO_INT_LVL_EDGE_FALLING 0x000100 56 #define GPIO_INT_LVL_EDGE_BOTH 0x010100 57 #define GPIO_INT_LVL_LEVEL_HIGH 0x000001 58 #define GPIO_INT_LVL_LEVEL_LOW 0x000000 59 60 struct tegra_gpio_info; 61 62 struct tegra_gpio_bank { 63 unsigned int bank; 64 65 /* 66 * IRQ-core code uses raw locking, and thus, nested locking also 67 * should be raw in order not to trip spinlock debug warnings. 68 */ 69 raw_spinlock_t lvl_lock[4]; 70 71 /* Lock for updating debounce count register */ 72 spinlock_t dbc_lock[4]; 73 74 #ifdef CONFIG_PM_SLEEP 75 u32 cnf[4]; 76 u32 out[4]; 77 u32 oe[4]; 78 u32 int_enb[4]; 79 u32 int_lvl[4]; 80 u32 wake_enb[4]; 81 u32 dbc_enb[4]; 82 #endif 83 u32 dbc_cnt[4]; 84 }; 85 86 struct tegra_gpio_soc_config { 87 bool debounce_supported; 88 u32 bank_stride; 89 u32 upper_offset; 90 }; 91 92 struct tegra_gpio_info { 93 struct device *dev; 94 void __iomem *regs; 95 struct tegra_gpio_bank *bank_info; 96 const struct tegra_gpio_soc_config *soc; 97 struct gpio_chip gc; 98 u32 bank_count; 99 unsigned int *irqs; 100 }; 101 102 static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi, 103 u32 val, u32 reg) 104 { 105 writel_relaxed(val, tgi->regs + reg); 106 } 107 108 static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg) 109 { 110 return readl_relaxed(tgi->regs + reg); 111 } 112 113 static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port, 114 unsigned int bit) 115 { 116 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); 117 } 118 119 static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg, 120 unsigned int gpio, u32 value) 121 { 122 u32 val; 123 124 val = 0x100 << GPIO_BIT(gpio); 125 if (value) 126 val |= 1 << GPIO_BIT(gpio); 127 tegra_gpio_writel(tgi, val, reg); 128 } 129 130 static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio) 131 { 132 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1); 133 } 134 135 static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio) 136 { 137 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0); 138 } 139 140 static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset) 141 { 142 return pinctrl_gpio_request(chip->base + offset); 143 } 144 145 static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset) 146 { 147 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 148 149 pinctrl_gpio_free(chip->base + offset); 150 tegra_gpio_disable(tgi, offset); 151 } 152 153 static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset, 154 int value) 155 { 156 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 157 158 tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value); 159 } 160 161 static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset) 162 { 163 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 164 unsigned int bval = BIT(GPIO_BIT(offset)); 165 166 /* If gpio is in output mode then read from the out value */ 167 if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval) 168 return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval); 169 170 return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval); 171 } 172 173 static int tegra_gpio_direction_input(struct gpio_chip *chip, 174 unsigned int offset) 175 { 176 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 177 int ret; 178 179 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0); 180 tegra_gpio_enable(tgi, offset); 181 182 ret = pinctrl_gpio_direction_input(chip->base + offset); 183 if (ret < 0) 184 dev_err(tgi->dev, 185 "Failed to set pinctrl input direction of GPIO %d: %d", 186 chip->base + offset, ret); 187 188 return ret; 189 } 190 191 static int tegra_gpio_direction_output(struct gpio_chip *chip, 192 unsigned int offset, 193 int value) 194 { 195 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 196 int ret; 197 198 tegra_gpio_set(chip, offset, value); 199 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1); 200 tegra_gpio_enable(tgi, offset); 201 202 ret = pinctrl_gpio_direction_output(chip->base + offset); 203 if (ret < 0) 204 dev_err(tgi->dev, 205 "Failed to set pinctrl output direction of GPIO %d: %d", 206 chip->base + offset, ret); 207 208 return ret; 209 } 210 211 static int tegra_gpio_get_direction(struct gpio_chip *chip, 212 unsigned int offset) 213 { 214 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 215 u32 pin_mask = BIT(GPIO_BIT(offset)); 216 u32 cnf, oe; 217 218 cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset)); 219 if (!(cnf & pin_mask)) 220 return -EINVAL; 221 222 oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)); 223 224 if (oe & pin_mask) 225 return GPIO_LINE_DIRECTION_OUT; 226 227 return GPIO_LINE_DIRECTION_IN; 228 } 229 230 static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset, 231 unsigned int debounce) 232 { 233 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 234 struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)]; 235 unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000); 236 unsigned long flags; 237 unsigned int port; 238 239 if (!debounce_ms) { 240 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), 241 offset, 0); 242 return 0; 243 } 244 245 debounce_ms = min(debounce_ms, 255U); 246 port = GPIO_PORT(offset); 247 248 /* There is only one debounce count register per port and hence 249 * set the maximum of current and requested debounce time. 250 */ 251 spin_lock_irqsave(&bank->dbc_lock[port], flags); 252 if (bank->dbc_cnt[port] < debounce_ms) { 253 tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset)); 254 bank->dbc_cnt[port] = debounce_ms; 255 } 256 spin_unlock_irqrestore(&bank->dbc_lock[port], flags); 257 258 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1); 259 260 return 0; 261 } 262 263 static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 264 unsigned long config) 265 { 266 u32 debounce; 267 268 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 269 return -ENOTSUPP; 270 271 debounce = pinconf_to_config_argument(config); 272 return tegra_gpio_set_debounce(chip, offset, debounce); 273 } 274 275 static void tegra_gpio_irq_ack(struct irq_data *d) 276 { 277 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 278 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 279 unsigned int gpio = d->hwirq; 280 281 tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio)); 282 } 283 284 static void tegra_gpio_irq_mask(struct irq_data *d) 285 { 286 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 287 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 288 unsigned int gpio = d->hwirq; 289 290 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0); 291 gpiochip_disable_irq(chip, gpio); 292 } 293 294 static void tegra_gpio_irq_unmask(struct irq_data *d) 295 { 296 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 297 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 298 unsigned int gpio = d->hwirq; 299 300 gpiochip_enable_irq(chip, gpio); 301 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1); 302 } 303 304 static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) 305 { 306 unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type; 307 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 308 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 309 struct tegra_gpio_bank *bank; 310 unsigned long flags; 311 int ret; 312 u32 val; 313 314 bank = &tgi->bank_info[GPIO_BANK(d->hwirq)]; 315 316 switch (type & IRQ_TYPE_SENSE_MASK) { 317 case IRQ_TYPE_EDGE_RISING: 318 lvl_type = GPIO_INT_LVL_EDGE_RISING; 319 break; 320 321 case IRQ_TYPE_EDGE_FALLING: 322 lvl_type = GPIO_INT_LVL_EDGE_FALLING; 323 break; 324 325 case IRQ_TYPE_EDGE_BOTH: 326 lvl_type = GPIO_INT_LVL_EDGE_BOTH; 327 break; 328 329 case IRQ_TYPE_LEVEL_HIGH: 330 lvl_type = GPIO_INT_LVL_LEVEL_HIGH; 331 break; 332 333 case IRQ_TYPE_LEVEL_LOW: 334 lvl_type = GPIO_INT_LVL_LEVEL_LOW; 335 break; 336 337 default: 338 return -EINVAL; 339 } 340 341 raw_spin_lock_irqsave(&bank->lvl_lock[port], flags); 342 343 val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)); 344 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio)); 345 val |= lvl_type << GPIO_BIT(gpio); 346 tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio)); 347 348 raw_spin_unlock_irqrestore(&bank->lvl_lock[port], flags); 349 350 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0); 351 tegra_gpio_enable(tgi, gpio); 352 353 ret = gpiochip_lock_as_irq(&tgi->gc, gpio); 354 if (ret) { 355 dev_err(tgi->dev, 356 "unable to lock Tegra GPIO %u as IRQ\n", gpio); 357 tegra_gpio_disable(tgi, gpio); 358 return ret; 359 } 360 361 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 362 irq_set_handler_locked(d, handle_level_irq); 363 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 364 irq_set_handler_locked(d, handle_edge_irq); 365 366 if (d->parent_data) 367 ret = irq_chip_set_type_parent(d, type); 368 369 return ret; 370 } 371 372 static void tegra_gpio_irq_shutdown(struct irq_data *d) 373 { 374 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 375 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 376 unsigned int gpio = d->hwirq; 377 378 tegra_gpio_irq_mask(d); 379 gpiochip_unlock_as_irq(&tgi->gc, gpio); 380 } 381 382 static void tegra_gpio_irq_handler(struct irq_desc *desc) 383 { 384 struct tegra_gpio_info *tgi = irq_desc_get_handler_data(desc); 385 struct irq_chip *chip = irq_desc_get_chip(desc); 386 struct irq_domain *domain = tgi->gc.irq.domain; 387 unsigned int irq = irq_desc_get_irq(desc); 388 struct tegra_gpio_bank *bank = NULL; 389 unsigned int port, pin, gpio, i; 390 bool unmasked = false; 391 unsigned long sta; 392 u32 lvl; 393 394 for (i = 0; i < tgi->bank_count; i++) { 395 if (tgi->irqs[i] == irq) { 396 bank = &tgi->bank_info[i]; 397 break; 398 } 399 } 400 401 if (WARN_ON(bank == NULL)) 402 return; 403 404 chained_irq_enter(chip, desc); 405 406 for (port = 0; port < 4; port++) { 407 gpio = tegra_gpio_compose(bank->bank, port, 0); 408 sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) & 409 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)); 410 lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)); 411 412 for_each_set_bit(pin, &sta, 8) { 413 int ret; 414 415 tegra_gpio_writel(tgi, 1 << pin, 416 GPIO_INT_CLR(tgi, gpio)); 417 418 /* if gpio is edge triggered, clear condition 419 * before executing the handler so that we don't 420 * miss edges 421 */ 422 if (!unmasked && lvl & (0x100 << pin)) { 423 unmasked = true; 424 chained_irq_exit(chip, desc); 425 } 426 427 ret = generic_handle_domain_irq(domain, gpio + pin); 428 WARN_RATELIMIT(ret, "hwirq = %d", gpio + pin); 429 } 430 } 431 432 if (!unmasked) 433 chained_irq_exit(chip, desc); 434 } 435 436 static int tegra_gpio_child_to_parent_hwirq(struct gpio_chip *chip, 437 unsigned int hwirq, 438 unsigned int type, 439 unsigned int *parent_hwirq, 440 unsigned int *parent_type) 441 { 442 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq); 443 *parent_type = type; 444 445 return 0; 446 } 447 448 static int tegra_gpio_populate_parent_fwspec(struct gpio_chip *chip, 449 union gpio_irq_fwspec *gfwspec, 450 unsigned int parent_hwirq, 451 unsigned int parent_type) 452 { 453 struct irq_fwspec *fwspec = &gfwspec->fwspec; 454 455 fwspec->fwnode = chip->irq.parent_domain->fwnode; 456 fwspec->param_count = 3; 457 fwspec->param[0] = 0; 458 fwspec->param[1] = parent_hwirq; 459 fwspec->param[2] = parent_type; 460 461 return 0; 462 } 463 464 #ifdef CONFIG_PM_SLEEP 465 static int tegra_gpio_resume(struct device *dev) 466 { 467 struct tegra_gpio_info *tgi = dev_get_drvdata(dev); 468 unsigned int b, p; 469 470 for (b = 0; b < tgi->bank_count; b++) { 471 struct tegra_gpio_bank *bank = &tgi->bank_info[b]; 472 473 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { 474 unsigned int gpio = (b << 5) | (p << 3); 475 476 tegra_gpio_writel(tgi, bank->cnf[p], 477 GPIO_CNF(tgi, gpio)); 478 479 if (tgi->soc->debounce_supported) { 480 tegra_gpio_writel(tgi, bank->dbc_cnt[p], 481 GPIO_DBC_CNT(tgi, gpio)); 482 tegra_gpio_writel(tgi, bank->dbc_enb[p], 483 GPIO_MSK_DBC_EN(tgi, gpio)); 484 } 485 486 tegra_gpio_writel(tgi, bank->out[p], 487 GPIO_OUT(tgi, gpio)); 488 tegra_gpio_writel(tgi, bank->oe[p], 489 GPIO_OE(tgi, gpio)); 490 tegra_gpio_writel(tgi, bank->int_lvl[p], 491 GPIO_INT_LVL(tgi, gpio)); 492 tegra_gpio_writel(tgi, bank->int_enb[p], 493 GPIO_INT_ENB(tgi, gpio)); 494 } 495 } 496 497 return 0; 498 } 499 500 static int tegra_gpio_suspend(struct device *dev) 501 { 502 struct tegra_gpio_info *tgi = dev_get_drvdata(dev); 503 unsigned int b, p; 504 505 for (b = 0; b < tgi->bank_count; b++) { 506 struct tegra_gpio_bank *bank = &tgi->bank_info[b]; 507 508 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { 509 unsigned int gpio = (b << 5) | (p << 3); 510 511 bank->cnf[p] = tegra_gpio_readl(tgi, 512 GPIO_CNF(tgi, gpio)); 513 bank->out[p] = tegra_gpio_readl(tgi, 514 GPIO_OUT(tgi, gpio)); 515 bank->oe[p] = tegra_gpio_readl(tgi, 516 GPIO_OE(tgi, gpio)); 517 if (tgi->soc->debounce_supported) { 518 bank->dbc_enb[p] = tegra_gpio_readl(tgi, 519 GPIO_MSK_DBC_EN(tgi, gpio)); 520 bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) | 521 bank->dbc_enb[p]; 522 } 523 524 bank->int_enb[p] = tegra_gpio_readl(tgi, 525 GPIO_INT_ENB(tgi, gpio)); 526 bank->int_lvl[p] = tegra_gpio_readl(tgi, 527 GPIO_INT_LVL(tgi, gpio)); 528 529 /* Enable gpio irq for wake up source */ 530 tegra_gpio_writel(tgi, bank->wake_enb[p], 531 GPIO_INT_ENB(tgi, gpio)); 532 } 533 } 534 535 return 0; 536 } 537 538 static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable) 539 { 540 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 541 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 542 struct tegra_gpio_bank *bank; 543 unsigned int gpio = d->hwirq; 544 u32 port, bit, mask; 545 int err; 546 547 bank = &tgi->bank_info[GPIO_BANK(d->hwirq)]; 548 549 port = GPIO_PORT(gpio); 550 bit = GPIO_BIT(gpio); 551 mask = BIT(bit); 552 553 err = irq_set_irq_wake(tgi->irqs[bank->bank], enable); 554 if (err) 555 return err; 556 557 if (d->parent_data) { 558 err = irq_chip_set_wake_parent(d, enable); 559 if (err) { 560 irq_set_irq_wake(tgi->irqs[bank->bank], !enable); 561 return err; 562 } 563 } 564 565 if (enable) 566 bank->wake_enb[port] |= mask; 567 else 568 bank->wake_enb[port] &= ~mask; 569 570 return 0; 571 } 572 #endif 573 574 static int tegra_gpio_irq_set_affinity(struct irq_data *data, 575 const struct cpumask *dest, 576 bool force) 577 { 578 if (data->parent_data) 579 return irq_chip_set_affinity_parent(data, dest, force); 580 581 return -EINVAL; 582 } 583 584 static int tegra_gpio_irq_request_resources(struct irq_data *d) 585 { 586 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 587 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 588 589 tegra_gpio_enable(tgi, d->hwirq); 590 591 return gpiochip_reqres_irq(chip, d->hwirq); 592 } 593 594 static void tegra_gpio_irq_release_resources(struct irq_data *d) 595 { 596 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 597 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 598 599 gpiochip_relres_irq(chip, d->hwirq); 600 tegra_gpio_enable(tgi, d->hwirq); 601 } 602 603 static void tegra_gpio_irq_print_chip(struct irq_data *d, struct seq_file *s) 604 { 605 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 606 607 seq_printf(s, dev_name(chip->parent)); 608 } 609 610 static const struct irq_chip tegra_gpio_irq_chip = { 611 .irq_shutdown = tegra_gpio_irq_shutdown, 612 .irq_ack = tegra_gpio_irq_ack, 613 .irq_mask = tegra_gpio_irq_mask, 614 .irq_unmask = tegra_gpio_irq_unmask, 615 .irq_set_type = tegra_gpio_irq_set_type, 616 #ifdef CONFIG_PM_SLEEP 617 .irq_set_wake = tegra_gpio_irq_set_wake, 618 #endif 619 .irq_print_chip = tegra_gpio_irq_print_chip, 620 .irq_request_resources = tegra_gpio_irq_request_resources, 621 .irq_release_resources = tegra_gpio_irq_release_resources, 622 .flags = IRQCHIP_IMMUTABLE, 623 }; 624 625 static const struct irq_chip tegra210_gpio_irq_chip = { 626 .irq_shutdown = tegra_gpio_irq_shutdown, 627 .irq_ack = tegra_gpio_irq_ack, 628 .irq_mask = tegra_gpio_irq_mask, 629 .irq_unmask = tegra_gpio_irq_unmask, 630 .irq_set_affinity = tegra_gpio_irq_set_affinity, 631 .irq_set_type = tegra_gpio_irq_set_type, 632 #ifdef CONFIG_PM_SLEEP 633 .irq_set_wake = tegra_gpio_irq_set_wake, 634 #endif 635 .irq_print_chip = tegra_gpio_irq_print_chip, 636 .irq_request_resources = tegra_gpio_irq_request_resources, 637 .irq_release_resources = tegra_gpio_irq_release_resources, 638 .flags = IRQCHIP_IMMUTABLE, 639 }; 640 641 #ifdef CONFIG_DEBUG_FS 642 643 #include <linux/debugfs.h> 644 645 static int tegra_dbg_gpio_show(struct seq_file *s, void *unused) 646 { 647 struct tegra_gpio_info *tgi = dev_get_drvdata(s->private); 648 unsigned int i, j; 649 650 for (i = 0; i < tgi->bank_count; i++) { 651 for (j = 0; j < 4; j++) { 652 unsigned int gpio = tegra_gpio_compose(i, j, 0); 653 654 seq_printf(s, 655 "%u:%u %02x %02x %02x %02x %02x %02x %06x\n", 656 i, j, 657 tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)), 658 tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)), 659 tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)), 660 tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)), 661 tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)), 662 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)), 663 tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio))); 664 } 665 } 666 return 0; 667 } 668 669 static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi) 670 { 671 debugfs_create_devm_seqfile(tgi->dev, "tegra_gpio", NULL, 672 tegra_dbg_gpio_show); 673 } 674 675 #else 676 677 static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi) 678 { 679 } 680 681 #endif 682 683 static const struct dev_pm_ops tegra_gpio_pm_ops = { 684 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume) 685 }; 686 687 static const struct of_device_id tegra_pmc_of_match[] = { 688 { .compatible = "nvidia,tegra210-pmc", }, 689 { /* sentinel */ }, 690 }; 691 692 static int tegra_gpio_probe(struct platform_device *pdev) 693 { 694 struct tegra_gpio_bank *bank; 695 struct tegra_gpio_info *tgi; 696 struct gpio_irq_chip *irq; 697 struct device_node *np; 698 unsigned int i, j; 699 int ret; 700 701 tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL); 702 if (!tgi) 703 return -ENODEV; 704 705 tgi->soc = of_device_get_match_data(&pdev->dev); 706 tgi->dev = &pdev->dev; 707 708 ret = platform_irq_count(pdev); 709 if (ret < 0) 710 return ret; 711 712 tgi->bank_count = ret; 713 714 if (!tgi->bank_count) { 715 dev_err(&pdev->dev, "Missing IRQ resource\n"); 716 return -ENODEV; 717 } 718 719 tgi->gc.label = "tegra-gpio"; 720 tgi->gc.request = tegra_gpio_request; 721 tgi->gc.free = tegra_gpio_free; 722 tgi->gc.direction_input = tegra_gpio_direction_input; 723 tgi->gc.get = tegra_gpio_get; 724 tgi->gc.direction_output = tegra_gpio_direction_output; 725 tgi->gc.set = tegra_gpio_set; 726 tgi->gc.get_direction = tegra_gpio_get_direction; 727 tgi->gc.base = 0; 728 tgi->gc.ngpio = tgi->bank_count * 32; 729 tgi->gc.parent = &pdev->dev; 730 731 platform_set_drvdata(pdev, tgi); 732 733 if (tgi->soc->debounce_supported) 734 tgi->gc.set_config = tegra_gpio_set_config; 735 736 tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count, 737 sizeof(*tgi->bank_info), GFP_KERNEL); 738 if (!tgi->bank_info) 739 return -ENOMEM; 740 741 tgi->irqs = devm_kcalloc(&pdev->dev, tgi->bank_count, 742 sizeof(*tgi->irqs), GFP_KERNEL); 743 if (!tgi->irqs) 744 return -ENOMEM; 745 746 for (i = 0; i < tgi->bank_count; i++) { 747 ret = platform_get_irq(pdev, i); 748 if (ret < 0) 749 return ret; 750 751 bank = &tgi->bank_info[i]; 752 bank->bank = i; 753 754 tgi->irqs[i] = ret; 755 756 for (j = 0; j < 4; j++) { 757 raw_spin_lock_init(&bank->lvl_lock[j]); 758 spin_lock_init(&bank->dbc_lock[j]); 759 } 760 } 761 762 irq = &tgi->gc.irq; 763 irq->fwnode = of_node_to_fwnode(pdev->dev.of_node); 764 irq->child_to_parent_hwirq = tegra_gpio_child_to_parent_hwirq; 765 irq->populate_parent_alloc_arg = tegra_gpio_populate_parent_fwspec; 766 irq->handler = handle_simple_irq; 767 irq->default_type = IRQ_TYPE_NONE; 768 irq->parent_handler = tegra_gpio_irq_handler; 769 irq->parent_handler_data = tgi; 770 irq->num_parents = tgi->bank_count; 771 irq->parents = tgi->irqs; 772 773 np = of_find_matching_node(NULL, tegra_pmc_of_match); 774 if (np) { 775 irq->parent_domain = irq_find_host(np); 776 of_node_put(np); 777 778 if (!irq->parent_domain) 779 return -EPROBE_DEFER; 780 781 gpio_irq_chip_set_chip(irq, &tegra210_gpio_irq_chip); 782 } else { 783 gpio_irq_chip_set_chip(irq, &tegra_gpio_irq_chip); 784 } 785 786 tgi->regs = devm_platform_ioremap_resource(pdev, 0); 787 if (IS_ERR(tgi->regs)) 788 return PTR_ERR(tgi->regs); 789 790 for (i = 0; i < tgi->bank_count; i++) { 791 for (j = 0; j < 4; j++) { 792 int gpio = tegra_gpio_compose(i, j, 0); 793 794 tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio)); 795 } 796 } 797 798 ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi); 799 if (ret < 0) 800 return ret; 801 802 tegra_gpio_debuginit(tgi); 803 804 return 0; 805 } 806 807 static const struct tegra_gpio_soc_config tegra20_gpio_config = { 808 .bank_stride = 0x80, 809 .upper_offset = 0x800, 810 }; 811 812 static const struct tegra_gpio_soc_config tegra30_gpio_config = { 813 .bank_stride = 0x100, 814 .upper_offset = 0x80, 815 }; 816 817 static const struct tegra_gpio_soc_config tegra210_gpio_config = { 818 .debounce_supported = true, 819 .bank_stride = 0x100, 820 .upper_offset = 0x80, 821 }; 822 823 static const struct of_device_id tegra_gpio_of_match[] = { 824 { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config }, 825 { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config }, 826 { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config }, 827 { }, 828 }; 829 MODULE_DEVICE_TABLE(of, tegra_gpio_of_match); 830 831 static struct platform_driver tegra_gpio_driver = { 832 .driver = { 833 .name = "tegra-gpio", 834 .pm = &tegra_gpio_pm_ops, 835 .of_match_table = tegra_gpio_of_match, 836 }, 837 .probe = tegra_gpio_probe, 838 }; 839 module_platform_driver(tegra_gpio_driver); 840 841 MODULE_DESCRIPTION("NVIDIA Tegra GPIO controller driver"); 842 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>"); 843 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); 844 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 845 MODULE_AUTHOR("Erik Gilling <konkers@google.com>"); 846 MODULE_LICENSE("GPL v2"); 847