1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * arch/arm/mach-tegra/gpio.c 4 * 5 * Copyright (c) 2010 Google, Inc 6 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. 7 * 8 * Author: 9 * Erik Gilling <konkers@google.com> 10 */ 11 12 #include <linux/err.h> 13 #include <linux/init.h> 14 #include <linux/irq.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/of_device.h> 19 #include <linux/platform_device.h> 20 #include <linux/module.h> 21 #include <linux/irqdomain.h> 22 #include <linux/irqchip/chained_irq.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pm.h> 25 26 #define GPIO_BANK(x) ((x) >> 5) 27 #define GPIO_PORT(x) (((x) >> 3) & 0x3) 28 #define GPIO_BIT(x) ((x) & 0x7) 29 30 #define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \ 31 GPIO_PORT(x) * 4) 32 33 #define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00) 34 #define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10) 35 #define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20) 36 #define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30) 37 #define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40) 38 #define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50) 39 #define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60) 40 #define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70) 41 #define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0) 42 43 44 #define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00) 45 #define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10) 46 #define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20) 47 #define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30) 48 #define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40) 49 #define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50) 50 #define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60) 51 52 #define GPIO_INT_LVL_MASK 0x010101 53 #define GPIO_INT_LVL_EDGE_RISING 0x000101 54 #define GPIO_INT_LVL_EDGE_FALLING 0x000100 55 #define GPIO_INT_LVL_EDGE_BOTH 0x010100 56 #define GPIO_INT_LVL_LEVEL_HIGH 0x000001 57 #define GPIO_INT_LVL_LEVEL_LOW 0x000000 58 59 struct tegra_gpio_info; 60 61 struct tegra_gpio_bank { 62 unsigned int bank; 63 unsigned int irq; 64 spinlock_t lvl_lock[4]; 65 spinlock_t dbc_lock[4]; /* Lock for updating debounce count register */ 66 #ifdef CONFIG_PM_SLEEP 67 u32 cnf[4]; 68 u32 out[4]; 69 u32 oe[4]; 70 u32 int_enb[4]; 71 u32 int_lvl[4]; 72 u32 wake_enb[4]; 73 u32 dbc_enb[4]; 74 #endif 75 u32 dbc_cnt[4]; 76 struct tegra_gpio_info *tgi; 77 }; 78 79 struct tegra_gpio_soc_config { 80 bool debounce_supported; 81 u32 bank_stride; 82 u32 upper_offset; 83 }; 84 85 struct tegra_gpio_info { 86 struct device *dev; 87 void __iomem *regs; 88 struct irq_domain *irq_domain; 89 struct tegra_gpio_bank *bank_info; 90 const struct tegra_gpio_soc_config *soc; 91 struct gpio_chip gc; 92 struct irq_chip ic; 93 u32 bank_count; 94 }; 95 96 static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi, 97 u32 val, u32 reg) 98 { 99 __raw_writel(val, tgi->regs + reg); 100 } 101 102 static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg) 103 { 104 return __raw_readl(tgi->regs + reg); 105 } 106 107 static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port, 108 unsigned int bit) 109 { 110 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); 111 } 112 113 static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg, 114 unsigned int gpio, u32 value) 115 { 116 u32 val; 117 118 val = 0x100 << GPIO_BIT(gpio); 119 if (value) 120 val |= 1 << GPIO_BIT(gpio); 121 tegra_gpio_writel(tgi, val, reg); 122 } 123 124 static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio) 125 { 126 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1); 127 } 128 129 static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio) 130 { 131 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0); 132 } 133 134 static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset) 135 { 136 return pinctrl_gpio_request(chip->base + offset); 137 } 138 139 static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset) 140 { 141 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 142 143 pinctrl_gpio_free(chip->base + offset); 144 tegra_gpio_disable(tgi, offset); 145 } 146 147 static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset, 148 int value) 149 { 150 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 151 152 tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value); 153 } 154 155 static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset) 156 { 157 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 158 unsigned int bval = BIT(GPIO_BIT(offset)); 159 160 /* If gpio is in output mode then read from the out value */ 161 if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval) 162 return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval); 163 164 return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval); 165 } 166 167 static int tegra_gpio_direction_input(struct gpio_chip *chip, 168 unsigned int offset) 169 { 170 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 171 int ret; 172 173 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0); 174 tegra_gpio_enable(tgi, offset); 175 176 ret = pinctrl_gpio_direction_input(chip->base + offset); 177 if (ret < 0) 178 dev_err(tgi->dev, 179 "Failed to set pinctrl input direction of GPIO %d: %d", 180 chip->base + offset, ret); 181 182 return ret; 183 } 184 185 static int tegra_gpio_direction_output(struct gpio_chip *chip, 186 unsigned int offset, 187 int value) 188 { 189 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 190 int ret; 191 192 tegra_gpio_set(chip, offset, value); 193 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1); 194 tegra_gpio_enable(tgi, offset); 195 196 ret = pinctrl_gpio_direction_output(chip->base + offset); 197 if (ret < 0) 198 dev_err(tgi->dev, 199 "Failed to set pinctrl output direction of GPIO %d: %d", 200 chip->base + offset, ret); 201 202 return ret; 203 } 204 205 static int tegra_gpio_get_direction(struct gpio_chip *chip, 206 unsigned int offset) 207 { 208 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 209 u32 pin_mask = BIT(GPIO_BIT(offset)); 210 u32 cnf, oe; 211 212 cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset)); 213 if (!(cnf & pin_mask)) 214 return -EINVAL; 215 216 oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)); 217 218 return !(oe & pin_mask); 219 } 220 221 static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset, 222 unsigned int debounce) 223 { 224 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 225 struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)]; 226 unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000); 227 unsigned long flags; 228 unsigned int port; 229 230 if (!debounce_ms) { 231 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), 232 offset, 0); 233 return 0; 234 } 235 236 debounce_ms = min(debounce_ms, 255U); 237 port = GPIO_PORT(offset); 238 239 /* There is only one debounce count register per port and hence 240 * set the maximum of current and requested debounce time. 241 */ 242 spin_lock_irqsave(&bank->dbc_lock[port], flags); 243 if (bank->dbc_cnt[port] < debounce_ms) { 244 tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset)); 245 bank->dbc_cnt[port] = debounce_ms; 246 } 247 spin_unlock_irqrestore(&bank->dbc_lock[port], flags); 248 249 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1); 250 251 return 0; 252 } 253 254 static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 255 unsigned long config) 256 { 257 u32 debounce; 258 259 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 260 return -ENOTSUPP; 261 262 debounce = pinconf_to_config_argument(config); 263 return tegra_gpio_set_debounce(chip, offset, debounce); 264 } 265 266 static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) 267 { 268 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 269 270 return irq_find_mapping(tgi->irq_domain, offset); 271 } 272 273 static void tegra_gpio_irq_ack(struct irq_data *d) 274 { 275 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 276 struct tegra_gpio_info *tgi = bank->tgi; 277 unsigned int gpio = d->hwirq; 278 279 tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio)); 280 } 281 282 static void tegra_gpio_irq_mask(struct irq_data *d) 283 { 284 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 285 struct tegra_gpio_info *tgi = bank->tgi; 286 unsigned int gpio = d->hwirq; 287 288 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0); 289 } 290 291 static void tegra_gpio_irq_unmask(struct irq_data *d) 292 { 293 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 294 struct tegra_gpio_info *tgi = bank->tgi; 295 unsigned int gpio = d->hwirq; 296 297 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1); 298 } 299 300 static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) 301 { 302 unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type; 303 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 304 struct tegra_gpio_info *tgi = bank->tgi; 305 unsigned long flags; 306 u32 val; 307 int ret; 308 309 switch (type & IRQ_TYPE_SENSE_MASK) { 310 case IRQ_TYPE_EDGE_RISING: 311 lvl_type = GPIO_INT_LVL_EDGE_RISING; 312 break; 313 314 case IRQ_TYPE_EDGE_FALLING: 315 lvl_type = GPIO_INT_LVL_EDGE_FALLING; 316 break; 317 318 case IRQ_TYPE_EDGE_BOTH: 319 lvl_type = GPIO_INT_LVL_EDGE_BOTH; 320 break; 321 322 case IRQ_TYPE_LEVEL_HIGH: 323 lvl_type = GPIO_INT_LVL_LEVEL_HIGH; 324 break; 325 326 case IRQ_TYPE_LEVEL_LOW: 327 lvl_type = GPIO_INT_LVL_LEVEL_LOW; 328 break; 329 330 default: 331 return -EINVAL; 332 } 333 334 spin_lock_irqsave(&bank->lvl_lock[port], flags); 335 336 val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)); 337 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio)); 338 val |= lvl_type << GPIO_BIT(gpio); 339 tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio)); 340 341 spin_unlock_irqrestore(&bank->lvl_lock[port], flags); 342 343 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0); 344 tegra_gpio_enable(tgi, gpio); 345 346 ret = gpiochip_lock_as_irq(&tgi->gc, gpio); 347 if (ret) { 348 dev_err(tgi->dev, 349 "unable to lock Tegra GPIO %u as IRQ\n", gpio); 350 tegra_gpio_disable(tgi, gpio); 351 return ret; 352 } 353 354 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 355 irq_set_handler_locked(d, handle_level_irq); 356 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 357 irq_set_handler_locked(d, handle_edge_irq); 358 359 return 0; 360 } 361 362 static void tegra_gpio_irq_shutdown(struct irq_data *d) 363 { 364 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 365 struct tegra_gpio_info *tgi = bank->tgi; 366 unsigned int gpio = d->hwirq; 367 368 gpiochip_unlock_as_irq(&tgi->gc, gpio); 369 } 370 371 static void tegra_gpio_irq_handler(struct irq_desc *desc) 372 { 373 unsigned int port, pin, gpio; 374 bool unmasked = false; 375 u32 lvl; 376 unsigned long sta; 377 struct irq_chip *chip = irq_desc_get_chip(desc); 378 struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc); 379 struct tegra_gpio_info *tgi = bank->tgi; 380 381 chained_irq_enter(chip, desc); 382 383 for (port = 0; port < 4; port++) { 384 gpio = tegra_gpio_compose(bank->bank, port, 0); 385 sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) & 386 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)); 387 lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)); 388 389 for_each_set_bit(pin, &sta, 8) { 390 tegra_gpio_writel(tgi, 1 << pin, 391 GPIO_INT_CLR(tgi, gpio)); 392 393 /* if gpio is edge triggered, clear condition 394 * before executing the handler so that we don't 395 * miss edges 396 */ 397 if (!unmasked && lvl & (0x100 << pin)) { 398 unmasked = true; 399 chained_irq_exit(chip, desc); 400 } 401 402 generic_handle_irq(irq_find_mapping(tgi->irq_domain, 403 gpio + pin)); 404 } 405 } 406 407 if (!unmasked) 408 chained_irq_exit(chip, desc); 409 410 } 411 412 #ifdef CONFIG_PM_SLEEP 413 static int tegra_gpio_resume(struct device *dev) 414 { 415 struct tegra_gpio_info *tgi = dev_get_drvdata(dev); 416 unsigned long flags; 417 unsigned int b, p; 418 419 local_irq_save(flags); 420 421 for (b = 0; b < tgi->bank_count; b++) { 422 struct tegra_gpio_bank *bank = &tgi->bank_info[b]; 423 424 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { 425 unsigned int gpio = (b << 5) | (p << 3); 426 427 tegra_gpio_writel(tgi, bank->cnf[p], 428 GPIO_CNF(tgi, gpio)); 429 430 if (tgi->soc->debounce_supported) { 431 tegra_gpio_writel(tgi, bank->dbc_cnt[p], 432 GPIO_DBC_CNT(tgi, gpio)); 433 tegra_gpio_writel(tgi, bank->dbc_enb[p], 434 GPIO_MSK_DBC_EN(tgi, gpio)); 435 } 436 437 tegra_gpio_writel(tgi, bank->out[p], 438 GPIO_OUT(tgi, gpio)); 439 tegra_gpio_writel(tgi, bank->oe[p], 440 GPIO_OE(tgi, gpio)); 441 tegra_gpio_writel(tgi, bank->int_lvl[p], 442 GPIO_INT_LVL(tgi, gpio)); 443 tegra_gpio_writel(tgi, bank->int_enb[p], 444 GPIO_INT_ENB(tgi, gpio)); 445 } 446 } 447 448 local_irq_restore(flags); 449 return 0; 450 } 451 452 static int tegra_gpio_suspend(struct device *dev) 453 { 454 struct tegra_gpio_info *tgi = dev_get_drvdata(dev); 455 unsigned long flags; 456 unsigned int b, p; 457 458 local_irq_save(flags); 459 for (b = 0; b < tgi->bank_count; b++) { 460 struct tegra_gpio_bank *bank = &tgi->bank_info[b]; 461 462 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { 463 unsigned int gpio = (b << 5) | (p << 3); 464 465 bank->cnf[p] = tegra_gpio_readl(tgi, 466 GPIO_CNF(tgi, gpio)); 467 bank->out[p] = tegra_gpio_readl(tgi, 468 GPIO_OUT(tgi, gpio)); 469 bank->oe[p] = tegra_gpio_readl(tgi, 470 GPIO_OE(tgi, gpio)); 471 if (tgi->soc->debounce_supported) { 472 bank->dbc_enb[p] = tegra_gpio_readl(tgi, 473 GPIO_MSK_DBC_EN(tgi, gpio)); 474 bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) | 475 bank->dbc_enb[p]; 476 } 477 478 bank->int_enb[p] = tegra_gpio_readl(tgi, 479 GPIO_INT_ENB(tgi, gpio)); 480 bank->int_lvl[p] = tegra_gpio_readl(tgi, 481 GPIO_INT_LVL(tgi, gpio)); 482 483 /* Enable gpio irq for wake up source */ 484 tegra_gpio_writel(tgi, bank->wake_enb[p], 485 GPIO_INT_ENB(tgi, gpio)); 486 } 487 } 488 local_irq_restore(flags); 489 return 0; 490 } 491 492 static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable) 493 { 494 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 495 unsigned int gpio = d->hwirq; 496 u32 port, bit, mask; 497 498 port = GPIO_PORT(gpio); 499 bit = GPIO_BIT(gpio); 500 mask = BIT(bit); 501 502 if (enable) 503 bank->wake_enb[port] |= mask; 504 else 505 bank->wake_enb[port] &= ~mask; 506 507 return irq_set_irq_wake(bank->irq, enable); 508 } 509 #endif 510 511 #ifdef CONFIG_DEBUG_FS 512 513 #include <linux/debugfs.h> 514 #include <linux/seq_file.h> 515 516 static int tegra_dbg_gpio_show(struct seq_file *s, void *unused) 517 { 518 struct tegra_gpio_info *tgi = s->private; 519 unsigned int i, j; 520 521 for (i = 0; i < tgi->bank_count; i++) { 522 for (j = 0; j < 4; j++) { 523 unsigned int gpio = tegra_gpio_compose(i, j, 0); 524 525 seq_printf(s, 526 "%u:%u %02x %02x %02x %02x %02x %02x %06x\n", 527 i, j, 528 tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)), 529 tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)), 530 tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)), 531 tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)), 532 tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)), 533 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)), 534 tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio))); 535 } 536 } 537 return 0; 538 } 539 540 DEFINE_SHOW_ATTRIBUTE(tegra_dbg_gpio); 541 542 static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi) 543 { 544 debugfs_create_file("tegra_gpio", 0444, NULL, tgi, 545 &tegra_dbg_gpio_fops); 546 } 547 548 #else 549 550 static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi) 551 { 552 } 553 554 #endif 555 556 static const struct dev_pm_ops tegra_gpio_pm_ops = { 557 SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume) 558 }; 559 560 static int tegra_gpio_probe(struct platform_device *pdev) 561 { 562 struct tegra_gpio_info *tgi; 563 struct tegra_gpio_bank *bank; 564 unsigned int gpio, i, j; 565 int ret; 566 567 tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL); 568 if (!tgi) 569 return -ENODEV; 570 571 tgi->soc = of_device_get_match_data(&pdev->dev); 572 tgi->dev = &pdev->dev; 573 574 ret = platform_irq_count(pdev); 575 if (ret < 0) 576 return ret; 577 578 tgi->bank_count = ret; 579 580 if (!tgi->bank_count) { 581 dev_err(&pdev->dev, "Missing IRQ resource\n"); 582 return -ENODEV; 583 } 584 585 tgi->gc.label = "tegra-gpio"; 586 tgi->gc.request = tegra_gpio_request; 587 tgi->gc.free = tegra_gpio_free; 588 tgi->gc.direction_input = tegra_gpio_direction_input; 589 tgi->gc.get = tegra_gpio_get; 590 tgi->gc.direction_output = tegra_gpio_direction_output; 591 tgi->gc.set = tegra_gpio_set; 592 tgi->gc.get_direction = tegra_gpio_get_direction; 593 tgi->gc.to_irq = tegra_gpio_to_irq; 594 tgi->gc.base = 0; 595 tgi->gc.ngpio = tgi->bank_count * 32; 596 tgi->gc.parent = &pdev->dev; 597 tgi->gc.of_node = pdev->dev.of_node; 598 599 tgi->ic.name = "GPIO"; 600 tgi->ic.irq_ack = tegra_gpio_irq_ack; 601 tgi->ic.irq_mask = tegra_gpio_irq_mask; 602 tgi->ic.irq_unmask = tegra_gpio_irq_unmask; 603 tgi->ic.irq_set_type = tegra_gpio_irq_set_type; 604 tgi->ic.irq_shutdown = tegra_gpio_irq_shutdown; 605 #ifdef CONFIG_PM_SLEEP 606 tgi->ic.irq_set_wake = tegra_gpio_irq_set_wake; 607 #endif 608 609 platform_set_drvdata(pdev, tgi); 610 611 if (tgi->soc->debounce_supported) 612 tgi->gc.set_config = tegra_gpio_set_config; 613 614 tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count, 615 sizeof(*tgi->bank_info), GFP_KERNEL); 616 if (!tgi->bank_info) 617 return -ENOMEM; 618 619 tgi->irq_domain = irq_domain_add_linear(pdev->dev.of_node, 620 tgi->gc.ngpio, 621 &irq_domain_simple_ops, NULL); 622 if (!tgi->irq_domain) 623 return -ENODEV; 624 625 for (i = 0; i < tgi->bank_count; i++) { 626 ret = platform_get_irq(pdev, i); 627 if (ret < 0) { 628 dev_err(&pdev->dev, "Missing IRQ resource: %d\n", ret); 629 return ret; 630 } 631 632 bank = &tgi->bank_info[i]; 633 bank->bank = i; 634 bank->irq = ret; 635 bank->tgi = tgi; 636 } 637 638 tgi->regs = devm_platform_ioremap_resource(pdev, 0); 639 if (IS_ERR(tgi->regs)) 640 return PTR_ERR(tgi->regs); 641 642 for (i = 0; i < tgi->bank_count; i++) { 643 for (j = 0; j < 4; j++) { 644 int gpio = tegra_gpio_compose(i, j, 0); 645 646 tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio)); 647 } 648 } 649 650 ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi); 651 if (ret < 0) { 652 irq_domain_remove(tgi->irq_domain); 653 return ret; 654 } 655 656 for (gpio = 0; gpio < tgi->gc.ngpio; gpio++) { 657 int irq = irq_create_mapping(tgi->irq_domain, gpio); 658 /* No validity check; all Tegra GPIOs are valid IRQs */ 659 660 bank = &tgi->bank_info[GPIO_BANK(gpio)]; 661 662 irq_set_chip_data(irq, bank); 663 irq_set_chip_and_handler(irq, &tgi->ic, handle_simple_irq); 664 } 665 666 for (i = 0; i < tgi->bank_count; i++) { 667 bank = &tgi->bank_info[i]; 668 669 irq_set_chained_handler_and_data(bank->irq, 670 tegra_gpio_irq_handler, bank); 671 672 for (j = 0; j < 4; j++) { 673 spin_lock_init(&bank->lvl_lock[j]); 674 spin_lock_init(&bank->dbc_lock[j]); 675 } 676 } 677 678 tegra_gpio_debuginit(tgi); 679 680 return 0; 681 } 682 683 static const struct tegra_gpio_soc_config tegra20_gpio_config = { 684 .bank_stride = 0x80, 685 .upper_offset = 0x800, 686 }; 687 688 static const struct tegra_gpio_soc_config tegra30_gpio_config = { 689 .bank_stride = 0x100, 690 .upper_offset = 0x80, 691 }; 692 693 static const struct tegra_gpio_soc_config tegra210_gpio_config = { 694 .debounce_supported = true, 695 .bank_stride = 0x100, 696 .upper_offset = 0x80, 697 }; 698 699 static const struct of_device_id tegra_gpio_of_match[] = { 700 { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config }, 701 { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config }, 702 { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config }, 703 { }, 704 }; 705 706 static struct platform_driver tegra_gpio_driver = { 707 .driver = { 708 .name = "tegra-gpio", 709 .pm = &tegra_gpio_pm_ops, 710 .of_match_table = tegra_gpio_of_match, 711 }, 712 .probe = tegra_gpio_probe, 713 }; 714 715 static int __init tegra_gpio_init(void) 716 { 717 return platform_driver_register(&tegra_gpio_driver); 718 } 719 subsys_initcall(tegra_gpio_init); 720