xref: /openbmc/linux/drivers/gpio/gpio-tb10x.c (revision b85d4594)
1 /* Abilis Systems MODULE DESCRIPTION
2  *
3  * Copyright (C) Abilis Systems 2013
4  *
5  * Authors: Sascha Leuenberger <sascha.leuenberger@abilis.com>
6  *          Christian Ruppert <christian.ruppert@abilis.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
20  */
21 
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/gpio.h>
26 #include <linux/slab.h>
27 #include <linux/irq.h>
28 #include <linux/irqdomain.h>
29 #include <linux/interrupt.h>
30 #include <linux/io.h>
31 #include <linux/of.h>
32 #include <linux/of_platform.h>
33 #include <linux/of_gpio.h>
34 #include <linux/spinlock.h>
35 #include <linux/bitops.h>
36 #include <linux/pinctrl/consumer.h>
37 
38 #define TB10X_GPIO_DIR_IN	(0x00000000)
39 #define TB10X_GPIO_DIR_OUT	(0x00000001)
40 #define OFFSET_TO_REG_DDR	(0x00)
41 #define OFFSET_TO_REG_DATA	(0x04)
42 #define OFFSET_TO_REG_INT_EN	(0x08)
43 #define OFFSET_TO_REG_CHANGE	(0x0C)
44 #define OFFSET_TO_REG_WRMASK	(0x10)
45 #define OFFSET_TO_REG_INT_TYPE	(0x14)
46 
47 
48 /**
49  * @spinlock: used for atomic read/modify/write of registers
50  * @base: register base address
51  * @domain: IRQ domain of GPIO generated interrupts managed by this controller
52  * @irq: Interrupt line of parent interrupt controller
53  * @gc: gpio_chip structure associated to this GPIO controller
54  */
55 struct tb10x_gpio {
56 	spinlock_t spinlock;
57 	void __iomem *base;
58 	struct irq_domain *domain;
59 	int irq;
60 	struct gpio_chip gc;
61 };
62 
63 static inline u32 tb10x_reg_read(struct tb10x_gpio *gpio, unsigned int offs)
64 {
65 	return ioread32(gpio->base + offs);
66 }
67 
68 static inline void tb10x_reg_write(struct tb10x_gpio *gpio, unsigned int offs,
69 				u32 val)
70 {
71 	iowrite32(val, gpio->base + offs);
72 }
73 
74 static inline void tb10x_set_bits(struct tb10x_gpio *gpio, unsigned int offs,
75 				u32 mask, u32 val)
76 {
77 	u32 r;
78 	unsigned long flags;
79 
80 	spin_lock_irqsave(&gpio->spinlock, flags);
81 
82 	r = tb10x_reg_read(gpio, offs);
83 	r = (r & ~mask) | (val & mask);
84 
85 	tb10x_reg_write(gpio, offs, r);
86 
87 	spin_unlock_irqrestore(&gpio->spinlock, flags);
88 }
89 
90 static inline struct tb10x_gpio *to_tb10x_gpio(struct gpio_chip *chip)
91 {
92 	return container_of(chip, struct tb10x_gpio, gc);
93 }
94 
95 static int tb10x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
96 {
97 	struct tb10x_gpio *tb10x_gpio = to_tb10x_gpio(chip);
98 	int mask = BIT(offset);
99 	int val = TB10X_GPIO_DIR_IN << offset;
100 
101 	tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DDR, mask, val);
102 
103 	return 0;
104 }
105 
106 static int tb10x_gpio_get(struct gpio_chip *chip, unsigned offset)
107 {
108 	struct tb10x_gpio *tb10x_gpio = to_tb10x_gpio(chip);
109 	int val;
110 
111 	val = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_DATA);
112 
113 	if (val & BIT(offset))
114 		return 1;
115 	else
116 		return 0;
117 }
118 
119 static void tb10x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
120 {
121 	struct tb10x_gpio *tb10x_gpio = to_tb10x_gpio(chip);
122 	int mask = BIT(offset);
123 	int val = value << offset;
124 
125 	tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DATA, mask, val);
126 }
127 
128 static int tb10x_gpio_direction_out(struct gpio_chip *chip,
129 					unsigned offset, int value)
130 {
131 	struct tb10x_gpio *tb10x_gpio = to_tb10x_gpio(chip);
132 	int mask = BIT(offset);
133 	int val = TB10X_GPIO_DIR_OUT << offset;
134 
135 	tb10x_gpio_set(chip, offset, value);
136 	tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DDR, mask, val);
137 
138 	return 0;
139 }
140 
141 static int tb10x_gpio_request(struct gpio_chip *chip, unsigned offset)
142 {
143 	return pinctrl_request_gpio(chip->base + offset);
144 }
145 
146 static void tb10x_gpio_free(struct gpio_chip *chip, unsigned offset)
147 {
148 	pinctrl_free_gpio(chip->base + offset);
149 }
150 
151 static int tb10x_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
152 {
153 	struct tb10x_gpio *tb10x_gpio = to_tb10x_gpio(chip);
154 
155 	return irq_create_mapping(tb10x_gpio->domain, offset);
156 }
157 
158 static int tb10x_gpio_irq_set_type(struct irq_data *data, unsigned int type)
159 {
160 	if ((type & IRQF_TRIGGER_MASK) != IRQ_TYPE_EDGE_BOTH) {
161 		pr_err("Only (both) edge triggered interrupts supported.\n");
162 		return -EINVAL;
163 	}
164 
165 	irqd_set_trigger_type(data, type);
166 
167 	return IRQ_SET_MASK_OK;
168 }
169 
170 static irqreturn_t tb10x_gpio_irq_cascade(int irq, void *data)
171 {
172 	struct tb10x_gpio *tb10x_gpio = data;
173 	u32 r = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_CHANGE);
174 	u32 m = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_INT_EN);
175 	const unsigned long bits = r & m;
176 	int i;
177 
178 	for_each_set_bit(i, &bits, 32)
179 		generic_handle_irq(irq_find_mapping(tb10x_gpio->domain, i));
180 
181 	return IRQ_HANDLED;
182 }
183 
184 static int tb10x_gpio_probe(struct platform_device *pdev)
185 {
186 	struct tb10x_gpio *tb10x_gpio;
187 	struct resource *mem;
188 	struct device_node *dn = pdev->dev.of_node;
189 	int ret = -EBUSY;
190 	u32 ngpio;
191 
192 	if (!dn)
193 		return -EINVAL;
194 
195 	if (of_property_read_u32(dn, "abilis,ngpio", &ngpio))
196 		return -EINVAL;
197 
198 	tb10x_gpio = devm_kzalloc(&pdev->dev, sizeof(*tb10x_gpio), GFP_KERNEL);
199 	if (tb10x_gpio == NULL)
200 		return -ENOMEM;
201 
202 	spin_lock_init(&tb10x_gpio->spinlock);
203 
204 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
205 	tb10x_gpio->base = devm_ioremap_resource(&pdev->dev, mem);
206 	if (IS_ERR(tb10x_gpio->base))
207 		return PTR_ERR(tb10x_gpio->base);
208 
209 	tb10x_gpio->gc.label		= of_node_full_name(dn);
210 	tb10x_gpio->gc.dev		= &pdev->dev;
211 	tb10x_gpio->gc.owner		= THIS_MODULE;
212 	tb10x_gpio->gc.direction_input	= tb10x_gpio_direction_in;
213 	tb10x_gpio->gc.get		= tb10x_gpio_get;
214 	tb10x_gpio->gc.direction_output	= tb10x_gpio_direction_out;
215 	tb10x_gpio->gc.set		= tb10x_gpio_set;
216 	tb10x_gpio->gc.request		= tb10x_gpio_request;
217 	tb10x_gpio->gc.free		= tb10x_gpio_free;
218 	tb10x_gpio->gc.base		= -1;
219 	tb10x_gpio->gc.ngpio		= ngpio;
220 	tb10x_gpio->gc.can_sleep	= false;
221 
222 
223 	ret = gpiochip_add(&tb10x_gpio->gc);
224 	if (ret < 0) {
225 		dev_err(&pdev->dev, "Could not add gpiochip.\n");
226 		goto fail_gpiochip_registration;
227 	}
228 
229 	platform_set_drvdata(pdev, tb10x_gpio);
230 
231 	if (of_find_property(dn, "interrupt-controller", NULL)) {
232 		struct irq_chip_generic *gc;
233 
234 		ret = platform_get_irq(pdev, 0);
235 		if (ret < 0) {
236 			dev_err(&pdev->dev, "No interrupt specified.\n");
237 			goto fail_get_irq;
238 		}
239 
240 		tb10x_gpio->gc.to_irq	= tb10x_gpio_to_irq;
241 		tb10x_gpio->irq		= ret;
242 
243 		ret = devm_request_irq(&pdev->dev, ret, tb10x_gpio_irq_cascade,
244 				IRQF_TRIGGER_NONE | IRQF_SHARED,
245 				dev_name(&pdev->dev), tb10x_gpio);
246 		if (ret != 0)
247 			goto fail_request_irq;
248 
249 		tb10x_gpio->domain = irq_domain_add_linear(dn,
250 						tb10x_gpio->gc.ngpio,
251 						&irq_generic_chip_ops, NULL);
252 		if (!tb10x_gpio->domain) {
253 			ret = -ENOMEM;
254 			goto fail_irq_domain;
255 		}
256 
257 		ret = irq_alloc_domain_generic_chips(tb10x_gpio->domain,
258 				tb10x_gpio->gc.ngpio, 1, tb10x_gpio->gc.label,
259 				handle_edge_irq, IRQ_NOREQUEST, IRQ_NOPROBE,
260 				IRQ_GC_INIT_MASK_CACHE);
261 		if (ret)
262 			goto fail_irq_domain;
263 
264 		gc = tb10x_gpio->domain->gc->gc[0];
265 		gc->reg_base                         = tb10x_gpio->base;
266 		gc->chip_types[0].type               = IRQ_TYPE_EDGE_BOTH;
267 		gc->chip_types[0].chip.irq_ack       = irq_gc_ack_set_bit;
268 		gc->chip_types[0].chip.irq_mask      = irq_gc_mask_clr_bit;
269 		gc->chip_types[0].chip.irq_unmask    = irq_gc_mask_set_bit;
270 		gc->chip_types[0].chip.irq_set_type  = tb10x_gpio_irq_set_type;
271 		gc->chip_types[0].regs.ack           = OFFSET_TO_REG_CHANGE;
272 		gc->chip_types[0].regs.mask          = OFFSET_TO_REG_INT_EN;
273 	}
274 
275 	return 0;
276 
277 fail_irq_domain:
278 fail_request_irq:
279 fail_get_irq:
280 	gpiochip_remove(&tb10x_gpio->gc);
281 fail_gpiochip_registration:
282 fail_ioremap:
283 	return ret;
284 }
285 
286 static int tb10x_gpio_remove(struct platform_device *pdev)
287 {
288 	struct tb10x_gpio *tb10x_gpio = platform_get_drvdata(pdev);
289 
290 	if (tb10x_gpio->gc.to_irq) {
291 		irq_remove_generic_chip(tb10x_gpio->domain->gc->gc[0],
292 					BIT(tb10x_gpio->gc.ngpio) - 1, 0, 0);
293 		kfree(tb10x_gpio->domain->gc);
294 		irq_domain_remove(tb10x_gpio->domain);
295 	}
296 	gpiochip_remove(&tb10x_gpio->gc);
297 
298 	return 0;
299 }
300 
301 static const struct of_device_id tb10x_gpio_dt_ids[] = {
302 	{ .compatible = "abilis,tb10x-gpio" },
303 	{ }
304 };
305 MODULE_DEVICE_TABLE(of, tb10x_gpio_dt_ids);
306 
307 static struct platform_driver tb10x_gpio_driver = {
308 	.probe		= tb10x_gpio_probe,
309 	.remove		= tb10x_gpio_remove,
310 	.driver = {
311 		.name	= "tb10x-gpio",
312 		.of_match_table = tb10x_gpio_dt_ids,
313 	}
314 };
315 
316 module_platform_driver(tb10x_gpio_driver);
317 MODULE_LICENSE("GPL");
318 MODULE_DESCRIPTION("tb10x gpio.");
319 MODULE_VERSION("0.0.1");
320