1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Intel Tangier GPIO functions 4 * 5 * Copyright (c) 2016, 2021, 2023 Intel Corporation. 6 * 7 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 8 * Pandith N <pandith.n@intel.com> 9 * Raag Jadav <raag.jadav@intel.com> 10 */ 11 12 #ifndef _GPIO_TANGIER_H_ 13 #define _GPIO_TANGIER_H_ 14 15 #include <linux/gpio/driver.h> 16 #include <linux/spinlock_types.h> 17 #include <linux/types.h> 18 19 struct device; 20 21 struct tng_gpio_context; 22 23 /* Elkhart Lake specific wake registers */ 24 #define GWMR_EHL 0x100 /* Wake mask */ 25 #define GWSR_EHL 0x118 /* Wake source */ 26 #define GSIR_EHL 0x130 /* Secure input */ 27 28 /* Merrifield specific wake registers */ 29 #define GWMR_MRFLD 0x400 /* Wake mask */ 30 #define GWSR_MRFLD 0x418 /* Wake source */ 31 #define GSIR_MRFLD 0xc00 /* Secure input */ 32 33 /** 34 * struct tng_wake_regs - Platform specific wake registers 35 * @gwmr: Wake mask 36 * @gwsr: Wake source 37 * @gsir: Secure input 38 */ 39 struct tng_wake_regs { 40 u32 gwmr; 41 u32 gwsr; 42 u32 gsir; 43 }; 44 45 /** 46 * struct tng_gpio_pinrange - Map pin numbers to gpio numbers 47 * @gpio_base: Starting GPIO number of this range 48 * @pin_base: Starting pin number of this range 49 * @npins: Number of pins in this range 50 */ 51 struct tng_gpio_pinrange { 52 unsigned int gpio_base; 53 unsigned int pin_base; 54 unsigned int npins; 55 }; 56 57 #define GPIO_PINRANGE(gstart, gend, pstart) \ 58 (struct tng_gpio_pinrange) { \ 59 .gpio_base = (gstart), \ 60 .pin_base = (pstart), \ 61 .npins = (gend) - (gstart) + 1, \ 62 } 63 64 /** 65 * struct tng_gpio_pin_info - Platform specific pinout information 66 * @pin_ranges: Pin to GPIO mapping 67 * @nranges: Number of pin ranges 68 * @name: Respective pinctrl device name 69 */ 70 struct tng_gpio_pin_info { 71 const struct tng_gpio_pinrange *pin_ranges; 72 unsigned int nranges; 73 const char *name; 74 }; 75 76 /** 77 * struct tng_gpio_info - Platform specific GPIO and IRQ information 78 * @base: GPIO base to start numbering with 79 * @ngpio: Amount of GPIOs supported by the controller 80 * @first: First IRQ to start numbering with 81 */ 82 struct tng_gpio_info { 83 int base; 84 u16 ngpio; 85 unsigned int first; 86 }; 87 88 /** 89 * struct tng_gpio - Platform specific private data 90 * @chip: Instance of the struct gpio_chip 91 * @reg_base: Base address of MMIO registers 92 * @irq: Interrupt for the GPIO device 93 * @lock: Synchronization lock to prevent I/O race conditions 94 * @dev: The GPIO device 95 * @ctx: Context to be saved during suspend-resume 96 * @wake_regs: Platform specific wake registers 97 * @pin_info: Platform specific pinout information 98 * @info: Platform specific GPIO and IRQ information 99 */ 100 struct tng_gpio { 101 struct gpio_chip chip; 102 void __iomem *reg_base; 103 int irq; 104 raw_spinlock_t lock; 105 struct device *dev; 106 struct tng_gpio_context *ctx; 107 struct tng_wake_regs wake_regs; 108 struct tng_gpio_pin_info pin_info; 109 struct tng_gpio_info info; 110 }; 111 112 int devm_tng_gpio_probe(struct device *dev, struct tng_gpio *gpio); 113 114 int tng_gpio_suspend(struct device *dev); 115 int tng_gpio_resume(struct device *dev); 116 117 #endif /* _GPIO_TANGIER_H_ */ 118