1d2c19e89SPandith N /* SPDX-License-Identifier: GPL-2.0-only */ 2d2c19e89SPandith N /* 3d2c19e89SPandith N * Intel Tangier GPIO functions 4d2c19e89SPandith N * 5d2c19e89SPandith N * Copyright (c) 2016, 2021, 2023 Intel Corporation. 6d2c19e89SPandith N * 7d2c19e89SPandith N * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 8d2c19e89SPandith N * Pandith N <pandith.n@intel.com> 9d2c19e89SPandith N * Raag Jadav <raag.jadav@intel.com> 10d2c19e89SPandith N */ 11d2c19e89SPandith N 12d2c19e89SPandith N #ifndef _GPIO_TANGIER_H_ 13d2c19e89SPandith N #define _GPIO_TANGIER_H_ 14d2c19e89SPandith N 15d2c19e89SPandith N #include <linux/gpio/driver.h> 16d2c19e89SPandith N #include <linux/spinlock_types.h> 17d2c19e89SPandith N #include <linux/types.h> 18d2c19e89SPandith N 19d2c19e89SPandith N struct device; 20d2c19e89SPandith N 21d2c19e89SPandith N struct tng_gpio_context; 22d2c19e89SPandith N 23*9409d8cfSPandith N /* Elkhart Lake specific wake registers */ 24*9409d8cfSPandith N #define GWMR_EHL 0x100 /* Wake mask */ 25*9409d8cfSPandith N #define GWSR_EHL 0x118 /* Wake source */ 26*9409d8cfSPandith N #define GSIR_EHL 0x130 /* Secure input */ 27*9409d8cfSPandith N 2834840be5SPandith N /* Merrifield specific wake registers */ 2934840be5SPandith N #define GWMR_MRFLD 0x400 /* Wake mask */ 3034840be5SPandith N #define GWSR_MRFLD 0x418 /* Wake source */ 3134840be5SPandith N #define GSIR_MRFLD 0xc00 /* Secure input */ 3234840be5SPandith N 33d2c19e89SPandith N /** 34d2c19e89SPandith N * struct tng_wake_regs - Platform specific wake registers 35d2c19e89SPandith N * @gwmr: Wake mask 36d2c19e89SPandith N * @gwsr: Wake source 37d2c19e89SPandith N * @gsir: Secure input 38d2c19e89SPandith N */ 39d2c19e89SPandith N struct tng_wake_regs { 40d2c19e89SPandith N u32 gwmr; 41d2c19e89SPandith N u32 gwsr; 42d2c19e89SPandith N u32 gsir; 43d2c19e89SPandith N }; 44d2c19e89SPandith N 45d2c19e89SPandith N /** 46d2c19e89SPandith N * struct tng_gpio_pinrange - Map pin numbers to gpio numbers 47d2c19e89SPandith N * @gpio_base: Starting GPIO number of this range 48d2c19e89SPandith N * @pin_base: Starting pin number of this range 49d2c19e89SPandith N * @npins: Number of pins in this range 50d2c19e89SPandith N */ 51d2c19e89SPandith N struct tng_gpio_pinrange { 52d2c19e89SPandith N unsigned int gpio_base; 53d2c19e89SPandith N unsigned int pin_base; 54d2c19e89SPandith N unsigned int npins; 55d2c19e89SPandith N }; 56d2c19e89SPandith N 57d2c19e89SPandith N #define GPIO_PINRANGE(gstart, gend, pstart) \ 58d2c19e89SPandith N (struct tng_gpio_pinrange) { \ 59d2c19e89SPandith N .gpio_base = (gstart), \ 60d2c19e89SPandith N .pin_base = (pstart), \ 61d2c19e89SPandith N .npins = (gend) - (gstart) + 1, \ 62d2c19e89SPandith N } 63d2c19e89SPandith N 64d2c19e89SPandith N /** 65d2c19e89SPandith N * struct tng_gpio_pin_info - Platform specific pinout information 66d2c19e89SPandith N * @pin_ranges: Pin to GPIO mapping 67d2c19e89SPandith N * @nranges: Number of pin ranges 68d2c19e89SPandith N * @name: Respective pinctrl device name 69d2c19e89SPandith N */ 70d2c19e89SPandith N struct tng_gpio_pin_info { 71d2c19e89SPandith N const struct tng_gpio_pinrange *pin_ranges; 72d2c19e89SPandith N unsigned int nranges; 73d2c19e89SPandith N const char *name; 74d2c19e89SPandith N }; 75d2c19e89SPandith N 76d2c19e89SPandith N /** 77d2c19e89SPandith N * struct tng_gpio_info - Platform specific GPIO and IRQ information 78d2c19e89SPandith N * @base: GPIO base to start numbering with 79d2c19e89SPandith N * @ngpio: Amount of GPIOs supported by the controller 80d2c19e89SPandith N * @first: First IRQ to start numbering with 81d2c19e89SPandith N */ 82d2c19e89SPandith N struct tng_gpio_info { 83d2c19e89SPandith N int base; 84d2c19e89SPandith N u16 ngpio; 85d2c19e89SPandith N unsigned int first; 86d2c19e89SPandith N }; 87d2c19e89SPandith N 88d2c19e89SPandith N /** 89d2c19e89SPandith N * struct tng_gpio - Platform specific private data 90d2c19e89SPandith N * @chip: Instance of the struct gpio_chip 91d2c19e89SPandith N * @reg_base: Base address of MMIO registers 92d2c19e89SPandith N * @irq: Interrupt for the GPIO device 93d2c19e89SPandith N * @lock: Synchronization lock to prevent I/O race conditions 94d2c19e89SPandith N * @dev: The GPIO device 95d2c19e89SPandith N * @ctx: Context to be saved during suspend-resume 96d2c19e89SPandith N * @wake_regs: Platform specific wake registers 97d2c19e89SPandith N * @pin_info: Platform specific pinout information 98d2c19e89SPandith N * @info: Platform specific GPIO and IRQ information 99d2c19e89SPandith N */ 100d2c19e89SPandith N struct tng_gpio { 101d2c19e89SPandith N struct gpio_chip chip; 102d2c19e89SPandith N void __iomem *reg_base; 103d2c19e89SPandith N int irq; 104d2c19e89SPandith N raw_spinlock_t lock; 105d2c19e89SPandith N struct device *dev; 106d2c19e89SPandith N struct tng_gpio_context *ctx; 107d2c19e89SPandith N struct tng_wake_regs wake_regs; 108d2c19e89SPandith N struct tng_gpio_pin_info pin_info; 109d2c19e89SPandith N struct tng_gpio_info info; 110d2c19e89SPandith N }; 111d2c19e89SPandith N 112d2c19e89SPandith N int devm_tng_gpio_probe(struct device *dev, struct tng_gpio *gpio); 113d2c19e89SPandith N 114d2c19e89SPandith N int tng_gpio_suspend(struct device *dev); 115d2c19e89SPandith N int tng_gpio_resume(struct device *dev); 116d2c19e89SPandith N 117d2c19e89SPandith N #endif /* _GPIO_TANGIER_H_ */ 118