1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Intel Tangier GPIO driver 4 * 5 * Copyright (c) 2016, 2021, 2023 Intel Corporation. 6 * 7 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 8 * Pandith N <pandith.n@intel.com> 9 * Raag Jadav <raag.jadav@intel.com> 10 */ 11 12 #include <linux/bitops.h> 13 #include <linux/device.h> 14 #include <linux/errno.h> 15 #include <linux/export.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/irq.h> 19 #include <linux/math.h> 20 #include <linux/module.h> 21 #include <linux/pinctrl/pinconf-generic.h> 22 #include <linux/spinlock.h> 23 #include <linux/string_helpers.h> 24 #include <linux/types.h> 25 26 #include <linux/gpio/driver.h> 27 28 #include "gpio-tangier.h" 29 30 #define GCCR 0x000 /* Controller configuration */ 31 #define GPLR 0x004 /* Pin level r/o */ 32 #define GPDR 0x01c /* Pin direction */ 33 #define GPSR 0x034 /* Pin set w/o */ 34 #define GPCR 0x04c /* Pin clear w/o */ 35 #define GRER 0x064 /* Rising edge detect */ 36 #define GFER 0x07c /* Falling edge detect */ 37 #define GFBR 0x094 /* Glitch filter bypass */ 38 #define GIMR 0x0ac /* Interrupt mask */ 39 #define GISR 0x0c4 /* Interrupt source */ 40 #define GITR 0x300 /* Input type */ 41 #define GLPR 0x318 /* Level input polarity */ 42 43 /** 44 * struct tng_gpio_context - Context to be saved during suspend-resume 45 * @level: Pin level 46 * @gpdr: Pin direction 47 * @grer: Rising edge detect enable 48 * @gfer: Falling edge detect enable 49 * @gimr: Interrupt mask 50 * @gwmr: Wake mask 51 */ 52 struct tng_gpio_context { 53 u32 level; 54 u32 gpdr; 55 u32 grer; 56 u32 gfer; 57 u32 gimr; 58 u32 gwmr; 59 }; 60 61 static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned int offset, 62 unsigned int reg) 63 { 64 struct tng_gpio *priv = gpiochip_get_data(chip); 65 u8 reg_offset = offset / 32; 66 67 return priv->reg_base + reg + reg_offset * 4; 68 } 69 70 static void __iomem *gpio_reg_and_bit(struct gpio_chip *chip, unsigned int offset, 71 unsigned int reg, u8 *bit) 72 { 73 struct tng_gpio *priv = gpiochip_get_data(chip); 74 u8 reg_offset = offset / 32; 75 u8 shift = offset % 32; 76 77 *bit = shift; 78 return priv->reg_base + reg + reg_offset * 4; 79 } 80 81 static int tng_gpio_get(struct gpio_chip *chip, unsigned int offset) 82 { 83 void __iomem *gplr; 84 u8 shift; 85 86 gplr = gpio_reg_and_bit(chip, offset, GPLR, &shift); 87 88 return !!(readl(gplr) & BIT(shift)); 89 } 90 91 static void tng_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 92 { 93 struct tng_gpio *priv = gpiochip_get_data(chip); 94 unsigned long flags; 95 void __iomem *reg; 96 u8 shift; 97 98 reg = gpio_reg_and_bit(chip, offset, value ? GPSR : GPCR, &shift); 99 100 raw_spin_lock_irqsave(&priv->lock, flags); 101 102 writel(BIT(shift), reg); 103 104 raw_spin_unlock_irqrestore(&priv->lock, flags); 105 } 106 107 static int tng_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 108 { 109 struct tng_gpio *priv = gpiochip_get_data(chip); 110 unsigned long flags; 111 void __iomem *gpdr; 112 u32 value; 113 u8 shift; 114 115 gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift); 116 117 raw_spin_lock_irqsave(&priv->lock, flags); 118 119 value = readl(gpdr); 120 value &= ~BIT(shift); 121 writel(value, gpdr); 122 123 raw_spin_unlock_irqrestore(&priv->lock, flags); 124 125 return 0; 126 } 127 128 static int tng_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, 129 int value) 130 { 131 struct tng_gpio *priv = gpiochip_get_data(chip); 132 unsigned long flags; 133 void __iomem *gpdr; 134 u8 shift; 135 136 gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift); 137 tng_gpio_set(chip, offset, value); 138 139 raw_spin_lock_irqsave(&priv->lock, flags); 140 141 value = readl(gpdr); 142 value |= BIT(shift); 143 writel(value, gpdr); 144 145 raw_spin_unlock_irqrestore(&priv->lock, flags); 146 147 return 0; 148 } 149 150 static int tng_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 151 { 152 void __iomem *gpdr; 153 u8 shift; 154 155 gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift); 156 157 if (readl(gpdr) & BIT(shift)) 158 return GPIO_LINE_DIRECTION_OUT; 159 160 return GPIO_LINE_DIRECTION_IN; 161 } 162 163 static int tng_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset, 164 unsigned int debounce) 165 { 166 struct tng_gpio *priv = gpiochip_get_data(chip); 167 unsigned long flags; 168 void __iomem *gfbr; 169 u32 value; 170 u8 shift; 171 172 gfbr = gpio_reg_and_bit(chip, offset, GFBR, &shift); 173 174 raw_spin_lock_irqsave(&priv->lock, flags); 175 176 value = readl(gfbr); 177 if (debounce) 178 value &= ~BIT(shift); 179 else 180 value |= BIT(shift); 181 writel(value, gfbr); 182 183 raw_spin_unlock_irqrestore(&priv->lock, flags); 184 185 return 0; 186 } 187 188 static int tng_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 189 unsigned long config) 190 { 191 u32 debounce; 192 193 switch (pinconf_to_config_param(config)) { 194 case PIN_CONFIG_BIAS_DISABLE: 195 case PIN_CONFIG_BIAS_PULL_UP: 196 case PIN_CONFIG_BIAS_PULL_DOWN: 197 return gpiochip_generic_config(chip, offset, config); 198 case PIN_CONFIG_INPUT_DEBOUNCE: 199 debounce = pinconf_to_config_argument(config); 200 return tng_gpio_set_debounce(chip, offset, debounce); 201 default: 202 return -ENOTSUPP; 203 } 204 } 205 206 static void tng_irq_ack(struct irq_data *d) 207 { 208 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 209 struct tng_gpio *priv = gpiochip_get_data(gc); 210 irq_hw_number_t gpio = irqd_to_hwirq(d); 211 unsigned long flags; 212 void __iomem *gisr; 213 u8 shift; 214 215 gisr = gpio_reg_and_bit(&priv->chip, gpio, GISR, &shift); 216 217 raw_spin_lock_irqsave(&priv->lock, flags); 218 writel(BIT(shift), gisr); 219 raw_spin_unlock_irqrestore(&priv->lock, flags); 220 } 221 222 static void tng_irq_unmask_mask(struct tng_gpio *priv, u32 gpio, bool unmask) 223 { 224 unsigned long flags; 225 void __iomem *gimr; 226 u32 value; 227 u8 shift; 228 229 gimr = gpio_reg_and_bit(&priv->chip, gpio, GIMR, &shift); 230 231 raw_spin_lock_irqsave(&priv->lock, flags); 232 233 value = readl(gimr); 234 if (unmask) 235 value |= BIT(shift); 236 else 237 value &= ~BIT(shift); 238 writel(value, gimr); 239 240 raw_spin_unlock_irqrestore(&priv->lock, flags); 241 } 242 243 static void tng_irq_mask(struct irq_data *d) 244 { 245 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 246 struct tng_gpio *priv = gpiochip_get_data(gc); 247 irq_hw_number_t gpio = irqd_to_hwirq(d); 248 249 tng_irq_unmask_mask(priv, gpio, false); 250 gpiochip_disable_irq(&priv->chip, gpio); 251 } 252 253 static void tng_irq_unmask(struct irq_data *d) 254 { 255 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 256 struct tng_gpio *priv = gpiochip_get_data(gc); 257 irq_hw_number_t gpio = irqd_to_hwirq(d); 258 259 gpiochip_enable_irq(&priv->chip, gpio); 260 tng_irq_unmask_mask(priv, gpio, true); 261 } 262 263 static int tng_irq_set_type(struct irq_data *d, unsigned int type) 264 { 265 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 266 struct tng_gpio *priv = gpiochip_get_data(gc); 267 irq_hw_number_t gpio = irqd_to_hwirq(d); 268 void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER); 269 void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER); 270 void __iomem *gitr = gpio_reg(&priv->chip, gpio, GITR); 271 void __iomem *glpr = gpio_reg(&priv->chip, gpio, GLPR); 272 u8 shift = gpio % 32; 273 unsigned long flags; 274 u32 value; 275 276 raw_spin_lock_irqsave(&priv->lock, flags); 277 278 value = readl(grer); 279 if (type & IRQ_TYPE_EDGE_RISING) 280 value |= BIT(shift); 281 else 282 value &= ~BIT(shift); 283 writel(value, grer); 284 285 value = readl(gfer); 286 if (type & IRQ_TYPE_EDGE_FALLING) 287 value |= BIT(shift); 288 else 289 value &= ~BIT(shift); 290 writel(value, gfer); 291 292 /* 293 * To prevent glitches from triggering an unintended level interrupt, 294 * configure GLPR register first and then configure GITR. 295 */ 296 value = readl(glpr); 297 if (type & IRQ_TYPE_LEVEL_LOW) 298 value |= BIT(shift); 299 else 300 value &= ~BIT(shift); 301 writel(value, glpr); 302 303 if (type & IRQ_TYPE_LEVEL_MASK) { 304 value = readl(gitr); 305 value |= BIT(shift); 306 writel(value, gitr); 307 308 irq_set_handler_locked(d, handle_level_irq); 309 } else if (type & IRQ_TYPE_EDGE_BOTH) { 310 value = readl(gitr); 311 value &= ~BIT(shift); 312 writel(value, gitr); 313 314 irq_set_handler_locked(d, handle_edge_irq); 315 } 316 317 raw_spin_unlock_irqrestore(&priv->lock, flags); 318 319 return 0; 320 } 321 322 static int tng_irq_set_wake(struct irq_data *d, unsigned int on) 323 { 324 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 325 struct tng_gpio *priv = gpiochip_get_data(gc); 326 irq_hw_number_t gpio = irqd_to_hwirq(d); 327 void __iomem *gwmr = gpio_reg(&priv->chip, gpio, priv->wake_regs.gwmr); 328 void __iomem *gwsr = gpio_reg(&priv->chip, gpio, priv->wake_regs.gwsr); 329 u8 shift = gpio % 32; 330 unsigned long flags; 331 u32 value; 332 333 raw_spin_lock_irqsave(&priv->lock, flags); 334 335 /* Clear the existing wake status */ 336 writel(BIT(shift), gwsr); 337 338 value = readl(gwmr); 339 if (on) 340 value |= BIT(shift); 341 else 342 value &= ~BIT(shift); 343 writel(value, gwmr); 344 345 raw_spin_unlock_irqrestore(&priv->lock, flags); 346 347 dev_dbg(priv->dev, "%s wake for gpio %lu\n", str_enable_disable(on), gpio); 348 return 0; 349 } 350 351 static const struct irq_chip tng_irqchip = { 352 .name = "gpio-tangier", 353 .irq_ack = tng_irq_ack, 354 .irq_mask = tng_irq_mask, 355 .irq_unmask = tng_irq_unmask, 356 .irq_set_type = tng_irq_set_type, 357 .irq_set_wake = tng_irq_set_wake, 358 .flags = IRQCHIP_IMMUTABLE, 359 GPIOCHIP_IRQ_RESOURCE_HELPERS, 360 }; 361 362 static void tng_irq_handler(struct irq_desc *desc) 363 { 364 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 365 struct tng_gpio *priv = gpiochip_get_data(gc); 366 struct irq_chip *irqchip = irq_desc_get_chip(desc); 367 unsigned long base, gpio; 368 369 chained_irq_enter(irqchip, desc); 370 371 /* Check GPIO controller to check which pin triggered the interrupt */ 372 for (base = 0; base < priv->chip.ngpio; base += 32) { 373 void __iomem *gisr = gpio_reg(&priv->chip, base, GISR); 374 void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR); 375 unsigned long pending, enabled; 376 377 pending = readl(gisr); 378 enabled = readl(gimr); 379 380 /* Only interrupts that are enabled */ 381 pending &= enabled; 382 383 for_each_set_bit(gpio, &pending, 32) 384 generic_handle_domain_irq(gc->irq.domain, base + gpio); 385 } 386 387 chained_irq_exit(irqchip, desc); 388 } 389 390 static int tng_irq_init_hw(struct gpio_chip *chip) 391 { 392 struct tng_gpio *priv = gpiochip_get_data(chip); 393 void __iomem *reg; 394 unsigned int base; 395 396 for (base = 0; base < priv->chip.ngpio; base += 32) { 397 /* Clear the rising-edge detect register */ 398 reg = gpio_reg(&priv->chip, base, GRER); 399 writel(0, reg); 400 401 /* Clear the falling-edge detect register */ 402 reg = gpio_reg(&priv->chip, base, GFER); 403 writel(0, reg); 404 } 405 406 return 0; 407 } 408 409 static int tng_gpio_add_pin_ranges(struct gpio_chip *chip) 410 { 411 struct tng_gpio *priv = gpiochip_get_data(chip); 412 const struct tng_gpio_pinrange *range; 413 unsigned int i; 414 int ret; 415 416 for (i = 0; i < priv->pin_info.nranges; i++) { 417 range = &priv->pin_info.pin_ranges[i]; 418 ret = gpiochip_add_pin_range(&priv->chip, 419 priv->pin_info.name, 420 range->gpio_base, 421 range->pin_base, 422 range->npins); 423 if (ret) { 424 dev_err(priv->dev, "failed to add GPIO pin range\n"); 425 return ret; 426 } 427 } 428 429 return 0; 430 } 431 432 int devm_tng_gpio_probe(struct device *dev, struct tng_gpio *gpio) 433 { 434 const struct tng_gpio_info *info = &gpio->info; 435 size_t nctx = DIV_ROUND_UP(info->ngpio, 32); 436 struct gpio_irq_chip *girq; 437 int ret; 438 439 gpio->ctx = devm_kcalloc(dev, nctx, sizeof(*gpio->ctx), GFP_KERNEL); 440 if (!gpio->ctx) 441 return -ENOMEM; 442 443 gpio->chip.label = dev_name(dev); 444 gpio->chip.parent = dev; 445 gpio->chip.request = gpiochip_generic_request; 446 gpio->chip.free = gpiochip_generic_free; 447 gpio->chip.direction_input = tng_gpio_direction_input; 448 gpio->chip.direction_output = tng_gpio_direction_output; 449 gpio->chip.get = tng_gpio_get; 450 gpio->chip.set = tng_gpio_set; 451 gpio->chip.get_direction = tng_gpio_get_direction; 452 gpio->chip.set_config = tng_gpio_set_config; 453 gpio->chip.base = info->base; 454 gpio->chip.ngpio = info->ngpio; 455 gpio->chip.can_sleep = false; 456 gpio->chip.add_pin_ranges = tng_gpio_add_pin_ranges; 457 458 raw_spin_lock_init(&gpio->lock); 459 460 girq = &gpio->chip.irq; 461 gpio_irq_chip_set_chip(girq, &tng_irqchip); 462 girq->init_hw = tng_irq_init_hw; 463 girq->parent_handler = tng_irq_handler; 464 girq->num_parents = 1; 465 girq->parents = devm_kcalloc(dev, girq->num_parents, 466 sizeof(*girq->parents), GFP_KERNEL); 467 if (!girq->parents) 468 return -ENOMEM; 469 470 girq->parents[0] = gpio->irq; 471 girq->first = info->first; 472 girq->default_type = IRQ_TYPE_NONE; 473 girq->handler = handle_bad_irq; 474 475 ret = devm_gpiochip_add_data(dev, &gpio->chip, gpio); 476 if (ret) 477 return dev_err_probe(dev, ret, "gpiochip_add error\n"); 478 479 return 0; 480 } 481 EXPORT_SYMBOL_NS_GPL(devm_tng_gpio_probe, GPIO_TANGIER); 482 483 int tng_gpio_suspend(struct device *dev) 484 { 485 struct tng_gpio *priv = dev_get_drvdata(dev); 486 struct tng_gpio_context *ctx = priv->ctx; 487 unsigned long flags; 488 unsigned int base; 489 490 raw_spin_lock_irqsave(&priv->lock, flags); 491 492 for (base = 0; base < priv->chip.ngpio; base += 32, ctx++) { 493 /* GPLR is RO, values read will be restored using GPSR */ 494 ctx->level = readl(gpio_reg(&priv->chip, base, GPLR)); 495 496 ctx->gpdr = readl(gpio_reg(&priv->chip, base, GPDR)); 497 ctx->grer = readl(gpio_reg(&priv->chip, base, GRER)); 498 ctx->gfer = readl(gpio_reg(&priv->chip, base, GFER)); 499 ctx->gimr = readl(gpio_reg(&priv->chip, base, GIMR)); 500 501 ctx->gwmr = readl(gpio_reg(&priv->chip, base, priv->wake_regs.gwmr)); 502 } 503 504 raw_spin_unlock_irqrestore(&priv->lock, flags); 505 506 return 0; 507 } 508 EXPORT_SYMBOL_NS_GPL(tng_gpio_suspend, GPIO_TANGIER); 509 510 int tng_gpio_resume(struct device *dev) 511 { 512 struct tng_gpio *priv = dev_get_drvdata(dev); 513 struct tng_gpio_context *ctx = priv->ctx; 514 unsigned long flags; 515 unsigned int base; 516 517 raw_spin_lock_irqsave(&priv->lock, flags); 518 519 for (base = 0; base < priv->chip.ngpio; base += 32, ctx++) { 520 /* GPLR is RO, values read will be restored using GPSR */ 521 writel(ctx->level, gpio_reg(&priv->chip, base, GPSR)); 522 523 writel(ctx->gpdr, gpio_reg(&priv->chip, base, GPDR)); 524 writel(ctx->grer, gpio_reg(&priv->chip, base, GRER)); 525 writel(ctx->gfer, gpio_reg(&priv->chip, base, GFER)); 526 writel(ctx->gimr, gpio_reg(&priv->chip, base, GIMR)); 527 528 writel(ctx->gwmr, gpio_reg(&priv->chip, base, priv->wake_regs.gwmr)); 529 } 530 531 raw_spin_unlock_irqrestore(&priv->lock, flags); 532 533 return 0; 534 } 535 EXPORT_SYMBOL_NS_GPL(tng_gpio_resume, GPIO_TANGIER); 536 537 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); 538 MODULE_AUTHOR("Pandith N <pandith.n@intel.com>"); 539 MODULE_AUTHOR("Raag Jadav <raag.jadav@intel.com>"); 540 MODULE_DESCRIPTION("Intel Tangier GPIO driver"); 541 MODULE_LICENSE("GPL"); 542