xref: /openbmc/linux/drivers/gpio/gpio-tangier.c (revision 3d40aed8) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Intel Tangier GPIO driver
4  *
5  * Copyright (c) 2016, 2021, 2023 Intel Corporation.
6  *
7  * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
8  *          Pandith N <pandith.n@intel.com>
9  *          Raag Jadav <raag.jadav@intel.com>
10  */
11 
12 #include <linux/bitops.h>
13 #include <linux/device.h>
14 #include <linux/errno.h>
15 #include <linux/export.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/irq.h>
19 #include <linux/math.h>
20 #include <linux/module.h>
21 #include <linux/pinctrl/pinconf-generic.h>
22 #include <linux/spinlock.h>
23 #include <linux/string_helpers.h>
24 #include <linux/types.h>
25 
26 #include <linux/gpio/driver.h>
27 
28 #include "gpio-tangier.h"
29 
30 #define GCCR		0x000	/* Controller configuration */
31 #define GPLR		0x004	/* Pin level r/o */
32 #define GPDR		0x01c	/* Pin direction */
33 #define GPSR		0x034	/* Pin set w/o */
34 #define GPCR		0x04c	/* Pin clear w/o */
35 #define GRER		0x064	/* Rising edge detect */
36 #define GFER		0x07c	/* Falling edge detect */
37 #define GFBR		0x094	/* Glitch filter bypass */
38 #define GIMR		0x0ac	/* Interrupt mask */
39 #define GISR		0x0c4	/* Interrupt source */
40 #define GITR		0x300	/* Input type */
41 #define GLPR		0x318	/* Level input polarity */
42 
43 /**
44  * struct tng_gpio_context - Context to be saved during suspend-resume
45  * @level: Pin level
46  * @gpdr: Pin direction
47  * @grer: Rising edge detect enable
48  * @gfer: Falling edge detect enable
49  * @gimr: Interrupt mask
50  * @gwmr: Wake mask
51  */
52 struct tng_gpio_context {
53 	u32 level;
54 	u32 gpdr;
55 	u32 grer;
56 	u32 gfer;
57 	u32 gimr;
58 	u32 gwmr;
59 };
60 
61 static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned int offset,
62 			      unsigned int reg)
63 {
64 	struct tng_gpio *priv = gpiochip_get_data(chip);
65 	u8 reg_offset = offset / 32;
66 
67 	return priv->reg_base + reg + reg_offset * 4;
68 }
69 
70 static void __iomem *gpio_reg_and_bit(struct gpio_chip *chip, unsigned int offset,
71 				      unsigned int reg, u8 *bit)
72 {
73 	struct tng_gpio *priv = gpiochip_get_data(chip);
74 	u8 reg_offset = offset / 32;
75 	u8 shift = offset % 32;
76 
77 	*bit = shift;
78 	return priv->reg_base + reg + reg_offset * 4;
79 }
80 
81 static int tng_gpio_get(struct gpio_chip *chip, unsigned int offset)
82 {
83 	void __iomem *gplr;
84 	u8 shift;
85 
86 	gplr = gpio_reg_and_bit(chip, offset, GPLR, &shift);
87 
88 	return !!(readl(gplr) & BIT(shift));
89 }
90 
91 static void tng_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
92 {
93 	struct tng_gpio *priv = gpiochip_get_data(chip);
94 	unsigned long flags;
95 	void __iomem *reg;
96 	u8 shift;
97 
98 	reg = gpio_reg_and_bit(chip, offset, value ? GPSR : GPCR, &shift);
99 
100 	raw_spin_lock_irqsave(&priv->lock, flags);
101 
102 	writel(BIT(shift), reg);
103 
104 	raw_spin_unlock_irqrestore(&priv->lock, flags);
105 }
106 
107 static int tng_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
108 {
109 	struct tng_gpio *priv = gpiochip_get_data(chip);
110 	unsigned long flags;
111 	void __iomem *gpdr;
112 	u32 value;
113 	u8 shift;
114 
115 	gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift);
116 
117 	raw_spin_lock_irqsave(&priv->lock, flags);
118 
119 	value = readl(gpdr);
120 	value &= ~BIT(shift);
121 	writel(value, gpdr);
122 
123 	raw_spin_unlock_irqrestore(&priv->lock, flags);
124 
125 	return 0;
126 }
127 
128 static int tng_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
129 				     int value)
130 {
131 	struct tng_gpio *priv = gpiochip_get_data(chip);
132 	unsigned long flags;
133 	void __iomem *gpdr;
134 	u8 shift;
135 
136 	gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift);
137 	tng_gpio_set(chip, offset, value);
138 
139 	raw_spin_lock_irqsave(&priv->lock, flags);
140 
141 	value = readl(gpdr);
142 	value |= BIT(shift);
143 	writel(value, gpdr);
144 
145 	raw_spin_unlock_irqrestore(&priv->lock, flags);
146 
147 	return 0;
148 }
149 
150 static int tng_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
151 {
152 	void __iomem *gpdr;
153 	u8 shift;
154 
155 	gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift);
156 
157 	if (readl(gpdr) & BIT(shift))
158 		return GPIO_LINE_DIRECTION_OUT;
159 
160 	return GPIO_LINE_DIRECTION_IN;
161 }
162 
163 static int tng_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
164 				 unsigned int debounce)
165 {
166 	struct tng_gpio *priv = gpiochip_get_data(chip);
167 	unsigned long flags;
168 	void __iomem *gfbr;
169 	u32 value;
170 	u8 shift;
171 
172 	gfbr = gpio_reg_and_bit(chip, offset, GFBR, &shift);
173 
174 	raw_spin_lock_irqsave(&priv->lock, flags);
175 
176 	value = readl(gfbr);
177 	if (debounce)
178 		value &= ~BIT(shift);
179 	else
180 		value |= BIT(shift);
181 	writel(value, gfbr);
182 
183 	raw_spin_unlock_irqrestore(&priv->lock, flags);
184 
185 	return 0;
186 }
187 
188 static int tng_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
189 			       unsigned long config)
190 {
191 	u32 debounce;
192 
193 	switch (pinconf_to_config_param(config)) {
194 	case PIN_CONFIG_BIAS_DISABLE:
195 	case PIN_CONFIG_BIAS_PULL_UP:
196 	case PIN_CONFIG_BIAS_PULL_DOWN:
197 		return gpiochip_generic_config(chip, offset, config);
198 	case PIN_CONFIG_INPUT_DEBOUNCE:
199 		debounce = pinconf_to_config_argument(config);
200 		return tng_gpio_set_debounce(chip, offset, debounce);
201 	default:
202 		return -ENOTSUPP;
203 	}
204 }
205 
206 static void tng_irq_ack(struct irq_data *d)
207 {
208 	struct tng_gpio *priv = irq_data_get_irq_chip_data(d);
209 	irq_hw_number_t gpio = irqd_to_hwirq(d);
210 	unsigned long flags;
211 	void __iomem *gisr;
212 	u8 shift;
213 
214 	gisr = gpio_reg_and_bit(&priv->chip, gpio, GISR, &shift);
215 
216 	raw_spin_lock_irqsave(&priv->lock, flags);
217 	writel(BIT(shift), gisr);
218 	raw_spin_unlock_irqrestore(&priv->lock, flags);
219 }
220 
221 static void tng_irq_unmask_mask(struct tng_gpio *priv, u32 gpio, bool unmask)
222 {
223 	unsigned long flags;
224 	void __iomem *gimr;
225 	u32 value;
226 	u8 shift;
227 
228 	gimr = gpio_reg_and_bit(&priv->chip, gpio, GIMR, &shift);
229 
230 	raw_spin_lock_irqsave(&priv->lock, flags);
231 
232 	value = readl(gimr);
233 	if (unmask)
234 		value |= BIT(shift);
235 	else
236 		value &= ~BIT(shift);
237 	writel(value, gimr);
238 
239 	raw_spin_unlock_irqrestore(&priv->lock, flags);
240 }
241 
242 static void tng_irq_mask(struct irq_data *d)
243 {
244 	struct tng_gpio *priv = irq_data_get_irq_chip_data(d);
245 	irq_hw_number_t gpio = irqd_to_hwirq(d);
246 
247 	tng_irq_unmask_mask(priv, gpio, false);
248 	gpiochip_disable_irq(&priv->chip, gpio);
249 }
250 
251 static void tng_irq_unmask(struct irq_data *d)
252 {
253 	struct tng_gpio *priv = irq_data_get_irq_chip_data(d);
254 	irq_hw_number_t gpio = irqd_to_hwirq(d);
255 
256 	gpiochip_enable_irq(&priv->chip, gpio);
257 	tng_irq_unmask_mask(priv, gpio, true);
258 }
259 
260 static int tng_irq_set_type(struct irq_data *d, unsigned int type)
261 {
262 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
263 	struct tng_gpio *priv = gpiochip_get_data(gc);
264 	irq_hw_number_t gpio = irqd_to_hwirq(d);
265 	void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
266 	void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
267 	void __iomem *gitr = gpio_reg(&priv->chip, gpio, GITR);
268 	void __iomem *glpr = gpio_reg(&priv->chip, gpio, GLPR);
269 	u8 shift = gpio % 32;
270 	unsigned long flags;
271 	u32 value;
272 
273 	raw_spin_lock_irqsave(&priv->lock, flags);
274 
275 	value = readl(grer);
276 	if (type & IRQ_TYPE_EDGE_RISING)
277 		value |= BIT(shift);
278 	else
279 		value &= ~BIT(shift);
280 	writel(value, grer);
281 
282 	value = readl(gfer);
283 	if (type & IRQ_TYPE_EDGE_FALLING)
284 		value |= BIT(shift);
285 	else
286 		value &= ~BIT(shift);
287 	writel(value, gfer);
288 
289 	/*
290 	 * To prevent glitches from triggering an unintended level interrupt,
291 	 * configure GLPR register first and then configure GITR.
292 	 */
293 	value = readl(glpr);
294 	if (type & IRQ_TYPE_LEVEL_LOW)
295 		value |= BIT(shift);
296 	else
297 		value &= ~BIT(shift);
298 	writel(value, glpr);
299 
300 	if (type & IRQ_TYPE_LEVEL_MASK) {
301 		value = readl(gitr);
302 		value |= BIT(shift);
303 		writel(value, gitr);
304 
305 		irq_set_handler_locked(d, handle_level_irq);
306 	} else if (type & IRQ_TYPE_EDGE_BOTH) {
307 		value = readl(gitr);
308 		value &= ~BIT(shift);
309 		writel(value, gitr);
310 
311 		irq_set_handler_locked(d, handle_edge_irq);
312 	}
313 
314 	raw_spin_unlock_irqrestore(&priv->lock, flags);
315 
316 	return 0;
317 }
318 
319 static int tng_irq_set_wake(struct irq_data *d, unsigned int on)
320 {
321 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
322 	struct tng_gpio *priv = gpiochip_get_data(gc);
323 	irq_hw_number_t gpio = irqd_to_hwirq(d);
324 	void __iomem *gwmr = gpio_reg(&priv->chip, gpio, priv->wake_regs.gwmr);
325 	void __iomem *gwsr = gpio_reg(&priv->chip, gpio, priv->wake_regs.gwsr);
326 	u8 shift = gpio % 32;
327 	unsigned long flags;
328 	u32 value;
329 
330 	raw_spin_lock_irqsave(&priv->lock, flags);
331 
332 	/* Clear the existing wake status */
333 	writel(BIT(shift), gwsr);
334 
335 	value = readl(gwmr);
336 	if (on)
337 		value |= BIT(shift);
338 	else
339 		value &= ~BIT(shift);
340 	writel(value, gwmr);
341 
342 	raw_spin_unlock_irqrestore(&priv->lock, flags);
343 
344 	dev_dbg(priv->dev, "%s wake for gpio %lu\n", str_enable_disable(on), gpio);
345 	return 0;
346 }
347 
348 static const struct irq_chip tng_irqchip = {
349 	.name		= "gpio-tangier",
350 	.irq_ack	= tng_irq_ack,
351 	.irq_mask	= tng_irq_mask,
352 	.irq_unmask	= tng_irq_unmask,
353 	.irq_set_type	= tng_irq_set_type,
354 	.irq_set_wake	= tng_irq_set_wake,
355 	.flags          = IRQCHIP_IMMUTABLE,
356 	GPIOCHIP_IRQ_RESOURCE_HELPERS,
357 };
358 
359 static void tng_irq_handler(struct irq_desc *desc)
360 {
361 	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
362 	struct tng_gpio *priv = gpiochip_get_data(gc);
363 	struct irq_chip *irqchip = irq_desc_get_chip(desc);
364 	unsigned long base, gpio;
365 
366 	chained_irq_enter(irqchip, desc);
367 
368 	/* Check GPIO controller to check which pin triggered the interrupt */
369 	for (base = 0; base < priv->chip.ngpio; base += 32) {
370 		void __iomem *gisr = gpio_reg(&priv->chip, base, GISR);
371 		void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR);
372 		unsigned long pending, enabled;
373 
374 		pending = readl(gisr);
375 		enabled = readl(gimr);
376 
377 		/* Only interrupts that are enabled */
378 		pending &= enabled;
379 
380 		for_each_set_bit(gpio, &pending, 32)
381 			generic_handle_domain_irq(gc->irq.domain, base + gpio);
382 	}
383 
384 	chained_irq_exit(irqchip, desc);
385 }
386 
387 static int tng_irq_init_hw(struct gpio_chip *chip)
388 {
389 	struct tng_gpio *priv = gpiochip_get_data(chip);
390 	void __iomem *reg;
391 	unsigned int base;
392 
393 	for (base = 0; base < priv->chip.ngpio; base += 32) {
394 		/* Clear the rising-edge detect register */
395 		reg = gpio_reg(&priv->chip, base, GRER);
396 		writel(0, reg);
397 
398 		/* Clear the falling-edge detect register */
399 		reg = gpio_reg(&priv->chip, base, GFER);
400 		writel(0, reg);
401 	}
402 
403 	return 0;
404 }
405 
406 static int tng_gpio_add_pin_ranges(struct gpio_chip *chip)
407 {
408 	struct tng_gpio *priv = gpiochip_get_data(chip);
409 	const struct tng_gpio_pinrange *range;
410 	unsigned int i;
411 	int ret;
412 
413 	for (i = 0; i < priv->pin_info.nranges; i++) {
414 		range = &priv->pin_info.pin_ranges[i];
415 		ret = gpiochip_add_pin_range(&priv->chip,
416 					     priv->pin_info.name,
417 					     range->gpio_base,
418 					     range->pin_base,
419 					     range->npins);
420 		if (ret) {
421 			dev_err(priv->dev, "failed to add GPIO pin range\n");
422 			return ret;
423 		}
424 	}
425 
426 	return 0;
427 }
428 
429 int devm_tng_gpio_probe(struct device *dev, struct tng_gpio *gpio)
430 {
431 	const struct tng_gpio_info *info = &gpio->info;
432 	size_t nctx = DIV_ROUND_UP(info->ngpio, 32);
433 	struct gpio_irq_chip *girq;
434 	int ret;
435 
436 	gpio->ctx = devm_kcalloc(dev, nctx, sizeof(*gpio->ctx), GFP_KERNEL);
437 	if (!gpio->ctx)
438 		return -ENOMEM;
439 
440 	gpio->chip.label = dev_name(dev);
441 	gpio->chip.parent = dev;
442 	gpio->chip.request = gpiochip_generic_request;
443 	gpio->chip.free = gpiochip_generic_free;
444 	gpio->chip.direction_input = tng_gpio_direction_input;
445 	gpio->chip.direction_output = tng_gpio_direction_output;
446 	gpio->chip.get = tng_gpio_get;
447 	gpio->chip.set = tng_gpio_set;
448 	gpio->chip.get_direction = tng_gpio_get_direction;
449 	gpio->chip.set_config = tng_gpio_set_config;
450 	gpio->chip.base = info->base;
451 	gpio->chip.ngpio = info->ngpio;
452 	gpio->chip.can_sleep = false;
453 	gpio->chip.add_pin_ranges = tng_gpio_add_pin_ranges;
454 
455 	raw_spin_lock_init(&gpio->lock);
456 
457 	girq = &gpio->chip.irq;
458 	gpio_irq_chip_set_chip(girq, &tng_irqchip);
459 	girq->init_hw = tng_irq_init_hw;
460 	girq->parent_handler = tng_irq_handler;
461 	girq->num_parents = 1;
462 	girq->parents = devm_kcalloc(dev, girq->num_parents,
463 				     sizeof(*girq->parents), GFP_KERNEL);
464 	if (!girq->parents)
465 		return -ENOMEM;
466 
467 	girq->parents[0] = gpio->irq;
468 	girq->first = info->first;
469 	girq->default_type = IRQ_TYPE_NONE;
470 	girq->handler = handle_bad_irq;
471 
472 	ret = devm_gpiochip_add_data(dev, &gpio->chip, gpio);
473 	if (ret)
474 		return dev_err_probe(dev, ret, "gpiochip_add error\n");
475 
476 	return 0;
477 }
478 EXPORT_SYMBOL_NS_GPL(devm_tng_gpio_probe, GPIO_TANGIER);
479 
480 int tng_gpio_suspend(struct device *dev)
481 {
482 	struct tng_gpio *priv = dev_get_drvdata(dev);
483 	struct tng_gpio_context *ctx = priv->ctx;
484 	unsigned long flags;
485 	unsigned int base;
486 
487 	raw_spin_lock_irqsave(&priv->lock, flags);
488 
489 	for (base = 0; base < priv->chip.ngpio; base += 32, ctx++) {
490 		/* GPLR is RO, values read will be restored using GPSR */
491 		ctx->level = readl(gpio_reg(&priv->chip, base, GPLR));
492 
493 		ctx->gpdr = readl(gpio_reg(&priv->chip, base, GPDR));
494 		ctx->grer = readl(gpio_reg(&priv->chip, base, GRER));
495 		ctx->gfer = readl(gpio_reg(&priv->chip, base, GFER));
496 		ctx->gimr = readl(gpio_reg(&priv->chip, base, GIMR));
497 
498 		ctx->gwmr = readl(gpio_reg(&priv->chip, base, priv->wake_regs.gwmr));
499 	}
500 
501 	raw_spin_unlock_irqrestore(&priv->lock, flags);
502 
503 	return 0;
504 }
505 EXPORT_SYMBOL_NS_GPL(tng_gpio_suspend, GPIO_TANGIER);
506 
507 int tng_gpio_resume(struct device *dev)
508 {
509 	struct tng_gpio *priv = dev_get_drvdata(dev);
510 	struct tng_gpio_context *ctx = priv->ctx;
511 	unsigned long flags;
512 	unsigned int base;
513 
514 	raw_spin_lock_irqsave(&priv->lock, flags);
515 
516 	for (base = 0; base < priv->chip.ngpio; base += 32, ctx++) {
517 		/* GPLR is RO, values read will be restored using GPSR */
518 		writel(ctx->level, gpio_reg(&priv->chip, base, GPSR));
519 
520 		writel(ctx->gpdr, gpio_reg(&priv->chip, base, GPDR));
521 		writel(ctx->grer, gpio_reg(&priv->chip, base, GRER));
522 		writel(ctx->gfer, gpio_reg(&priv->chip, base, GFER));
523 		writel(ctx->gimr, gpio_reg(&priv->chip, base, GIMR));
524 
525 		writel(ctx->gwmr, gpio_reg(&priv->chip, base, priv->wake_regs.gwmr));
526 	}
527 
528 	raw_spin_unlock_irqrestore(&priv->lock, flags);
529 
530 	return 0;
531 }
532 EXPORT_SYMBOL_NS_GPL(tng_gpio_resume, GPIO_TANGIER);
533 
534 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
535 MODULE_AUTHOR("Pandith N <pandith.n@intel.com>");
536 MODULE_AUTHOR("Raag Jadav <raag.jadav@intel.com>");
537 MODULE_DESCRIPTION("Intel Tangier GPIO driver");
538 MODULE_LICENSE("GPL");
539