16a8a0c1dSAlexander Shiyan /* 26a8a0c1dSAlexander Shiyan * SYSCON GPIO driver 36a8a0c1dSAlexander Shiyan * 46a8a0c1dSAlexander Shiyan * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> 56a8a0c1dSAlexander Shiyan * 66a8a0c1dSAlexander Shiyan * This program is free software; you can redistribute it and/or modify 76a8a0c1dSAlexander Shiyan * it under the terms of the GNU General Public License as published by 86a8a0c1dSAlexander Shiyan * the Free Software Foundation; either version 2 of the License, or 96a8a0c1dSAlexander Shiyan * (at your option) any later version. 106a8a0c1dSAlexander Shiyan */ 116a8a0c1dSAlexander Shiyan 126a8a0c1dSAlexander Shiyan #include <linux/err.h> 13122d00f7SLinus Walleij #include <linux/gpio/driver.h> 146a8a0c1dSAlexander Shiyan #include <linux/module.h> 156a8a0c1dSAlexander Shiyan #include <linux/of.h> 166a8a0c1dSAlexander Shiyan #include <linux/of_device.h> 176a8a0c1dSAlexander Shiyan #include <linux/platform_device.h> 186a8a0c1dSAlexander Shiyan #include <linux/regmap.h> 196a8a0c1dSAlexander Shiyan #include <linux/mfd/syscon.h> 206a8a0c1dSAlexander Shiyan 216a8a0c1dSAlexander Shiyan #define GPIO_SYSCON_FEAT_IN BIT(0) 226a8a0c1dSAlexander Shiyan #define GPIO_SYSCON_FEAT_OUT BIT(1) 236a8a0c1dSAlexander Shiyan #define GPIO_SYSCON_FEAT_DIR BIT(2) 246a8a0c1dSAlexander Shiyan 256a8a0c1dSAlexander Shiyan /* SYSCON driver is designed to use 32-bit wide registers */ 266a8a0c1dSAlexander Shiyan #define SYSCON_REG_SIZE (4) 276a8a0c1dSAlexander Shiyan #define SYSCON_REG_BITS (SYSCON_REG_SIZE * 8) 286a8a0c1dSAlexander Shiyan 296a8a0c1dSAlexander Shiyan /** 306a8a0c1dSAlexander Shiyan * struct syscon_gpio_data - Configuration for the device. 316a8a0c1dSAlexander Shiyan * compatible: SYSCON driver compatible string. 326a8a0c1dSAlexander Shiyan * flags: Set of GPIO_SYSCON_FEAT_ flags: 336a8a0c1dSAlexander Shiyan * GPIO_SYSCON_FEAT_IN: GPIOs supports input, 346a8a0c1dSAlexander Shiyan * GPIO_SYSCON_FEAT_OUT: GPIOs supports output, 356a8a0c1dSAlexander Shiyan * GPIO_SYSCON_FEAT_DIR: GPIOs supports switch direction. 366a8a0c1dSAlexander Shiyan * bit_count: Number of bits used as GPIOs. 376a8a0c1dSAlexander Shiyan * dat_bit_offset: Offset (in bits) to the first GPIO bit. 386a8a0c1dSAlexander Shiyan * dir_bit_offset: Optional offset (in bits) to the first bit to switch 396a8a0c1dSAlexander Shiyan * GPIO direction (Used with GPIO_SYSCON_FEAT_DIR flag). 402c341d62SGrygorii Strashko * set: HW specific callback to assigns output value 412c341d62SGrygorii Strashko * for signal "offset" 426a8a0c1dSAlexander Shiyan */ 436a8a0c1dSAlexander Shiyan 446a8a0c1dSAlexander Shiyan struct syscon_gpio_data { 456a8a0c1dSAlexander Shiyan const char *compatible; 466a8a0c1dSAlexander Shiyan unsigned int flags; 476a8a0c1dSAlexander Shiyan unsigned int bit_count; 486a8a0c1dSAlexander Shiyan unsigned int dat_bit_offset; 496a8a0c1dSAlexander Shiyan unsigned int dir_bit_offset; 502c341d62SGrygorii Strashko void (*set)(struct gpio_chip *chip, 512c341d62SGrygorii Strashko unsigned offset, int value); 526a8a0c1dSAlexander Shiyan }; 536a8a0c1dSAlexander Shiyan 546a8a0c1dSAlexander Shiyan struct syscon_gpio_priv { 556a8a0c1dSAlexander Shiyan struct gpio_chip chip; 566a8a0c1dSAlexander Shiyan struct regmap *syscon; 576a8a0c1dSAlexander Shiyan const struct syscon_gpio_data *data; 585a3e3f88SGrygorii Strashko u32 dreg_offset; 595a3e3f88SGrygorii Strashko u32 dir_reg_offset; 606a8a0c1dSAlexander Shiyan }; 616a8a0c1dSAlexander Shiyan 626a8a0c1dSAlexander Shiyan static int syscon_gpio_get(struct gpio_chip *chip, unsigned offset) 636a8a0c1dSAlexander Shiyan { 64d27ad7a8SLinus Walleij struct syscon_gpio_priv *priv = gpiochip_get_data(chip); 655a3e3f88SGrygorii Strashko unsigned int val, offs; 666a8a0c1dSAlexander Shiyan int ret; 676a8a0c1dSAlexander Shiyan 685a3e3f88SGrygorii Strashko offs = priv->dreg_offset + priv->data->dat_bit_offset + offset; 695a3e3f88SGrygorii Strashko 706a8a0c1dSAlexander Shiyan ret = regmap_read(priv->syscon, 716a8a0c1dSAlexander Shiyan (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, &val); 726a8a0c1dSAlexander Shiyan if (ret) 736a8a0c1dSAlexander Shiyan return ret; 746a8a0c1dSAlexander Shiyan 756a8a0c1dSAlexander Shiyan return !!(val & BIT(offs % SYSCON_REG_BITS)); 766a8a0c1dSAlexander Shiyan } 776a8a0c1dSAlexander Shiyan 786a8a0c1dSAlexander Shiyan static void syscon_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 796a8a0c1dSAlexander Shiyan { 80d27ad7a8SLinus Walleij struct syscon_gpio_priv *priv = gpiochip_get_data(chip); 815a3e3f88SGrygorii Strashko unsigned int offs; 825a3e3f88SGrygorii Strashko 835a3e3f88SGrygorii Strashko offs = priv->dreg_offset + priv->data->dat_bit_offset + offset; 846a8a0c1dSAlexander Shiyan 856a8a0c1dSAlexander Shiyan regmap_update_bits(priv->syscon, 866a8a0c1dSAlexander Shiyan (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, 876a8a0c1dSAlexander Shiyan BIT(offs % SYSCON_REG_BITS), 886a8a0c1dSAlexander Shiyan val ? BIT(offs % SYSCON_REG_BITS) : 0); 896a8a0c1dSAlexander Shiyan } 906a8a0c1dSAlexander Shiyan 916a8a0c1dSAlexander Shiyan static int syscon_gpio_dir_in(struct gpio_chip *chip, unsigned offset) 926a8a0c1dSAlexander Shiyan { 93d27ad7a8SLinus Walleij struct syscon_gpio_priv *priv = gpiochip_get_data(chip); 946a8a0c1dSAlexander Shiyan 956a8a0c1dSAlexander Shiyan if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) { 965a3e3f88SGrygorii Strashko unsigned int offs; 975a3e3f88SGrygorii Strashko 985a3e3f88SGrygorii Strashko offs = priv->dir_reg_offset + 995a3e3f88SGrygorii Strashko priv->data->dir_bit_offset + offset; 1006a8a0c1dSAlexander Shiyan 1016a8a0c1dSAlexander Shiyan regmap_update_bits(priv->syscon, 1026a8a0c1dSAlexander Shiyan (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, 1036a8a0c1dSAlexander Shiyan BIT(offs % SYSCON_REG_BITS), 0); 1046a8a0c1dSAlexander Shiyan } 1056a8a0c1dSAlexander Shiyan 1066a8a0c1dSAlexander Shiyan return 0; 1076a8a0c1dSAlexander Shiyan } 1086a8a0c1dSAlexander Shiyan 1096a8a0c1dSAlexander Shiyan static int syscon_gpio_dir_out(struct gpio_chip *chip, unsigned offset, int val) 1106a8a0c1dSAlexander Shiyan { 111d27ad7a8SLinus Walleij struct syscon_gpio_priv *priv = gpiochip_get_data(chip); 1126a8a0c1dSAlexander Shiyan 1136a8a0c1dSAlexander Shiyan if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) { 1145a3e3f88SGrygorii Strashko unsigned int offs; 1155a3e3f88SGrygorii Strashko 1165a3e3f88SGrygorii Strashko offs = priv->dir_reg_offset + 1175a3e3f88SGrygorii Strashko priv->data->dir_bit_offset + offset; 1186a8a0c1dSAlexander Shiyan 1196a8a0c1dSAlexander Shiyan regmap_update_bits(priv->syscon, 1206a8a0c1dSAlexander Shiyan (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, 1216a8a0c1dSAlexander Shiyan BIT(offs % SYSCON_REG_BITS), 1226a8a0c1dSAlexander Shiyan BIT(offs % SYSCON_REG_BITS)); 1236a8a0c1dSAlexander Shiyan } 1246a8a0c1dSAlexander Shiyan 12570728c29SMarek Vasut chip->set(chip, offset, val); 1266a8a0c1dSAlexander Shiyan 1276a8a0c1dSAlexander Shiyan return 0; 1286a8a0c1dSAlexander Shiyan } 1296a8a0c1dSAlexander Shiyan 1306a8a0c1dSAlexander Shiyan static const struct syscon_gpio_data clps711x_mctrl_gpio = { 1316a8a0c1dSAlexander Shiyan /* ARM CLPS711X SYSFLG1 Bits 8-10 */ 1322e607fcaSAlexander Shiyan .compatible = "cirrus,ep7209-syscon1", 1336a8a0c1dSAlexander Shiyan .flags = GPIO_SYSCON_FEAT_IN, 1346a8a0c1dSAlexander Shiyan .bit_count = 3, 1356a8a0c1dSAlexander Shiyan .dat_bit_offset = 0x40 * 8 + 8, 1366a8a0c1dSAlexander Shiyan }; 1376a8a0c1dSAlexander Shiyan 138cf2ff877SLevin Du static void rockchip_gpio_set(struct gpio_chip *chip, unsigned int offset, 139cf2ff877SLevin Du int val) 140cf2ff877SLevin Du { 141cf2ff877SLevin Du struct syscon_gpio_priv *priv = gpiochip_get_data(chip); 142cf2ff877SLevin Du unsigned int offs; 143cf2ff877SLevin Du u8 bit; 144cf2ff877SLevin Du u32 data; 145cf2ff877SLevin Du int ret; 146cf2ff877SLevin Du 147cf2ff877SLevin Du offs = priv->dreg_offset + priv->data->dat_bit_offset + offset; 148cf2ff877SLevin Du bit = offs % SYSCON_REG_BITS; 149cf2ff877SLevin Du data = (val ? BIT(bit) : 0) | BIT(bit + 16); 150cf2ff877SLevin Du ret = regmap_write(priv->syscon, 151cf2ff877SLevin Du (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, 152cf2ff877SLevin Du data); 153cf2ff877SLevin Du if (ret < 0) 154cf2ff877SLevin Du dev_err(chip->parent, "gpio write failed ret(%d)\n", ret); 155cf2ff877SLevin Du } 156cf2ff877SLevin Du 157cf2ff877SLevin Du static const struct syscon_gpio_data rockchip_rk3328_gpio_mute = { 158cf2ff877SLevin Du /* RK3328 GPIO_MUTE is an output only pin at GRF_SOC_CON10[1] */ 159cf2ff877SLevin Du .flags = GPIO_SYSCON_FEAT_OUT, 160cf2ff877SLevin Du .bit_count = 1, 161cf2ff877SLevin Du .dat_bit_offset = 0x0428 * 8 + 1, 162cf2ff877SLevin Du .set = rockchip_gpio_set, 163cf2ff877SLevin Du }; 164cf2ff877SLevin Du 1652134cb99SGrygorii Strashko #define KEYSTONE_LOCK_BIT BIT(0) 1662134cb99SGrygorii Strashko 1672134cb99SGrygorii Strashko static void keystone_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 1682134cb99SGrygorii Strashko { 169d27ad7a8SLinus Walleij struct syscon_gpio_priv *priv = gpiochip_get_data(chip); 1702134cb99SGrygorii Strashko unsigned int offs; 1712134cb99SGrygorii Strashko int ret; 1722134cb99SGrygorii Strashko 1732134cb99SGrygorii Strashko offs = priv->dreg_offset + priv->data->dat_bit_offset + offset; 1742134cb99SGrygorii Strashko 1752134cb99SGrygorii Strashko if (!val) 1762134cb99SGrygorii Strashko return; 1772134cb99SGrygorii Strashko 1782134cb99SGrygorii Strashko ret = regmap_update_bits( 1792134cb99SGrygorii Strashko priv->syscon, 1802134cb99SGrygorii Strashko (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, 1812134cb99SGrygorii Strashko BIT(offs % SYSCON_REG_BITS) | KEYSTONE_LOCK_BIT, 1822134cb99SGrygorii Strashko BIT(offs % SYSCON_REG_BITS) | KEYSTONE_LOCK_BIT); 1832134cb99SGrygorii Strashko if (ret < 0) 18458383c78SLinus Walleij dev_err(chip->parent, "gpio write failed ret(%d)\n", ret); 1852134cb99SGrygorii Strashko } 1862134cb99SGrygorii Strashko 1872134cb99SGrygorii Strashko static const struct syscon_gpio_data keystone_dsp_gpio = { 1882134cb99SGrygorii Strashko /* ARM Keystone 2 */ 1892134cb99SGrygorii Strashko .compatible = NULL, 1902134cb99SGrygorii Strashko .flags = GPIO_SYSCON_FEAT_OUT, 1912134cb99SGrygorii Strashko .bit_count = 28, 1922134cb99SGrygorii Strashko .dat_bit_offset = 4, 1932134cb99SGrygorii Strashko .set = keystone_gpio_set, 1942134cb99SGrygorii Strashko }; 1952134cb99SGrygorii Strashko 1966a8a0c1dSAlexander Shiyan static const struct of_device_id syscon_gpio_ids[] = { 1976a8a0c1dSAlexander Shiyan { 1982e607fcaSAlexander Shiyan .compatible = "cirrus,ep7209-mctrl-gpio", 1996a8a0c1dSAlexander Shiyan .data = &clps711x_mctrl_gpio, 2006a8a0c1dSAlexander Shiyan }, 2012134cb99SGrygorii Strashko { 2022134cb99SGrygorii Strashko .compatible = "ti,keystone-dsp-gpio", 2032134cb99SGrygorii Strashko .data = &keystone_dsp_gpio, 2042134cb99SGrygorii Strashko }, 205cf2ff877SLevin Du { 206cf2ff877SLevin Du .compatible = "rockchip,rk3328-grf-gpio", 207cf2ff877SLevin Du .data = &rockchip_rk3328_gpio_mute, 208cf2ff877SLevin Du }, 2096a8a0c1dSAlexander Shiyan { } 2106a8a0c1dSAlexander Shiyan }; 2116a8a0c1dSAlexander Shiyan MODULE_DEVICE_TABLE(of, syscon_gpio_ids); 2126a8a0c1dSAlexander Shiyan 2136a8a0c1dSAlexander Shiyan static int syscon_gpio_probe(struct platform_device *pdev) 2146a8a0c1dSAlexander Shiyan { 2156a8a0c1dSAlexander Shiyan struct device *dev = &pdev->dev; 2166a8a0c1dSAlexander Shiyan struct syscon_gpio_priv *priv; 2175a3e3f88SGrygorii Strashko struct device_node *np = dev->of_node; 2185a3e3f88SGrygorii Strashko int ret; 2196a8a0c1dSAlexander Shiyan 2206a8a0c1dSAlexander Shiyan priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 2216a8a0c1dSAlexander Shiyan if (!priv) 2226a8a0c1dSAlexander Shiyan return -ENOMEM; 2236a8a0c1dSAlexander Shiyan 224edf874efSThierry Reding priv->data = of_device_get_match_data(dev); 2256a8a0c1dSAlexander Shiyan 2265a3e3f88SGrygorii Strashko if (priv->data->compatible) { 2275a3e3f88SGrygorii Strashko priv->syscon = syscon_regmap_lookup_by_compatible( 2285a3e3f88SGrygorii Strashko priv->data->compatible); 2296a8a0c1dSAlexander Shiyan if (IS_ERR(priv->syscon)) 2306a8a0c1dSAlexander Shiyan return PTR_ERR(priv->syscon); 2315a3e3f88SGrygorii Strashko } else { 2325a3e3f88SGrygorii Strashko priv->syscon = 2335a3e3f88SGrygorii Strashko syscon_regmap_lookup_by_phandle(np, "gpio,syscon-dev"); 234aa1fdda8SHeiko Stuebner if (IS_ERR(priv->syscon) && np->parent) 235aa1fdda8SHeiko Stuebner priv->syscon = syscon_node_to_regmap(np->parent); 2365a3e3f88SGrygorii Strashko if (IS_ERR(priv->syscon)) 2375a3e3f88SGrygorii Strashko return PTR_ERR(priv->syscon); 2385a3e3f88SGrygorii Strashko 2395a3e3f88SGrygorii Strashko ret = of_property_read_u32_index(np, "gpio,syscon-dev", 1, 2405a3e3f88SGrygorii Strashko &priv->dreg_offset); 2415a3e3f88SGrygorii Strashko if (ret) 2425a3e3f88SGrygorii Strashko dev_err(dev, "can't read the data register offset!\n"); 2435a3e3f88SGrygorii Strashko 2445a3e3f88SGrygorii Strashko priv->dreg_offset <<= 3; 2455a3e3f88SGrygorii Strashko 2465a3e3f88SGrygorii Strashko ret = of_property_read_u32_index(np, "gpio,syscon-dev", 2, 2475a3e3f88SGrygorii Strashko &priv->dir_reg_offset); 2485a3e3f88SGrygorii Strashko if (ret) 249c6ac19daSGrygorii Strashko dev_dbg(dev, "can't read the dir register offset!\n"); 2505a3e3f88SGrygorii Strashko 2515a3e3f88SGrygorii Strashko priv->dir_reg_offset <<= 3; 2525a3e3f88SGrygorii Strashko } 2536a8a0c1dSAlexander Shiyan 25458383c78SLinus Walleij priv->chip.parent = dev; 2556a8a0c1dSAlexander Shiyan priv->chip.owner = THIS_MODULE; 2566a8a0c1dSAlexander Shiyan priv->chip.label = dev_name(dev); 2576a8a0c1dSAlexander Shiyan priv->chip.base = -1; 2586a8a0c1dSAlexander Shiyan priv->chip.ngpio = priv->data->bit_count; 2596a8a0c1dSAlexander Shiyan priv->chip.get = syscon_gpio_get; 2606a8a0c1dSAlexander Shiyan if (priv->data->flags & GPIO_SYSCON_FEAT_IN) 2616a8a0c1dSAlexander Shiyan priv->chip.direction_input = syscon_gpio_dir_in; 2626a8a0c1dSAlexander Shiyan if (priv->data->flags & GPIO_SYSCON_FEAT_OUT) { 2632c341d62SGrygorii Strashko priv->chip.set = priv->data->set ? : syscon_gpio_set; 2646a8a0c1dSAlexander Shiyan priv->chip.direction_output = syscon_gpio_dir_out; 2656a8a0c1dSAlexander Shiyan } 2666a8a0c1dSAlexander Shiyan 2676a8a0c1dSAlexander Shiyan platform_set_drvdata(pdev, priv); 2686a8a0c1dSAlexander Shiyan 26994c683abSLaxman Dewangan return devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv); 2706a8a0c1dSAlexander Shiyan } 2716a8a0c1dSAlexander Shiyan 2726a8a0c1dSAlexander Shiyan static struct platform_driver syscon_gpio_driver = { 2736a8a0c1dSAlexander Shiyan .driver = { 2746a8a0c1dSAlexander Shiyan .name = "gpio-syscon", 2756a8a0c1dSAlexander Shiyan .of_match_table = syscon_gpio_ids, 2766a8a0c1dSAlexander Shiyan }, 2776a8a0c1dSAlexander Shiyan .probe = syscon_gpio_probe, 2786a8a0c1dSAlexander Shiyan }; 2796a8a0c1dSAlexander Shiyan module_platform_driver(syscon_gpio_driver); 2806a8a0c1dSAlexander Shiyan 2816a8a0c1dSAlexander Shiyan MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 2826a8a0c1dSAlexander Shiyan MODULE_DESCRIPTION("SYSCON GPIO driver"); 2836a8a0c1dSAlexander Shiyan MODULE_LICENSE("GPL"); 284