12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 26a8a0c1dSAlexander Shiyan /* 36a8a0c1dSAlexander Shiyan * SYSCON GPIO driver 46a8a0c1dSAlexander Shiyan * 56a8a0c1dSAlexander Shiyan * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> 66a8a0c1dSAlexander Shiyan */ 76a8a0c1dSAlexander Shiyan 86a8a0c1dSAlexander Shiyan #include <linux/err.h> 9122d00f7SLinus Walleij #include <linux/gpio/driver.h> 106a8a0c1dSAlexander Shiyan #include <linux/module.h> 116a8a0c1dSAlexander Shiyan #include <linux/of.h> 126a8a0c1dSAlexander Shiyan #include <linux/of_device.h> 136a8a0c1dSAlexander Shiyan #include <linux/platform_device.h> 146a8a0c1dSAlexander Shiyan #include <linux/regmap.h> 156a8a0c1dSAlexander Shiyan #include <linux/mfd/syscon.h> 166a8a0c1dSAlexander Shiyan 176a8a0c1dSAlexander Shiyan #define GPIO_SYSCON_FEAT_IN BIT(0) 186a8a0c1dSAlexander Shiyan #define GPIO_SYSCON_FEAT_OUT BIT(1) 196a8a0c1dSAlexander Shiyan #define GPIO_SYSCON_FEAT_DIR BIT(2) 206a8a0c1dSAlexander Shiyan 216a8a0c1dSAlexander Shiyan /* SYSCON driver is designed to use 32-bit wide registers */ 226a8a0c1dSAlexander Shiyan #define SYSCON_REG_SIZE (4) 236a8a0c1dSAlexander Shiyan #define SYSCON_REG_BITS (SYSCON_REG_SIZE * 8) 246a8a0c1dSAlexander Shiyan 256a8a0c1dSAlexander Shiyan /** 266a8a0c1dSAlexander Shiyan * struct syscon_gpio_data - Configuration for the device. 275f3beb67SLee Jones * @compatible: SYSCON driver compatible string. 285f3beb67SLee Jones * @flags: Set of GPIO_SYSCON_FEAT_ flags: 296a8a0c1dSAlexander Shiyan * GPIO_SYSCON_FEAT_IN: GPIOs supports input, 306a8a0c1dSAlexander Shiyan * GPIO_SYSCON_FEAT_OUT: GPIOs supports output, 316a8a0c1dSAlexander Shiyan * GPIO_SYSCON_FEAT_DIR: GPIOs supports switch direction. 325f3beb67SLee Jones * @bit_count: Number of bits used as GPIOs. 335f3beb67SLee Jones * @dat_bit_offset: Offset (in bits) to the first GPIO bit. 345f3beb67SLee Jones * @dir_bit_offset: Optional offset (in bits) to the first bit to switch 356a8a0c1dSAlexander Shiyan * GPIO direction (Used with GPIO_SYSCON_FEAT_DIR flag). 365f3beb67SLee Jones * @set: HW specific callback to assigns output value 372c341d62SGrygorii Strashko * for signal "offset" 386a8a0c1dSAlexander Shiyan */ 396a8a0c1dSAlexander Shiyan 406a8a0c1dSAlexander Shiyan struct syscon_gpio_data { 416a8a0c1dSAlexander Shiyan unsigned int flags; 426a8a0c1dSAlexander Shiyan unsigned int bit_count; 436a8a0c1dSAlexander Shiyan unsigned int dat_bit_offset; 446a8a0c1dSAlexander Shiyan unsigned int dir_bit_offset; 452c341d62SGrygorii Strashko void (*set)(struct gpio_chip *chip, 462c341d62SGrygorii Strashko unsigned offset, int value); 476a8a0c1dSAlexander Shiyan }; 486a8a0c1dSAlexander Shiyan 496a8a0c1dSAlexander Shiyan struct syscon_gpio_priv { 506a8a0c1dSAlexander Shiyan struct gpio_chip chip; 516a8a0c1dSAlexander Shiyan struct regmap *syscon; 526a8a0c1dSAlexander Shiyan const struct syscon_gpio_data *data; 535a3e3f88SGrygorii Strashko u32 dreg_offset; 545a3e3f88SGrygorii Strashko u32 dir_reg_offset; 556a8a0c1dSAlexander Shiyan }; 566a8a0c1dSAlexander Shiyan 576a8a0c1dSAlexander Shiyan static int syscon_gpio_get(struct gpio_chip *chip, unsigned offset) 586a8a0c1dSAlexander Shiyan { 59d27ad7a8SLinus Walleij struct syscon_gpio_priv *priv = gpiochip_get_data(chip); 605a3e3f88SGrygorii Strashko unsigned int val, offs; 616a8a0c1dSAlexander Shiyan int ret; 626a8a0c1dSAlexander Shiyan 635a3e3f88SGrygorii Strashko offs = priv->dreg_offset + priv->data->dat_bit_offset + offset; 645a3e3f88SGrygorii Strashko 656a8a0c1dSAlexander Shiyan ret = regmap_read(priv->syscon, 666a8a0c1dSAlexander Shiyan (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, &val); 676a8a0c1dSAlexander Shiyan if (ret) 686a8a0c1dSAlexander Shiyan return ret; 696a8a0c1dSAlexander Shiyan 706a8a0c1dSAlexander Shiyan return !!(val & BIT(offs % SYSCON_REG_BITS)); 716a8a0c1dSAlexander Shiyan } 726a8a0c1dSAlexander Shiyan 736a8a0c1dSAlexander Shiyan static void syscon_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 746a8a0c1dSAlexander Shiyan { 75d27ad7a8SLinus Walleij struct syscon_gpio_priv *priv = gpiochip_get_data(chip); 765a3e3f88SGrygorii Strashko unsigned int offs; 775a3e3f88SGrygorii Strashko 785a3e3f88SGrygorii Strashko offs = priv->dreg_offset + priv->data->dat_bit_offset + offset; 796a8a0c1dSAlexander Shiyan 806a8a0c1dSAlexander Shiyan regmap_update_bits(priv->syscon, 816a8a0c1dSAlexander Shiyan (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, 826a8a0c1dSAlexander Shiyan BIT(offs % SYSCON_REG_BITS), 836a8a0c1dSAlexander Shiyan val ? BIT(offs % SYSCON_REG_BITS) : 0); 846a8a0c1dSAlexander Shiyan } 856a8a0c1dSAlexander Shiyan 866a8a0c1dSAlexander Shiyan static int syscon_gpio_dir_in(struct gpio_chip *chip, unsigned offset) 876a8a0c1dSAlexander Shiyan { 88d27ad7a8SLinus Walleij struct syscon_gpio_priv *priv = gpiochip_get_data(chip); 896a8a0c1dSAlexander Shiyan 906a8a0c1dSAlexander Shiyan if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) { 915a3e3f88SGrygorii Strashko unsigned int offs; 925a3e3f88SGrygorii Strashko 935a3e3f88SGrygorii Strashko offs = priv->dir_reg_offset + 945a3e3f88SGrygorii Strashko priv->data->dir_bit_offset + offset; 956a8a0c1dSAlexander Shiyan 966a8a0c1dSAlexander Shiyan regmap_update_bits(priv->syscon, 976a8a0c1dSAlexander Shiyan (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, 986a8a0c1dSAlexander Shiyan BIT(offs % SYSCON_REG_BITS), 0); 996a8a0c1dSAlexander Shiyan } 1006a8a0c1dSAlexander Shiyan 1016a8a0c1dSAlexander Shiyan return 0; 1026a8a0c1dSAlexander Shiyan } 1036a8a0c1dSAlexander Shiyan 1046a8a0c1dSAlexander Shiyan static int syscon_gpio_dir_out(struct gpio_chip *chip, unsigned offset, int val) 1056a8a0c1dSAlexander Shiyan { 106d27ad7a8SLinus Walleij struct syscon_gpio_priv *priv = gpiochip_get_data(chip); 1076a8a0c1dSAlexander Shiyan 1086a8a0c1dSAlexander Shiyan if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) { 1095a3e3f88SGrygorii Strashko unsigned int offs; 1105a3e3f88SGrygorii Strashko 1115a3e3f88SGrygorii Strashko offs = priv->dir_reg_offset + 1125a3e3f88SGrygorii Strashko priv->data->dir_bit_offset + offset; 1136a8a0c1dSAlexander Shiyan 1146a8a0c1dSAlexander Shiyan regmap_update_bits(priv->syscon, 1156a8a0c1dSAlexander Shiyan (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, 1166a8a0c1dSAlexander Shiyan BIT(offs % SYSCON_REG_BITS), 1176a8a0c1dSAlexander Shiyan BIT(offs % SYSCON_REG_BITS)); 1186a8a0c1dSAlexander Shiyan } 1196a8a0c1dSAlexander Shiyan 12070728c29SMarek Vasut chip->set(chip, offset, val); 1216a8a0c1dSAlexander Shiyan 1226a8a0c1dSAlexander Shiyan return 0; 1236a8a0c1dSAlexander Shiyan } 1246a8a0c1dSAlexander Shiyan 1256a8a0c1dSAlexander Shiyan static const struct syscon_gpio_data clps711x_mctrl_gpio = { 1266a8a0c1dSAlexander Shiyan /* ARM CLPS711X SYSFLG1 Bits 8-10 */ 1276a8a0c1dSAlexander Shiyan .flags = GPIO_SYSCON_FEAT_IN, 1286a8a0c1dSAlexander Shiyan .bit_count = 3, 1296a8a0c1dSAlexander Shiyan .dat_bit_offset = 0x40 * 8 + 8, 1306a8a0c1dSAlexander Shiyan }; 1316a8a0c1dSAlexander Shiyan 132cf2ff877SLevin Du static void rockchip_gpio_set(struct gpio_chip *chip, unsigned int offset, 133cf2ff877SLevin Du int val) 134cf2ff877SLevin Du { 135cf2ff877SLevin Du struct syscon_gpio_priv *priv = gpiochip_get_data(chip); 136cf2ff877SLevin Du unsigned int offs; 137cf2ff877SLevin Du u8 bit; 138cf2ff877SLevin Du u32 data; 139cf2ff877SLevin Du int ret; 140cf2ff877SLevin Du 141cf2ff877SLevin Du offs = priv->dreg_offset + priv->data->dat_bit_offset + offset; 142cf2ff877SLevin Du bit = offs % SYSCON_REG_BITS; 143cf2ff877SLevin Du data = (val ? BIT(bit) : 0) | BIT(bit + 16); 144cf2ff877SLevin Du ret = regmap_write(priv->syscon, 145cf2ff877SLevin Du (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, 146cf2ff877SLevin Du data); 147cf2ff877SLevin Du if (ret < 0) 148cf2ff877SLevin Du dev_err(chip->parent, "gpio write failed ret(%d)\n", ret); 149cf2ff877SLevin Du } 150cf2ff877SLevin Du 151cf2ff877SLevin Du static const struct syscon_gpio_data rockchip_rk3328_gpio_mute = { 152cf2ff877SLevin Du /* RK3328 GPIO_MUTE is an output only pin at GRF_SOC_CON10[1] */ 153cf2ff877SLevin Du .flags = GPIO_SYSCON_FEAT_OUT, 154cf2ff877SLevin Du .bit_count = 1, 155cf2ff877SLevin Du .dat_bit_offset = 0x0428 * 8 + 1, 156cf2ff877SLevin Du .set = rockchip_gpio_set, 157cf2ff877SLevin Du }; 158cf2ff877SLevin Du 1592134cb99SGrygorii Strashko #define KEYSTONE_LOCK_BIT BIT(0) 1602134cb99SGrygorii Strashko 1612134cb99SGrygorii Strashko static void keystone_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 1622134cb99SGrygorii Strashko { 163d27ad7a8SLinus Walleij struct syscon_gpio_priv *priv = gpiochip_get_data(chip); 1642134cb99SGrygorii Strashko unsigned int offs; 1652134cb99SGrygorii Strashko int ret; 1662134cb99SGrygorii Strashko 1672134cb99SGrygorii Strashko offs = priv->dreg_offset + priv->data->dat_bit_offset + offset; 1682134cb99SGrygorii Strashko 1692134cb99SGrygorii Strashko if (!val) 1702134cb99SGrygorii Strashko return; 1712134cb99SGrygorii Strashko 1722134cb99SGrygorii Strashko ret = regmap_update_bits( 1732134cb99SGrygorii Strashko priv->syscon, 1742134cb99SGrygorii Strashko (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, 1752134cb99SGrygorii Strashko BIT(offs % SYSCON_REG_BITS) | KEYSTONE_LOCK_BIT, 1762134cb99SGrygorii Strashko BIT(offs % SYSCON_REG_BITS) | KEYSTONE_LOCK_BIT); 1772134cb99SGrygorii Strashko if (ret < 0) 17858383c78SLinus Walleij dev_err(chip->parent, "gpio write failed ret(%d)\n", ret); 1792134cb99SGrygorii Strashko } 1802134cb99SGrygorii Strashko 1812134cb99SGrygorii Strashko static const struct syscon_gpio_data keystone_dsp_gpio = { 1822134cb99SGrygorii Strashko /* ARM Keystone 2 */ 1832134cb99SGrygorii Strashko .flags = GPIO_SYSCON_FEAT_OUT, 1842134cb99SGrygorii Strashko .bit_count = 28, 1852134cb99SGrygorii Strashko .dat_bit_offset = 4, 1862134cb99SGrygorii Strashko .set = keystone_gpio_set, 1872134cb99SGrygorii Strashko }; 1882134cb99SGrygorii Strashko 1896a8a0c1dSAlexander Shiyan static const struct of_device_id syscon_gpio_ids[] = { 1906a8a0c1dSAlexander Shiyan { 1912e607fcaSAlexander Shiyan .compatible = "cirrus,ep7209-mctrl-gpio", 1926a8a0c1dSAlexander Shiyan .data = &clps711x_mctrl_gpio, 1936a8a0c1dSAlexander Shiyan }, 1942134cb99SGrygorii Strashko { 1952134cb99SGrygorii Strashko .compatible = "ti,keystone-dsp-gpio", 1962134cb99SGrygorii Strashko .data = &keystone_dsp_gpio, 1972134cb99SGrygorii Strashko }, 198cf2ff877SLevin Du { 199cf2ff877SLevin Du .compatible = "rockchip,rk3328-grf-gpio", 200cf2ff877SLevin Du .data = &rockchip_rk3328_gpio_mute, 201cf2ff877SLevin Du }, 2026a8a0c1dSAlexander Shiyan { } 2036a8a0c1dSAlexander Shiyan }; 2046a8a0c1dSAlexander Shiyan MODULE_DEVICE_TABLE(of, syscon_gpio_ids); 2056a8a0c1dSAlexander Shiyan 2066a8a0c1dSAlexander Shiyan static int syscon_gpio_probe(struct platform_device *pdev) 2076a8a0c1dSAlexander Shiyan { 2086a8a0c1dSAlexander Shiyan struct device *dev = &pdev->dev; 2096a8a0c1dSAlexander Shiyan struct syscon_gpio_priv *priv; 2105a3e3f88SGrygorii Strashko struct device_node *np = dev->of_node; 2115a3e3f88SGrygorii Strashko int ret; 2126a8a0c1dSAlexander Shiyan 2136a8a0c1dSAlexander Shiyan priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 2146a8a0c1dSAlexander Shiyan if (!priv) 2156a8a0c1dSAlexander Shiyan return -ENOMEM; 2166a8a0c1dSAlexander Shiyan 217edf874efSThierry Reding priv->data = of_device_get_match_data(dev); 2186a8a0c1dSAlexander Shiyan 219*2e9cf845SAlexander Shiyan priv->syscon = syscon_regmap_lookup_by_phandle(np, "gpio,syscon-dev"); 220aa1fdda8SHeiko Stuebner if (IS_ERR(priv->syscon) && np->parent) 221aa1fdda8SHeiko Stuebner priv->syscon = syscon_node_to_regmap(np->parent); 2225a3e3f88SGrygorii Strashko if (IS_ERR(priv->syscon)) 2235a3e3f88SGrygorii Strashko return PTR_ERR(priv->syscon); 2245a3e3f88SGrygorii Strashko 2255a3e3f88SGrygorii Strashko ret = of_property_read_u32_index(np, "gpio,syscon-dev", 1, 2265a3e3f88SGrygorii Strashko &priv->dreg_offset); 2275a3e3f88SGrygorii Strashko if (ret) 2285a3e3f88SGrygorii Strashko dev_err(dev, "can't read the data register offset!\n"); 2295a3e3f88SGrygorii Strashko 2305a3e3f88SGrygorii Strashko priv->dreg_offset <<= 3; 2315a3e3f88SGrygorii Strashko 2325a3e3f88SGrygorii Strashko ret = of_property_read_u32_index(np, "gpio,syscon-dev", 2, 2335a3e3f88SGrygorii Strashko &priv->dir_reg_offset); 2345a3e3f88SGrygorii Strashko if (ret) 235c6ac19daSGrygorii Strashko dev_dbg(dev, "can't read the dir register offset!\n"); 2365a3e3f88SGrygorii Strashko 2375a3e3f88SGrygorii Strashko priv->dir_reg_offset <<= 3; 2386a8a0c1dSAlexander Shiyan 23958383c78SLinus Walleij priv->chip.parent = dev; 2406a8a0c1dSAlexander Shiyan priv->chip.owner = THIS_MODULE; 2416a8a0c1dSAlexander Shiyan priv->chip.label = dev_name(dev); 2426a8a0c1dSAlexander Shiyan priv->chip.base = -1; 2436a8a0c1dSAlexander Shiyan priv->chip.ngpio = priv->data->bit_count; 2446a8a0c1dSAlexander Shiyan priv->chip.get = syscon_gpio_get; 2456a8a0c1dSAlexander Shiyan if (priv->data->flags & GPIO_SYSCON_FEAT_IN) 2466a8a0c1dSAlexander Shiyan priv->chip.direction_input = syscon_gpio_dir_in; 2476a8a0c1dSAlexander Shiyan if (priv->data->flags & GPIO_SYSCON_FEAT_OUT) { 2482c341d62SGrygorii Strashko priv->chip.set = priv->data->set ? : syscon_gpio_set; 2496a8a0c1dSAlexander Shiyan priv->chip.direction_output = syscon_gpio_dir_out; 2506a8a0c1dSAlexander Shiyan } 2516a8a0c1dSAlexander Shiyan 2526a8a0c1dSAlexander Shiyan platform_set_drvdata(pdev, priv); 2536a8a0c1dSAlexander Shiyan 25494c683abSLaxman Dewangan return devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv); 2556a8a0c1dSAlexander Shiyan } 2566a8a0c1dSAlexander Shiyan 2576a8a0c1dSAlexander Shiyan static struct platform_driver syscon_gpio_driver = { 2586a8a0c1dSAlexander Shiyan .driver = { 2596a8a0c1dSAlexander Shiyan .name = "gpio-syscon", 2606a8a0c1dSAlexander Shiyan .of_match_table = syscon_gpio_ids, 2616a8a0c1dSAlexander Shiyan }, 2626a8a0c1dSAlexander Shiyan .probe = syscon_gpio_probe, 2636a8a0c1dSAlexander Shiyan }; 2646a8a0c1dSAlexander Shiyan module_platform_driver(syscon_gpio_driver); 2656a8a0c1dSAlexander Shiyan 2666a8a0c1dSAlexander Shiyan MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 2676a8a0c1dSAlexander Shiyan MODULE_DESCRIPTION("SYSCON GPIO driver"); 2686a8a0c1dSAlexander Shiyan MODULE_LICENSE("GPL"); 269