16a8a0c1dSAlexander Shiyan /* 26a8a0c1dSAlexander Shiyan * SYSCON GPIO driver 36a8a0c1dSAlexander Shiyan * 46a8a0c1dSAlexander Shiyan * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> 56a8a0c1dSAlexander Shiyan * 66a8a0c1dSAlexander Shiyan * This program is free software; you can redistribute it and/or modify 76a8a0c1dSAlexander Shiyan * it under the terms of the GNU General Public License as published by 86a8a0c1dSAlexander Shiyan * the Free Software Foundation; either version 2 of the License, or 96a8a0c1dSAlexander Shiyan * (at your option) any later version. 106a8a0c1dSAlexander Shiyan */ 116a8a0c1dSAlexander Shiyan 126a8a0c1dSAlexander Shiyan #include <linux/err.h> 136a8a0c1dSAlexander Shiyan #include <linux/gpio.h> 146a8a0c1dSAlexander Shiyan #include <linux/module.h> 156a8a0c1dSAlexander Shiyan #include <linux/of.h> 166a8a0c1dSAlexander Shiyan #include <linux/of_device.h> 176a8a0c1dSAlexander Shiyan #include <linux/platform_device.h> 186a8a0c1dSAlexander Shiyan #include <linux/regmap.h> 196a8a0c1dSAlexander Shiyan #include <linux/mfd/syscon.h> 206a8a0c1dSAlexander Shiyan 216a8a0c1dSAlexander Shiyan #define GPIO_SYSCON_FEAT_IN BIT(0) 226a8a0c1dSAlexander Shiyan #define GPIO_SYSCON_FEAT_OUT BIT(1) 236a8a0c1dSAlexander Shiyan #define GPIO_SYSCON_FEAT_DIR BIT(2) 246a8a0c1dSAlexander Shiyan 256a8a0c1dSAlexander Shiyan /* SYSCON driver is designed to use 32-bit wide registers */ 266a8a0c1dSAlexander Shiyan #define SYSCON_REG_SIZE (4) 276a8a0c1dSAlexander Shiyan #define SYSCON_REG_BITS (SYSCON_REG_SIZE * 8) 286a8a0c1dSAlexander Shiyan 296a8a0c1dSAlexander Shiyan /** 306a8a0c1dSAlexander Shiyan * struct syscon_gpio_data - Configuration for the device. 316a8a0c1dSAlexander Shiyan * compatible: SYSCON driver compatible string. 326a8a0c1dSAlexander Shiyan * flags: Set of GPIO_SYSCON_FEAT_ flags: 336a8a0c1dSAlexander Shiyan * GPIO_SYSCON_FEAT_IN: GPIOs supports input, 346a8a0c1dSAlexander Shiyan * GPIO_SYSCON_FEAT_OUT: GPIOs supports output, 356a8a0c1dSAlexander Shiyan * GPIO_SYSCON_FEAT_DIR: GPIOs supports switch direction. 366a8a0c1dSAlexander Shiyan * bit_count: Number of bits used as GPIOs. 376a8a0c1dSAlexander Shiyan * dat_bit_offset: Offset (in bits) to the first GPIO bit. 386a8a0c1dSAlexander Shiyan * dir_bit_offset: Optional offset (in bits) to the first bit to switch 396a8a0c1dSAlexander Shiyan * GPIO direction (Used with GPIO_SYSCON_FEAT_DIR flag). 402c341d62SGrygorii Strashko * set: HW specific callback to assigns output value 412c341d62SGrygorii Strashko * for signal "offset" 426a8a0c1dSAlexander Shiyan */ 436a8a0c1dSAlexander Shiyan 446a8a0c1dSAlexander Shiyan struct syscon_gpio_data { 456a8a0c1dSAlexander Shiyan const char *compatible; 466a8a0c1dSAlexander Shiyan unsigned int flags; 476a8a0c1dSAlexander Shiyan unsigned int bit_count; 486a8a0c1dSAlexander Shiyan unsigned int dat_bit_offset; 496a8a0c1dSAlexander Shiyan unsigned int dir_bit_offset; 502c341d62SGrygorii Strashko void (*set)(struct gpio_chip *chip, 512c341d62SGrygorii Strashko unsigned offset, int value); 526a8a0c1dSAlexander Shiyan }; 536a8a0c1dSAlexander Shiyan 546a8a0c1dSAlexander Shiyan struct syscon_gpio_priv { 556a8a0c1dSAlexander Shiyan struct gpio_chip chip; 566a8a0c1dSAlexander Shiyan struct regmap *syscon; 576a8a0c1dSAlexander Shiyan const struct syscon_gpio_data *data; 585a3e3f88SGrygorii Strashko u32 dreg_offset; 595a3e3f88SGrygorii Strashko u32 dir_reg_offset; 606a8a0c1dSAlexander Shiyan }; 616a8a0c1dSAlexander Shiyan 626a8a0c1dSAlexander Shiyan static inline struct syscon_gpio_priv *to_syscon_gpio(struct gpio_chip *chip) 636a8a0c1dSAlexander Shiyan { 646a8a0c1dSAlexander Shiyan return container_of(chip, struct syscon_gpio_priv, chip); 656a8a0c1dSAlexander Shiyan } 666a8a0c1dSAlexander Shiyan 676a8a0c1dSAlexander Shiyan static int syscon_gpio_get(struct gpio_chip *chip, unsigned offset) 686a8a0c1dSAlexander Shiyan { 696a8a0c1dSAlexander Shiyan struct syscon_gpio_priv *priv = to_syscon_gpio(chip); 705a3e3f88SGrygorii Strashko unsigned int val, offs; 716a8a0c1dSAlexander Shiyan int ret; 726a8a0c1dSAlexander Shiyan 735a3e3f88SGrygorii Strashko offs = priv->dreg_offset + priv->data->dat_bit_offset + offset; 745a3e3f88SGrygorii Strashko 756a8a0c1dSAlexander Shiyan ret = regmap_read(priv->syscon, 766a8a0c1dSAlexander Shiyan (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, &val); 776a8a0c1dSAlexander Shiyan if (ret) 786a8a0c1dSAlexander Shiyan return ret; 796a8a0c1dSAlexander Shiyan 806a8a0c1dSAlexander Shiyan return !!(val & BIT(offs % SYSCON_REG_BITS)); 816a8a0c1dSAlexander Shiyan } 826a8a0c1dSAlexander Shiyan 836a8a0c1dSAlexander Shiyan static void syscon_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 846a8a0c1dSAlexander Shiyan { 856a8a0c1dSAlexander Shiyan struct syscon_gpio_priv *priv = to_syscon_gpio(chip); 865a3e3f88SGrygorii Strashko unsigned int offs; 875a3e3f88SGrygorii Strashko 885a3e3f88SGrygorii Strashko offs = priv->dreg_offset + priv->data->dat_bit_offset + offset; 896a8a0c1dSAlexander Shiyan 906a8a0c1dSAlexander Shiyan regmap_update_bits(priv->syscon, 916a8a0c1dSAlexander Shiyan (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, 926a8a0c1dSAlexander Shiyan BIT(offs % SYSCON_REG_BITS), 936a8a0c1dSAlexander Shiyan val ? BIT(offs % SYSCON_REG_BITS) : 0); 946a8a0c1dSAlexander Shiyan } 956a8a0c1dSAlexander Shiyan 966a8a0c1dSAlexander Shiyan static int syscon_gpio_dir_in(struct gpio_chip *chip, unsigned offset) 976a8a0c1dSAlexander Shiyan { 986a8a0c1dSAlexander Shiyan struct syscon_gpio_priv *priv = to_syscon_gpio(chip); 996a8a0c1dSAlexander Shiyan 1006a8a0c1dSAlexander Shiyan if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) { 1015a3e3f88SGrygorii Strashko unsigned int offs; 1025a3e3f88SGrygorii Strashko 1035a3e3f88SGrygorii Strashko offs = priv->dir_reg_offset + 1045a3e3f88SGrygorii Strashko priv->data->dir_bit_offset + offset; 1056a8a0c1dSAlexander Shiyan 1066a8a0c1dSAlexander Shiyan regmap_update_bits(priv->syscon, 1076a8a0c1dSAlexander Shiyan (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, 1086a8a0c1dSAlexander Shiyan BIT(offs % SYSCON_REG_BITS), 0); 1096a8a0c1dSAlexander Shiyan } 1106a8a0c1dSAlexander Shiyan 1116a8a0c1dSAlexander Shiyan return 0; 1126a8a0c1dSAlexander Shiyan } 1136a8a0c1dSAlexander Shiyan 1146a8a0c1dSAlexander Shiyan static int syscon_gpio_dir_out(struct gpio_chip *chip, unsigned offset, int val) 1156a8a0c1dSAlexander Shiyan { 1166a8a0c1dSAlexander Shiyan struct syscon_gpio_priv *priv = to_syscon_gpio(chip); 1176a8a0c1dSAlexander Shiyan 1186a8a0c1dSAlexander Shiyan if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) { 1195a3e3f88SGrygorii Strashko unsigned int offs; 1205a3e3f88SGrygorii Strashko 1215a3e3f88SGrygorii Strashko offs = priv->dir_reg_offset + 1225a3e3f88SGrygorii Strashko priv->data->dir_bit_offset + offset; 1236a8a0c1dSAlexander Shiyan 1246a8a0c1dSAlexander Shiyan regmap_update_bits(priv->syscon, 1256a8a0c1dSAlexander Shiyan (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, 1266a8a0c1dSAlexander Shiyan BIT(offs % SYSCON_REG_BITS), 1276a8a0c1dSAlexander Shiyan BIT(offs % SYSCON_REG_BITS)); 1286a8a0c1dSAlexander Shiyan } 1296a8a0c1dSAlexander Shiyan 1302c341d62SGrygorii Strashko priv->data->set(chip, offset, val); 1316a8a0c1dSAlexander Shiyan 1326a8a0c1dSAlexander Shiyan return 0; 1336a8a0c1dSAlexander Shiyan } 1346a8a0c1dSAlexander Shiyan 1356a8a0c1dSAlexander Shiyan static const struct syscon_gpio_data clps711x_mctrl_gpio = { 1366a8a0c1dSAlexander Shiyan /* ARM CLPS711X SYSFLG1 Bits 8-10 */ 1376a8a0c1dSAlexander Shiyan .compatible = "cirrus,clps711x-syscon1", 1386a8a0c1dSAlexander Shiyan .flags = GPIO_SYSCON_FEAT_IN, 1396a8a0c1dSAlexander Shiyan .bit_count = 3, 1406a8a0c1dSAlexander Shiyan .dat_bit_offset = 0x40 * 8 + 8, 1416a8a0c1dSAlexander Shiyan }; 1426a8a0c1dSAlexander Shiyan 1432134cb99SGrygorii Strashko #define KEYSTONE_LOCK_BIT BIT(0) 1442134cb99SGrygorii Strashko 1452134cb99SGrygorii Strashko static void keystone_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 1462134cb99SGrygorii Strashko { 1472134cb99SGrygorii Strashko struct syscon_gpio_priv *priv = to_syscon_gpio(chip); 1482134cb99SGrygorii Strashko unsigned int offs; 1492134cb99SGrygorii Strashko int ret; 1502134cb99SGrygorii Strashko 1512134cb99SGrygorii Strashko offs = priv->dreg_offset + priv->data->dat_bit_offset + offset; 1522134cb99SGrygorii Strashko 1532134cb99SGrygorii Strashko if (!val) 1542134cb99SGrygorii Strashko return; 1552134cb99SGrygorii Strashko 1562134cb99SGrygorii Strashko ret = regmap_update_bits( 1572134cb99SGrygorii Strashko priv->syscon, 1582134cb99SGrygorii Strashko (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, 1592134cb99SGrygorii Strashko BIT(offs % SYSCON_REG_BITS) | KEYSTONE_LOCK_BIT, 1602134cb99SGrygorii Strashko BIT(offs % SYSCON_REG_BITS) | KEYSTONE_LOCK_BIT); 1612134cb99SGrygorii Strashko if (ret < 0) 1622134cb99SGrygorii Strashko dev_err(chip->dev, "gpio write failed ret(%d)\n", ret); 1632134cb99SGrygorii Strashko } 1642134cb99SGrygorii Strashko 1652134cb99SGrygorii Strashko static const struct syscon_gpio_data keystone_dsp_gpio = { 1662134cb99SGrygorii Strashko /* ARM Keystone 2 */ 1672134cb99SGrygorii Strashko .compatible = NULL, 1682134cb99SGrygorii Strashko .flags = GPIO_SYSCON_FEAT_OUT, 1692134cb99SGrygorii Strashko .bit_count = 28, 1702134cb99SGrygorii Strashko .dat_bit_offset = 4, 1712134cb99SGrygorii Strashko .set = keystone_gpio_set, 1722134cb99SGrygorii Strashko }; 1732134cb99SGrygorii Strashko 1746a8a0c1dSAlexander Shiyan static const struct of_device_id syscon_gpio_ids[] = { 1756a8a0c1dSAlexander Shiyan { 1766a8a0c1dSAlexander Shiyan .compatible = "cirrus,clps711x-mctrl-gpio", 1776a8a0c1dSAlexander Shiyan .data = &clps711x_mctrl_gpio, 1786a8a0c1dSAlexander Shiyan }, 1792134cb99SGrygorii Strashko { 1802134cb99SGrygorii Strashko .compatible = "ti,keystone-dsp-gpio", 1812134cb99SGrygorii Strashko .data = &keystone_dsp_gpio, 1822134cb99SGrygorii Strashko }, 1836a8a0c1dSAlexander Shiyan { } 1846a8a0c1dSAlexander Shiyan }; 1856a8a0c1dSAlexander Shiyan MODULE_DEVICE_TABLE(of, syscon_gpio_ids); 1866a8a0c1dSAlexander Shiyan 1876a8a0c1dSAlexander Shiyan static int syscon_gpio_probe(struct platform_device *pdev) 1886a8a0c1dSAlexander Shiyan { 1896a8a0c1dSAlexander Shiyan struct device *dev = &pdev->dev; 1906a8a0c1dSAlexander Shiyan const struct of_device_id *of_id = of_match_device(syscon_gpio_ids, dev); 1916a8a0c1dSAlexander Shiyan struct syscon_gpio_priv *priv; 1925a3e3f88SGrygorii Strashko struct device_node *np = dev->of_node; 1935a3e3f88SGrygorii Strashko int ret; 1946a8a0c1dSAlexander Shiyan 1956a8a0c1dSAlexander Shiyan priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1966a8a0c1dSAlexander Shiyan if (!priv) 1976a8a0c1dSAlexander Shiyan return -ENOMEM; 1986a8a0c1dSAlexander Shiyan 1996a8a0c1dSAlexander Shiyan priv->data = of_id->data; 2006a8a0c1dSAlexander Shiyan 2015a3e3f88SGrygorii Strashko if (priv->data->compatible) { 2025a3e3f88SGrygorii Strashko priv->syscon = syscon_regmap_lookup_by_compatible( 2035a3e3f88SGrygorii Strashko priv->data->compatible); 2046a8a0c1dSAlexander Shiyan if (IS_ERR(priv->syscon)) 2056a8a0c1dSAlexander Shiyan return PTR_ERR(priv->syscon); 2065a3e3f88SGrygorii Strashko } else { 2075a3e3f88SGrygorii Strashko priv->syscon = 2085a3e3f88SGrygorii Strashko syscon_regmap_lookup_by_phandle(np, "gpio,syscon-dev"); 2095a3e3f88SGrygorii Strashko if (IS_ERR(priv->syscon)) 2105a3e3f88SGrygorii Strashko return PTR_ERR(priv->syscon); 2115a3e3f88SGrygorii Strashko 2125a3e3f88SGrygorii Strashko ret = of_property_read_u32_index(np, "gpio,syscon-dev", 1, 2135a3e3f88SGrygorii Strashko &priv->dreg_offset); 2145a3e3f88SGrygorii Strashko if (ret) 2155a3e3f88SGrygorii Strashko dev_err(dev, "can't read the data register offset!\n"); 2165a3e3f88SGrygorii Strashko 2175a3e3f88SGrygorii Strashko priv->dreg_offset <<= 3; 2185a3e3f88SGrygorii Strashko 2195a3e3f88SGrygorii Strashko ret = of_property_read_u32_index(np, "gpio,syscon-dev", 2, 2205a3e3f88SGrygorii Strashko &priv->dir_reg_offset); 2215a3e3f88SGrygorii Strashko if (ret) 2225a3e3f88SGrygorii Strashko dev_err(dev, "can't read the dir register offset!\n"); 2235a3e3f88SGrygorii Strashko 2245a3e3f88SGrygorii Strashko priv->dir_reg_offset <<= 3; 2255a3e3f88SGrygorii Strashko } 2266a8a0c1dSAlexander Shiyan 2276a8a0c1dSAlexander Shiyan priv->chip.dev = dev; 2286a8a0c1dSAlexander Shiyan priv->chip.owner = THIS_MODULE; 2296a8a0c1dSAlexander Shiyan priv->chip.label = dev_name(dev); 2306a8a0c1dSAlexander Shiyan priv->chip.base = -1; 2316a8a0c1dSAlexander Shiyan priv->chip.ngpio = priv->data->bit_count; 2326a8a0c1dSAlexander Shiyan priv->chip.get = syscon_gpio_get; 2336a8a0c1dSAlexander Shiyan if (priv->data->flags & GPIO_SYSCON_FEAT_IN) 2346a8a0c1dSAlexander Shiyan priv->chip.direction_input = syscon_gpio_dir_in; 2356a8a0c1dSAlexander Shiyan if (priv->data->flags & GPIO_SYSCON_FEAT_OUT) { 2362c341d62SGrygorii Strashko priv->chip.set = priv->data->set ? : syscon_gpio_set; 2376a8a0c1dSAlexander Shiyan priv->chip.direction_output = syscon_gpio_dir_out; 2386a8a0c1dSAlexander Shiyan } 2396a8a0c1dSAlexander Shiyan 2406a8a0c1dSAlexander Shiyan platform_set_drvdata(pdev, priv); 2416a8a0c1dSAlexander Shiyan 2426a8a0c1dSAlexander Shiyan return gpiochip_add(&priv->chip); 2436a8a0c1dSAlexander Shiyan } 2446a8a0c1dSAlexander Shiyan 2456a8a0c1dSAlexander Shiyan static int syscon_gpio_remove(struct platform_device *pdev) 2466a8a0c1dSAlexander Shiyan { 2476a8a0c1dSAlexander Shiyan struct syscon_gpio_priv *priv = platform_get_drvdata(pdev); 2486a8a0c1dSAlexander Shiyan 2499f5132aeSabdoulaye berthe gpiochip_remove(&priv->chip); 2509f5132aeSabdoulaye berthe return 0; 2516a8a0c1dSAlexander Shiyan } 2526a8a0c1dSAlexander Shiyan 2536a8a0c1dSAlexander Shiyan static struct platform_driver syscon_gpio_driver = { 2546a8a0c1dSAlexander Shiyan .driver = { 2556a8a0c1dSAlexander Shiyan .name = "gpio-syscon", 2566a8a0c1dSAlexander Shiyan .owner = THIS_MODULE, 2576a8a0c1dSAlexander Shiyan .of_match_table = syscon_gpio_ids, 2586a8a0c1dSAlexander Shiyan }, 2596a8a0c1dSAlexander Shiyan .probe = syscon_gpio_probe, 2606a8a0c1dSAlexander Shiyan .remove = syscon_gpio_remove, 2616a8a0c1dSAlexander Shiyan }; 2626a8a0c1dSAlexander Shiyan module_platform_driver(syscon_gpio_driver); 2636a8a0c1dSAlexander Shiyan 2646a8a0c1dSAlexander Shiyan MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 2656a8a0c1dSAlexander Shiyan MODULE_DESCRIPTION("SYSCON GPIO driver"); 2666a8a0c1dSAlexander Shiyan MODULE_LICENSE("GPL"); 267