1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2012 John Crispin <john@phrozen.org> 5 */ 6 7 #include <linux/slab.h> 8 #include <linux/init.h> 9 #include <linux/module.h> 10 #include <linux/types.h> 11 #include <linux/of_platform.h> 12 #include <linux/mutex.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/io.h> 15 #include <linux/clk.h> 16 #include <linux/err.h> 17 18 /* 19 * The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a 20 * peripheral controller used to drive external shift register cascades. At most 21 * 3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem 22 * to drive the 2 LSBs of the cascade automatically. 23 */ 24 25 /* control register 0 */ 26 #define XWAY_STP_CON0 0x00 27 /* control register 1 */ 28 #define XWAY_STP_CON1 0x04 29 /* data register 0 */ 30 #define XWAY_STP_CPU0 0x08 31 /* data register 1 */ 32 #define XWAY_STP_CPU1 0x0C 33 /* access register */ 34 #define XWAY_STP_AR 0x10 35 36 /* software or hardware update select bit */ 37 #define XWAY_STP_CON_SWU BIT(31) 38 39 /* automatic update rates */ 40 #define XWAY_STP_2HZ 0 41 #define XWAY_STP_4HZ BIT(23) 42 #define XWAY_STP_8HZ BIT(24) 43 #define XWAY_STP_10HZ (BIT(24) | BIT(23)) 44 #define XWAY_STP_SPEED_MASK (0xf << 23) 45 46 /* clock source for automatic update */ 47 #define XWAY_STP_UPD_FPI BIT(31) 48 #define XWAY_STP_UPD_MASK (BIT(31) | BIT(30)) 49 50 /* let the adsl core drive the 2 LSBs */ 51 #define XWAY_STP_ADSL_SHIFT 24 52 #define XWAY_STP_ADSL_MASK 0x3 53 54 /* 2 groups of 3 bits can be driven by the phys */ 55 #define XWAY_STP_PHY_MASK 0x7 56 #define XWAY_STP_PHY1_SHIFT 27 57 #define XWAY_STP_PHY2_SHIFT 15 58 59 /* STP has 3 groups of 8 bits */ 60 #define XWAY_STP_GROUP0 BIT(0) 61 #define XWAY_STP_GROUP1 BIT(1) 62 #define XWAY_STP_GROUP2 BIT(2) 63 #define XWAY_STP_GROUP_MASK (0x7) 64 65 /* Edge configuration bits */ 66 #define XWAY_STP_FALLING BIT(26) 67 #define XWAY_STP_EDGE_MASK BIT(26) 68 69 #define xway_stp_r32(m, reg) __raw_readl(m + reg) 70 #define xway_stp_w32(m, val, reg) __raw_writel(val, m + reg) 71 #define xway_stp_w32_mask(m, clear, set, reg) \ 72 xway_stp_w32(m, (xway_stp_r32(m, reg) & ~(clear)) | (set), reg) 73 74 struct xway_stp { 75 struct gpio_chip gc; 76 void __iomem *virt; 77 u32 edge; /* rising or falling edge triggered shift register */ 78 u32 shadow; /* shadow the shift registers state */ 79 u8 groups; /* we can drive 1-3 groups of 8bit each */ 80 u8 dsl; /* the 2 LSBs can be driven by the dsl core */ 81 u8 phy1; /* 3 bits can be driven by phy1 */ 82 u8 phy2; /* 3 bits can be driven by phy2 */ 83 u8 reserved; /* mask out the hw driven bits in gpio_request */ 84 }; 85 86 /** 87 * xway_stp_get() - gpio_chip->get - get gpios. 88 * @gc: Pointer to gpio_chip device structure. 89 * @gpio: GPIO signal number. 90 * 91 * Gets the shadow value. 92 */ 93 static int xway_stp_get(struct gpio_chip *gc, unsigned int gpio) 94 { 95 struct xway_stp *chip = gpiochip_get_data(gc); 96 97 return (xway_stp_r32(chip->virt, XWAY_STP_CPU0) & BIT(gpio)); 98 } 99 100 /** 101 * xway_stp_set() - gpio_chip->set - set gpios. 102 * @gc: Pointer to gpio_chip device structure. 103 * @gpio: GPIO signal number. 104 * @val: Value to be written to specified signal. 105 * 106 * Set the shadow value and call ltq_ebu_apply. 107 */ 108 static void xway_stp_set(struct gpio_chip *gc, unsigned gpio, int val) 109 { 110 struct xway_stp *chip = gpiochip_get_data(gc); 111 112 if (val) 113 chip->shadow |= BIT(gpio); 114 else 115 chip->shadow &= ~BIT(gpio); 116 xway_stp_w32(chip->virt, chip->shadow, XWAY_STP_CPU0); 117 xway_stp_w32_mask(chip->virt, 0, XWAY_STP_CON_SWU, XWAY_STP_CON0); 118 } 119 120 /** 121 * xway_stp_dir_out() - gpio_chip->dir_out - set gpio direction. 122 * @gc: Pointer to gpio_chip device structure. 123 * @gpio: GPIO signal number. 124 * @val: Value to be written to specified signal. 125 * 126 * Same as xway_stp_set, always returns 0. 127 */ 128 static int xway_stp_dir_out(struct gpio_chip *gc, unsigned gpio, int val) 129 { 130 xway_stp_set(gc, gpio, val); 131 132 return 0; 133 } 134 135 /** 136 * xway_stp_request() - gpio_chip->request 137 * @gc: Pointer to gpio_chip device structure. 138 * @gpio: GPIO signal number. 139 * 140 * We mask out the HW driven pins 141 */ 142 static int xway_stp_request(struct gpio_chip *gc, unsigned gpio) 143 { 144 struct xway_stp *chip = gpiochip_get_data(gc); 145 146 if ((gpio < 8) && (chip->reserved & BIT(gpio))) { 147 dev_err(gc->parent, "GPIO %d is driven by hardware\n", gpio); 148 return -ENODEV; 149 } 150 151 return 0; 152 } 153 154 /** 155 * xway_stp_hw_init() - Configure the STP unit and enable the clock gate 156 * @chip: Pointer to the xway_stp chip structure 157 */ 158 static void xway_stp_hw_init(struct xway_stp *chip) 159 { 160 /* sane defaults */ 161 xway_stp_w32(chip->virt, 0, XWAY_STP_AR); 162 xway_stp_w32(chip->virt, 0, XWAY_STP_CPU0); 163 xway_stp_w32(chip->virt, 0, XWAY_STP_CPU1); 164 xway_stp_w32(chip->virt, XWAY_STP_CON_SWU, XWAY_STP_CON0); 165 xway_stp_w32(chip->virt, 0, XWAY_STP_CON1); 166 167 /* apply edge trigger settings for the shift register */ 168 xway_stp_w32_mask(chip->virt, XWAY_STP_EDGE_MASK, 169 chip->edge, XWAY_STP_CON0); 170 171 /* apply led group settings */ 172 xway_stp_w32_mask(chip->virt, XWAY_STP_GROUP_MASK, 173 chip->groups, XWAY_STP_CON1); 174 175 /* tell the hardware which pins are controlled by the dsl modem */ 176 xway_stp_w32_mask(chip->virt, 177 XWAY_STP_ADSL_MASK << XWAY_STP_ADSL_SHIFT, 178 chip->dsl << XWAY_STP_ADSL_SHIFT, 179 XWAY_STP_CON0); 180 181 /* tell the hardware which pins are controlled by the phys */ 182 xway_stp_w32_mask(chip->virt, 183 XWAY_STP_PHY_MASK << XWAY_STP_PHY1_SHIFT, 184 chip->phy1 << XWAY_STP_PHY1_SHIFT, 185 XWAY_STP_CON0); 186 xway_stp_w32_mask(chip->virt, 187 XWAY_STP_PHY_MASK << XWAY_STP_PHY2_SHIFT, 188 chip->phy2 << XWAY_STP_PHY2_SHIFT, 189 XWAY_STP_CON1); 190 191 /* mask out the hw driven bits in gpio_request */ 192 chip->reserved = (chip->phy2 << 5) | (chip->phy1 << 2) | chip->dsl; 193 194 /* 195 * if we have pins that are driven by hw, we need to tell the stp what 196 * clock to use as a timer. 197 */ 198 if (chip->reserved) 199 xway_stp_w32_mask(chip->virt, XWAY_STP_UPD_MASK, 200 XWAY_STP_UPD_FPI, XWAY_STP_CON1); 201 } 202 203 static int xway_stp_probe(struct platform_device *pdev) 204 { 205 u32 shadow, groups, dsl, phy; 206 struct xway_stp *chip; 207 struct clk *clk; 208 int ret = 0; 209 210 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 211 if (!chip) 212 return -ENOMEM; 213 214 chip->virt = devm_platform_ioremap_resource(pdev, 0); 215 if (IS_ERR(chip->virt)) 216 return PTR_ERR(chip->virt); 217 218 chip->gc.parent = &pdev->dev; 219 chip->gc.label = "stp-xway"; 220 chip->gc.direction_output = xway_stp_dir_out; 221 chip->gc.get = xway_stp_get; 222 chip->gc.set = xway_stp_set; 223 chip->gc.request = xway_stp_request; 224 chip->gc.base = -1; 225 chip->gc.owner = THIS_MODULE; 226 227 /* store the shadow value if one was passed by the devicetree */ 228 if (!of_property_read_u32(pdev->dev.of_node, "lantiq,shadow", &shadow)) 229 chip->shadow = shadow; 230 231 /* find out which gpio groups should be enabled */ 232 if (!of_property_read_u32(pdev->dev.of_node, "lantiq,groups", &groups)) 233 chip->groups = groups & XWAY_STP_GROUP_MASK; 234 else 235 chip->groups = XWAY_STP_GROUP0; 236 chip->gc.ngpio = fls(chip->groups) * 8; 237 238 /* find out which gpios are controlled by the dsl core */ 239 if (!of_property_read_u32(pdev->dev.of_node, "lantiq,dsl", &dsl)) 240 chip->dsl = dsl & XWAY_STP_ADSL_MASK; 241 242 /* find out which gpios are controlled by the phys */ 243 if (of_machine_is_compatible("lantiq,ar9") || 244 of_machine_is_compatible("lantiq,gr9") || 245 of_machine_is_compatible("lantiq,vr9")) { 246 if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy1", &phy)) 247 chip->phy1 = phy & XWAY_STP_PHY_MASK; 248 if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy2", &phy)) 249 chip->phy2 = phy & XWAY_STP_PHY_MASK; 250 } 251 252 /* check which edge trigger we should use, default to a falling edge */ 253 if (!of_find_property(pdev->dev.of_node, "lantiq,rising", NULL)) 254 chip->edge = XWAY_STP_FALLING; 255 256 clk = devm_clk_get(&pdev->dev, NULL); 257 if (IS_ERR(clk)) { 258 dev_err(&pdev->dev, "Failed to get clock\n"); 259 return PTR_ERR(clk); 260 } 261 262 ret = clk_prepare_enable(clk); 263 if (ret) 264 return ret; 265 266 xway_stp_hw_init(chip); 267 268 ret = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip); 269 if (ret) { 270 clk_disable_unprepare(clk); 271 return ret; 272 } 273 274 dev_info(&pdev->dev, "Init done\n"); 275 276 return 0; 277 } 278 279 static const struct of_device_id xway_stp_match[] = { 280 { .compatible = "lantiq,gpio-stp-xway" }, 281 {}, 282 }; 283 MODULE_DEVICE_TABLE(of, xway_stp_match); 284 285 static struct platform_driver xway_stp_driver = { 286 .probe = xway_stp_probe, 287 .driver = { 288 .name = "gpio-stp-xway", 289 .of_match_table = xway_stp_match, 290 }, 291 }; 292 293 static int __init xway_stp_init(void) 294 { 295 return platform_driver_register(&xway_stp_driver); 296 } 297 298 subsys_initcall(xway_stp_init); 299