1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2012 John Crispin <john@phrozen.org> 5 */ 6 7 #include <linux/slab.h> 8 #include <linux/init.h> 9 #include <linux/module.h> 10 #include <linux/types.h> 11 #include <linux/of_platform.h> 12 #include <linux/mutex.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/io.h> 15 #include <linux/clk.h> 16 #include <linux/err.h> 17 18 #include <lantiq_soc.h> 19 20 /* 21 * The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a 22 * peripheral controller used to drive external shift register cascades. At most 23 * 3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem 24 * to drive the 2 LSBs of the cascade automatically. 25 */ 26 27 /* control register 0 */ 28 #define XWAY_STP_CON0 0x00 29 /* control register 1 */ 30 #define XWAY_STP_CON1 0x04 31 /* data register 0 */ 32 #define XWAY_STP_CPU0 0x08 33 /* data register 1 */ 34 #define XWAY_STP_CPU1 0x0C 35 /* access register */ 36 #define XWAY_STP_AR 0x10 37 38 /* software or hardware update select bit */ 39 #define XWAY_STP_CON_SWU BIT(31) 40 41 /* automatic update rates */ 42 #define XWAY_STP_2HZ 0 43 #define XWAY_STP_4HZ BIT(23) 44 #define XWAY_STP_8HZ BIT(24) 45 #define XWAY_STP_10HZ (BIT(24) | BIT(23)) 46 #define XWAY_STP_SPEED_MASK (0xf << 23) 47 48 /* clock source for automatic update */ 49 #define XWAY_STP_UPD_FPI BIT(31) 50 #define XWAY_STP_UPD_MASK (BIT(31) | BIT(30)) 51 52 /* let the adsl core drive the 2 LSBs */ 53 #define XWAY_STP_ADSL_SHIFT 24 54 #define XWAY_STP_ADSL_MASK 0x3 55 56 /* 2 groups of 3 bits can be driven by the phys */ 57 #define XWAY_STP_PHY_MASK 0x7 58 #define XWAY_STP_PHY1_SHIFT 27 59 #define XWAY_STP_PHY2_SHIFT 15 60 61 /* STP has 3 groups of 8 bits */ 62 #define XWAY_STP_GROUP0 BIT(0) 63 #define XWAY_STP_GROUP1 BIT(1) 64 #define XWAY_STP_GROUP2 BIT(2) 65 #define XWAY_STP_GROUP_MASK (0x7) 66 67 /* Edge configuration bits */ 68 #define XWAY_STP_FALLING BIT(26) 69 #define XWAY_STP_EDGE_MASK BIT(26) 70 71 #define xway_stp_r32(m, reg) __raw_readl(m + reg) 72 #define xway_stp_w32(m, val, reg) __raw_writel(val, m + reg) 73 #define xway_stp_w32_mask(m, clear, set, reg) \ 74 ltq_w32((ltq_r32(m + reg) & ~(clear)) | (set), \ 75 m + reg) 76 77 struct xway_stp { 78 struct gpio_chip gc; 79 void __iomem *virt; 80 u32 edge; /* rising or falling edge triggered shift register */ 81 u32 shadow; /* shadow the shift registers state */ 82 u8 groups; /* we can drive 1-3 groups of 8bit each */ 83 u8 dsl; /* the 2 LSBs can be driven by the dsl core */ 84 u8 phy1; /* 3 bits can be driven by phy1 */ 85 u8 phy2; /* 3 bits can be driven by phy2 */ 86 u8 reserved; /* mask out the hw driven bits in gpio_request */ 87 }; 88 89 /** 90 * xway_stp_get() - gpio_chip->get - get gpios. 91 * @gc: Pointer to gpio_chip device structure. 92 * @gpio: GPIO signal number. 93 * 94 * Gets the shadow value. 95 */ 96 static int xway_stp_get(struct gpio_chip *gc, unsigned int gpio) 97 { 98 struct xway_stp *chip = gpiochip_get_data(gc); 99 100 return (xway_stp_r32(chip->virt, XWAY_STP_CPU0) & BIT(gpio)); 101 } 102 103 /** 104 * xway_stp_set() - gpio_chip->set - set gpios. 105 * @gc: Pointer to gpio_chip device structure. 106 * @gpio: GPIO signal number. 107 * @val: Value to be written to specified signal. 108 * 109 * Set the shadow value and call ltq_ebu_apply. 110 */ 111 static void xway_stp_set(struct gpio_chip *gc, unsigned gpio, int val) 112 { 113 struct xway_stp *chip = gpiochip_get_data(gc); 114 115 if (val) 116 chip->shadow |= BIT(gpio); 117 else 118 chip->shadow &= ~BIT(gpio); 119 xway_stp_w32(chip->virt, chip->shadow, XWAY_STP_CPU0); 120 xway_stp_w32_mask(chip->virt, 0, XWAY_STP_CON_SWU, XWAY_STP_CON0); 121 } 122 123 /** 124 * xway_stp_dir_out() - gpio_chip->dir_out - set gpio direction. 125 * @gc: Pointer to gpio_chip device structure. 126 * @gpio: GPIO signal number. 127 * @val: Value to be written to specified signal. 128 * 129 * Same as xway_stp_set, always returns 0. 130 */ 131 static int xway_stp_dir_out(struct gpio_chip *gc, unsigned gpio, int val) 132 { 133 xway_stp_set(gc, gpio, val); 134 135 return 0; 136 } 137 138 /** 139 * xway_stp_request() - gpio_chip->request 140 * @gc: Pointer to gpio_chip device structure. 141 * @gpio: GPIO signal number. 142 * 143 * We mask out the HW driven pins 144 */ 145 static int xway_stp_request(struct gpio_chip *gc, unsigned gpio) 146 { 147 struct xway_stp *chip = gpiochip_get_data(gc); 148 149 if ((gpio < 8) && (chip->reserved & BIT(gpio))) { 150 dev_err(gc->parent, "GPIO %d is driven by hardware\n", gpio); 151 return -ENODEV; 152 } 153 154 return 0; 155 } 156 157 /** 158 * xway_stp_hw_init() - Configure the STP unit and enable the clock gate 159 * @virt: pointer to the remapped register range 160 */ 161 static int xway_stp_hw_init(struct xway_stp *chip) 162 { 163 /* sane defaults */ 164 xway_stp_w32(chip->virt, 0, XWAY_STP_AR); 165 xway_stp_w32(chip->virt, 0, XWAY_STP_CPU0); 166 xway_stp_w32(chip->virt, 0, XWAY_STP_CPU1); 167 xway_stp_w32(chip->virt, XWAY_STP_CON_SWU, XWAY_STP_CON0); 168 xway_stp_w32(chip->virt, 0, XWAY_STP_CON1); 169 170 /* apply edge trigger settings for the shift register */ 171 xway_stp_w32_mask(chip->virt, XWAY_STP_EDGE_MASK, 172 chip->edge, XWAY_STP_CON0); 173 174 /* apply led group settings */ 175 xway_stp_w32_mask(chip->virt, XWAY_STP_GROUP_MASK, 176 chip->groups, XWAY_STP_CON1); 177 178 /* tell the hardware which pins are controlled by the dsl modem */ 179 xway_stp_w32_mask(chip->virt, 180 XWAY_STP_ADSL_MASK << XWAY_STP_ADSL_SHIFT, 181 chip->dsl << XWAY_STP_ADSL_SHIFT, 182 XWAY_STP_CON0); 183 184 /* tell the hardware which pins are controlled by the phys */ 185 xway_stp_w32_mask(chip->virt, 186 XWAY_STP_PHY_MASK << XWAY_STP_PHY1_SHIFT, 187 chip->phy1 << XWAY_STP_PHY1_SHIFT, 188 XWAY_STP_CON0); 189 xway_stp_w32_mask(chip->virt, 190 XWAY_STP_PHY_MASK << XWAY_STP_PHY2_SHIFT, 191 chip->phy2 << XWAY_STP_PHY2_SHIFT, 192 XWAY_STP_CON1); 193 194 /* mask out the hw driven bits in gpio_request */ 195 chip->reserved = (chip->phy2 << 5) | (chip->phy1 << 2) | chip->dsl; 196 197 /* 198 * if we have pins that are driven by hw, we need to tell the stp what 199 * clock to use as a timer. 200 */ 201 if (chip->reserved) 202 xway_stp_w32_mask(chip->virt, XWAY_STP_UPD_MASK, 203 XWAY_STP_UPD_FPI, XWAY_STP_CON1); 204 205 return 0; 206 } 207 208 static int xway_stp_probe(struct platform_device *pdev) 209 { 210 u32 shadow, groups, dsl, phy; 211 struct xway_stp *chip; 212 struct clk *clk; 213 int ret = 0; 214 215 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 216 if (!chip) 217 return -ENOMEM; 218 219 chip->virt = devm_platform_ioremap_resource(pdev, 0); 220 if (IS_ERR(chip->virt)) 221 return PTR_ERR(chip->virt); 222 223 chip->gc.parent = &pdev->dev; 224 chip->gc.label = "stp-xway"; 225 chip->gc.direction_output = xway_stp_dir_out; 226 chip->gc.get = xway_stp_get; 227 chip->gc.set = xway_stp_set; 228 chip->gc.request = xway_stp_request; 229 chip->gc.base = -1; 230 chip->gc.owner = THIS_MODULE; 231 232 /* store the shadow value if one was passed by the devicetree */ 233 if (!of_property_read_u32(pdev->dev.of_node, "lantiq,shadow", &shadow)) 234 chip->shadow = shadow; 235 236 /* find out which gpio groups should be enabled */ 237 if (!of_property_read_u32(pdev->dev.of_node, "lantiq,groups", &groups)) 238 chip->groups = groups & XWAY_STP_GROUP_MASK; 239 else 240 chip->groups = XWAY_STP_GROUP0; 241 chip->gc.ngpio = fls(chip->groups) * 8; 242 243 /* find out which gpios are controlled by the dsl core */ 244 if (!of_property_read_u32(pdev->dev.of_node, "lantiq,dsl", &dsl)) 245 chip->dsl = dsl & XWAY_STP_ADSL_MASK; 246 247 /* find out which gpios are controlled by the phys */ 248 if (of_machine_is_compatible("lantiq,ar9") || 249 of_machine_is_compatible("lantiq,gr9") || 250 of_machine_is_compatible("lantiq,vr9")) { 251 if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy1", &phy)) 252 chip->phy1 = phy & XWAY_STP_PHY_MASK; 253 if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy2", &phy)) 254 chip->phy2 = phy & XWAY_STP_PHY_MASK; 255 } 256 257 /* check which edge trigger we should use, default to a falling edge */ 258 if (!of_find_property(pdev->dev.of_node, "lantiq,rising", NULL)) 259 chip->edge = XWAY_STP_FALLING; 260 261 clk = clk_get(&pdev->dev, NULL); 262 if (IS_ERR(clk)) { 263 dev_err(&pdev->dev, "Failed to get clock\n"); 264 return PTR_ERR(clk); 265 } 266 clk_enable(clk); 267 268 ret = xway_stp_hw_init(chip); 269 if (!ret) 270 ret = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip); 271 272 if (!ret) 273 dev_info(&pdev->dev, "Init done\n"); 274 275 return ret; 276 } 277 278 static const struct of_device_id xway_stp_match[] = { 279 { .compatible = "lantiq,gpio-stp-xway" }, 280 {}, 281 }; 282 MODULE_DEVICE_TABLE(of, xway_stp_match); 283 284 static struct platform_driver xway_stp_driver = { 285 .probe = xway_stp_probe, 286 .driver = { 287 .name = "gpio-stp-xway", 288 .of_match_table = xway_stp_match, 289 }, 290 }; 291 292 static int __init xway_stp_init(void) 293 { 294 return platform_driver_register(&xway_stp_driver); 295 } 296 297 subsys_initcall(xway_stp_init); 298