1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 *
4 * Copyright (C) 2012 John Crispin <john@phrozen.org>
5 */
6
7 #include <linux/platform_device.h>
8 #include <linux/slab.h>
9 #include <linux/init.h>
10 #include <linux/module.h>
11 #include <linux/types.h>
12 #include <linux/of.h>
13 #include <linux/mutex.h>
14 #include <linux/gpio/driver.h>
15 #include <linux/io.h>
16 #include <linux/clk.h>
17 #include <linux/err.h>
18
19 /*
20 * The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
21 * peripheral controller used to drive external shift register cascades. At most
22 * 3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
23 * to drive the 2 LSBs of the cascade automatically.
24 */
25
26 /* control register 0 */
27 #define XWAY_STP_CON0 0x00
28 /* control register 1 */
29 #define XWAY_STP_CON1 0x04
30 /* data register 0 */
31 #define XWAY_STP_CPU0 0x08
32 /* data register 1 */
33 #define XWAY_STP_CPU1 0x0C
34 /* access register */
35 #define XWAY_STP_AR 0x10
36
37 /* software or hardware update select bit */
38 #define XWAY_STP_CON_SWU BIT(31)
39
40 /* automatic update rates */
41 #define XWAY_STP_2HZ 0
42 #define XWAY_STP_4HZ BIT(23)
43 #define XWAY_STP_8HZ BIT(24)
44 #define XWAY_STP_10HZ (BIT(24) | BIT(23))
45 #define XWAY_STP_SPEED_MASK (BIT(23) | BIT(24) | BIT(25) | BIT(26) | BIT(27))
46
47 #define XWAY_STP_FPIS_VALUE BIT(21)
48 #define XWAY_STP_FPIS_MASK (BIT(20) | BIT(21))
49
50 /* clock source for automatic update */
51 #define XWAY_STP_UPD_FPI BIT(31)
52 #define XWAY_STP_UPD_MASK (BIT(31) | BIT(30))
53
54 /* let the adsl core drive the 2 LSBs */
55 #define XWAY_STP_ADSL_SHIFT 24
56 #define XWAY_STP_ADSL_MASK 0x3
57
58 /* 2 groups of 3 bits can be driven by the phys */
59 #define XWAY_STP_PHY_MASK 0x7
60 #define XWAY_STP_PHY1_SHIFT 27
61 #define XWAY_STP_PHY2_SHIFT 3
62 #define XWAY_STP_PHY3_SHIFT 6
63 #define XWAY_STP_PHY4_SHIFT 15
64
65 /* STP has 3 groups of 8 bits */
66 #define XWAY_STP_GROUP0 BIT(0)
67 #define XWAY_STP_GROUP1 BIT(1)
68 #define XWAY_STP_GROUP2 BIT(2)
69 #define XWAY_STP_GROUP_MASK (0x7)
70
71 /* Edge configuration bits */
72 #define XWAY_STP_FALLING BIT(26)
73 #define XWAY_STP_EDGE_MASK BIT(26)
74
75 #define xway_stp_r32(m, reg) __raw_readl(m + reg)
76 #define xway_stp_w32(m, val, reg) __raw_writel(val, m + reg)
77 #define xway_stp_w32_mask(m, clear, set, reg) \
78 xway_stp_w32(m, (xway_stp_r32(m, reg) & ~(clear)) | (set), reg)
79
80 struct xway_stp {
81 struct gpio_chip gc;
82 void __iomem *virt;
83 u32 edge; /* rising or falling edge triggered shift register */
84 u32 shadow; /* shadow the shift registers state */
85 u8 groups; /* we can drive 1-3 groups of 8bit each */
86 u8 dsl; /* the 2 LSBs can be driven by the dsl core */
87 u8 phy1; /* 3 bits can be driven by phy1 */
88 u8 phy2; /* 3 bits can be driven by phy2 */
89 u8 phy3; /* 3 bits can be driven by phy3 */
90 u8 phy4; /* 3 bits can be driven by phy4 */
91 u8 reserved; /* mask out the hw driven bits in gpio_request */
92 };
93
94 /**
95 * xway_stp_get() - gpio_chip->get - get gpios.
96 * @gc: Pointer to gpio_chip device structure.
97 * @gpio: GPIO signal number.
98 *
99 * Gets the shadow value.
100 */
xway_stp_get(struct gpio_chip * gc,unsigned int gpio)101 static int xway_stp_get(struct gpio_chip *gc, unsigned int gpio)
102 {
103 struct xway_stp *chip = gpiochip_get_data(gc);
104
105 return (xway_stp_r32(chip->virt, XWAY_STP_CPU0) & BIT(gpio));
106 }
107
108 /**
109 * xway_stp_set() - gpio_chip->set - set gpios.
110 * @gc: Pointer to gpio_chip device structure.
111 * @gpio: GPIO signal number.
112 * @val: Value to be written to specified signal.
113 *
114 * Set the shadow value and call ltq_ebu_apply.
115 */
xway_stp_set(struct gpio_chip * gc,unsigned gpio,int val)116 static void xway_stp_set(struct gpio_chip *gc, unsigned gpio, int val)
117 {
118 struct xway_stp *chip = gpiochip_get_data(gc);
119
120 if (val)
121 chip->shadow |= BIT(gpio);
122 else
123 chip->shadow &= ~BIT(gpio);
124 xway_stp_w32(chip->virt, chip->shadow, XWAY_STP_CPU0);
125 if (!chip->reserved)
126 xway_stp_w32_mask(chip->virt, 0, XWAY_STP_CON_SWU, XWAY_STP_CON0);
127 }
128
129 /**
130 * xway_stp_dir_out() - gpio_chip->dir_out - set gpio direction.
131 * @gc: Pointer to gpio_chip device structure.
132 * @gpio: GPIO signal number.
133 * @val: Value to be written to specified signal.
134 *
135 * Same as xway_stp_set, always returns 0.
136 */
xway_stp_dir_out(struct gpio_chip * gc,unsigned gpio,int val)137 static int xway_stp_dir_out(struct gpio_chip *gc, unsigned gpio, int val)
138 {
139 xway_stp_set(gc, gpio, val);
140
141 return 0;
142 }
143
144 /**
145 * xway_stp_request() - gpio_chip->request
146 * @gc: Pointer to gpio_chip device structure.
147 * @gpio: GPIO signal number.
148 *
149 * We mask out the HW driven pins
150 */
xway_stp_request(struct gpio_chip * gc,unsigned gpio)151 static int xway_stp_request(struct gpio_chip *gc, unsigned gpio)
152 {
153 struct xway_stp *chip = gpiochip_get_data(gc);
154
155 if ((gpio < 8) && (chip->reserved & BIT(gpio))) {
156 dev_err(gc->parent, "GPIO %d is driven by hardware\n", gpio);
157 return -ENODEV;
158 }
159
160 return 0;
161 }
162
163 /**
164 * xway_stp_hw_init() - Configure the STP unit and enable the clock gate
165 * @chip: Pointer to the xway_stp chip structure
166 */
xway_stp_hw_init(struct xway_stp * chip)167 static void xway_stp_hw_init(struct xway_stp *chip)
168 {
169 /* sane defaults */
170 xway_stp_w32(chip->virt, 0, XWAY_STP_AR);
171 xway_stp_w32(chip->virt, 0, XWAY_STP_CPU0);
172 xway_stp_w32(chip->virt, 0, XWAY_STP_CPU1);
173 xway_stp_w32(chip->virt, XWAY_STP_CON_SWU, XWAY_STP_CON0);
174 xway_stp_w32(chip->virt, 0, XWAY_STP_CON1);
175
176 /* apply edge trigger settings for the shift register */
177 xway_stp_w32_mask(chip->virt, XWAY_STP_EDGE_MASK,
178 chip->edge, XWAY_STP_CON0);
179
180 /* apply led group settings */
181 xway_stp_w32_mask(chip->virt, XWAY_STP_GROUP_MASK,
182 chip->groups, XWAY_STP_CON1);
183
184 /* tell the hardware which pins are controlled by the dsl modem */
185 xway_stp_w32_mask(chip->virt,
186 XWAY_STP_ADSL_MASK << XWAY_STP_ADSL_SHIFT,
187 chip->dsl << XWAY_STP_ADSL_SHIFT,
188 XWAY_STP_CON0);
189
190 /* tell the hardware which pins are controlled by the phys */
191 xway_stp_w32_mask(chip->virt,
192 XWAY_STP_PHY_MASK << XWAY_STP_PHY1_SHIFT,
193 chip->phy1 << XWAY_STP_PHY1_SHIFT,
194 XWAY_STP_CON0);
195 xway_stp_w32_mask(chip->virt,
196 XWAY_STP_PHY_MASK << XWAY_STP_PHY2_SHIFT,
197 chip->phy2 << XWAY_STP_PHY2_SHIFT,
198 XWAY_STP_CON1);
199
200 if (of_machine_is_compatible("lantiq,grx390")
201 || of_machine_is_compatible("lantiq,ar10")) {
202 xway_stp_w32_mask(chip->virt,
203 XWAY_STP_PHY_MASK << XWAY_STP_PHY3_SHIFT,
204 chip->phy3 << XWAY_STP_PHY3_SHIFT,
205 XWAY_STP_CON1);
206 }
207
208 if (of_machine_is_compatible("lantiq,grx390")) {
209 xway_stp_w32_mask(chip->virt,
210 XWAY_STP_PHY_MASK << XWAY_STP_PHY4_SHIFT,
211 chip->phy4 << XWAY_STP_PHY4_SHIFT,
212 XWAY_STP_CON1);
213 }
214
215 /* mask out the hw driven bits in gpio_request */
216 chip->reserved = (chip->phy4 << 11) | (chip->phy3 << 8) | (chip->phy2 << 5)
217 | (chip->phy1 << 2) | chip->dsl;
218
219 /*
220 * if we have pins that are driven by hw, we need to tell the stp what
221 * clock to use as a timer.
222 */
223 if (chip->reserved) {
224 xway_stp_w32_mask(chip->virt, XWAY_STP_UPD_MASK,
225 XWAY_STP_UPD_FPI, XWAY_STP_CON1);
226 xway_stp_w32_mask(chip->virt, XWAY_STP_SPEED_MASK,
227 XWAY_STP_10HZ, XWAY_STP_CON1);
228 xway_stp_w32_mask(chip->virt, XWAY_STP_FPIS_MASK,
229 XWAY_STP_FPIS_VALUE, XWAY_STP_CON1);
230 }
231 }
232
xway_stp_probe(struct platform_device * pdev)233 static int xway_stp_probe(struct platform_device *pdev)
234 {
235 u32 shadow, groups, dsl, phy;
236 struct xway_stp *chip;
237 struct clk *clk;
238 int ret = 0;
239
240 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
241 if (!chip)
242 return -ENOMEM;
243
244 chip->virt = devm_platform_ioremap_resource(pdev, 0);
245 if (IS_ERR(chip->virt))
246 return PTR_ERR(chip->virt);
247
248 chip->gc.parent = &pdev->dev;
249 chip->gc.label = "stp-xway";
250 chip->gc.direction_output = xway_stp_dir_out;
251 chip->gc.get = xway_stp_get;
252 chip->gc.set = xway_stp_set;
253 chip->gc.request = xway_stp_request;
254 chip->gc.base = -1;
255 chip->gc.owner = THIS_MODULE;
256
257 /* store the shadow value if one was passed by the devicetree */
258 if (!of_property_read_u32(pdev->dev.of_node, "lantiq,shadow", &shadow))
259 chip->shadow = shadow;
260
261 /* find out which gpio groups should be enabled */
262 if (!of_property_read_u32(pdev->dev.of_node, "lantiq,groups", &groups))
263 chip->groups = groups & XWAY_STP_GROUP_MASK;
264 else
265 chip->groups = XWAY_STP_GROUP0;
266 chip->gc.ngpio = fls(chip->groups) * 8;
267
268 /* find out which gpios are controlled by the dsl core */
269 if (!of_property_read_u32(pdev->dev.of_node, "lantiq,dsl", &dsl))
270 chip->dsl = dsl & XWAY_STP_ADSL_MASK;
271
272 /* find out which gpios are controlled by the phys */
273 if (of_machine_is_compatible("lantiq,ar9") ||
274 of_machine_is_compatible("lantiq,gr9") ||
275 of_machine_is_compatible("lantiq,vr9") ||
276 of_machine_is_compatible("lantiq,ar10") ||
277 of_machine_is_compatible("lantiq,grx390")) {
278 if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy1", &phy))
279 chip->phy1 = phy & XWAY_STP_PHY_MASK;
280 if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy2", &phy))
281 chip->phy2 = phy & XWAY_STP_PHY_MASK;
282 }
283
284 if (of_machine_is_compatible("lantiq,ar10") ||
285 of_machine_is_compatible("lantiq,grx390")) {
286 if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy3", &phy))
287 chip->phy3 = phy & XWAY_STP_PHY_MASK;
288 }
289
290 if (of_machine_is_compatible("lantiq,grx390")) {
291 if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy4", &phy))
292 chip->phy4 = phy & XWAY_STP_PHY_MASK;
293 }
294
295 /* check which edge trigger we should use, default to a falling edge */
296 if (!of_property_read_bool(pdev->dev.of_node, "lantiq,rising"))
297 chip->edge = XWAY_STP_FALLING;
298
299 clk = devm_clk_get(&pdev->dev, NULL);
300 if (IS_ERR(clk)) {
301 dev_err(&pdev->dev, "Failed to get clock\n");
302 return PTR_ERR(clk);
303 }
304
305 ret = clk_prepare_enable(clk);
306 if (ret)
307 return ret;
308
309 xway_stp_hw_init(chip);
310
311 ret = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
312 if (ret) {
313 clk_disable_unprepare(clk);
314 return ret;
315 }
316
317 dev_info(&pdev->dev, "Init done\n");
318
319 return 0;
320 }
321
322 static const struct of_device_id xway_stp_match[] = {
323 { .compatible = "lantiq,gpio-stp-xway" },
324 {},
325 };
326 MODULE_DEVICE_TABLE(of, xway_stp_match);
327
328 static struct platform_driver xway_stp_driver = {
329 .probe = xway_stp_probe,
330 .driver = {
331 .name = "gpio-stp-xway",
332 .of_match_table = xway_stp_match,
333 },
334 };
335
xway_stp_init(void)336 static int __init xway_stp_init(void)
337 {
338 return platform_driver_register(&xway_stp_driver);
339 }
340
341 subsys_initcall(xway_stp_init);
342