1 /* 2 * Copyright (C) ST-Ericsson SA 2010 3 * 4 * License Terms: GNU General Public License, version 2 5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson 6 */ 7 8 #include <linux/module.h> 9 #include <linux/init.h> 10 #include <linux/platform_device.h> 11 #include <linux/slab.h> 12 #include <linux/gpio.h> 13 #include <linux/interrupt.h> 14 #include <linux/of.h> 15 #include <linux/mfd/stmpe.h> 16 17 /* 18 * These registers are modified under the irq bus lock and cached to avoid 19 * unnecessary writes in bus_sync_unlock. 20 */ 21 enum { REG_RE, REG_FE, REG_IE }; 22 23 #define CACHE_NR_REGS 3 24 /* No variant has more than 24 GPIOs */ 25 #define CACHE_NR_BANKS (24 / 8) 26 27 struct stmpe_gpio { 28 struct gpio_chip chip; 29 struct stmpe *stmpe; 30 struct device *dev; 31 struct mutex irq_lock; 32 unsigned norequest_mask; 33 /* Caches of interrupt control registers for bus_lock */ 34 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS]; 35 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS]; 36 }; 37 38 static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip) 39 { 40 return container_of(chip, struct stmpe_gpio, chip); 41 } 42 43 static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset) 44 { 45 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); 46 struct stmpe *stmpe = stmpe_gpio->stmpe; 47 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8); 48 u8 mask = 1 << (offset % 8); 49 int ret; 50 51 ret = stmpe_reg_read(stmpe, reg); 52 if (ret < 0) 53 return ret; 54 55 return !!(ret & mask); 56 } 57 58 static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 59 { 60 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); 61 struct stmpe *stmpe = stmpe_gpio->stmpe; 62 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB; 63 u8 reg = stmpe->regs[which] - (offset / 8); 64 u8 mask = 1 << (offset % 8); 65 66 /* 67 * Some variants have single register for gpio set/clear functionality. 68 * For them we need to write 0 to clear and 1 to set. 69 */ 70 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB]) 71 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0); 72 else 73 stmpe_reg_write(stmpe, reg, mask); 74 } 75 76 static int stmpe_gpio_direction_output(struct gpio_chip *chip, 77 unsigned offset, int val) 78 { 79 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); 80 struct stmpe *stmpe = stmpe_gpio->stmpe; 81 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); 82 u8 mask = 1 << (offset % 8); 83 84 stmpe_gpio_set(chip, offset, val); 85 86 return stmpe_set_bits(stmpe, reg, mask, mask); 87 } 88 89 static int stmpe_gpio_direction_input(struct gpio_chip *chip, 90 unsigned offset) 91 { 92 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); 93 struct stmpe *stmpe = stmpe_gpio->stmpe; 94 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); 95 u8 mask = 1 << (offset % 8); 96 97 return stmpe_set_bits(stmpe, reg, mask, 0); 98 } 99 100 static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset) 101 { 102 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); 103 struct stmpe *stmpe = stmpe_gpio->stmpe; 104 105 if (stmpe_gpio->norequest_mask & (1 << offset)) 106 return -EINVAL; 107 108 return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO); 109 } 110 111 static struct gpio_chip template_chip = { 112 .label = "stmpe", 113 .owner = THIS_MODULE, 114 .direction_input = stmpe_gpio_direction_input, 115 .get = stmpe_gpio_get, 116 .direction_output = stmpe_gpio_direction_output, 117 .set = stmpe_gpio_set, 118 .request = stmpe_gpio_request, 119 .can_sleep = true, 120 }; 121 122 static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type) 123 { 124 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 125 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc); 126 int offset = d->hwirq; 127 int regoffset = offset / 8; 128 int mask = 1 << (offset % 8); 129 130 if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH) 131 return -EINVAL; 132 133 /* STMPE801 doesn't have RE and FE registers */ 134 if (stmpe_gpio->stmpe->partnum == STMPE801) 135 return 0; 136 137 if (type == IRQ_TYPE_EDGE_RISING) 138 stmpe_gpio->regs[REG_RE][regoffset] |= mask; 139 else 140 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask; 141 142 if (type == IRQ_TYPE_EDGE_FALLING) 143 stmpe_gpio->regs[REG_FE][regoffset] |= mask; 144 else 145 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask; 146 147 return 0; 148 } 149 150 static void stmpe_gpio_irq_lock(struct irq_data *d) 151 { 152 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 153 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc); 154 155 mutex_lock(&stmpe_gpio->irq_lock); 156 } 157 158 static void stmpe_gpio_irq_sync_unlock(struct irq_data *d) 159 { 160 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 161 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc); 162 struct stmpe *stmpe = stmpe_gpio->stmpe; 163 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); 164 static const u8 regmap[] = { 165 [REG_RE] = STMPE_IDX_GPRER_LSB, 166 [REG_FE] = STMPE_IDX_GPFER_LSB, 167 [REG_IE] = STMPE_IDX_IEGPIOR_LSB, 168 }; 169 int i, j; 170 171 for (i = 0; i < CACHE_NR_REGS; i++) { 172 /* STMPE801 doesn't have RE and FE registers */ 173 if ((stmpe->partnum == STMPE801) && 174 (i != REG_IE)) 175 continue; 176 177 for (j = 0; j < num_banks; j++) { 178 u8 old = stmpe_gpio->oldregs[i][j]; 179 u8 new = stmpe_gpio->regs[i][j]; 180 181 if (new == old) 182 continue; 183 184 stmpe_gpio->oldregs[i][j] = new; 185 stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new); 186 } 187 } 188 189 mutex_unlock(&stmpe_gpio->irq_lock); 190 } 191 192 static void stmpe_gpio_irq_mask(struct irq_data *d) 193 { 194 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 195 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc); 196 int offset = d->hwirq; 197 int regoffset = offset / 8; 198 int mask = 1 << (offset % 8); 199 200 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask; 201 } 202 203 static void stmpe_gpio_irq_unmask(struct irq_data *d) 204 { 205 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 206 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc); 207 int offset = d->hwirq; 208 int regoffset = offset / 8; 209 int mask = 1 << (offset % 8); 210 211 stmpe_gpio->regs[REG_IE][regoffset] |= mask; 212 } 213 214 static struct irq_chip stmpe_gpio_irq_chip = { 215 .name = "stmpe-gpio", 216 .irq_bus_lock = stmpe_gpio_irq_lock, 217 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock, 218 .irq_mask = stmpe_gpio_irq_mask, 219 .irq_unmask = stmpe_gpio_irq_unmask, 220 .irq_set_type = stmpe_gpio_irq_set_type, 221 }; 222 223 static irqreturn_t stmpe_gpio_irq(int irq, void *dev) 224 { 225 struct stmpe_gpio *stmpe_gpio = dev; 226 struct stmpe *stmpe = stmpe_gpio->stmpe; 227 u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB]; 228 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); 229 u8 status[num_banks]; 230 int ret; 231 int i; 232 233 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status); 234 if (ret < 0) 235 return IRQ_NONE; 236 237 for (i = 0; i < num_banks; i++) { 238 int bank = num_banks - i - 1; 239 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank]; 240 unsigned int stat = status[i]; 241 242 stat &= enabled; 243 if (!stat) 244 continue; 245 246 while (stat) { 247 int bit = __ffs(stat); 248 int line = bank * 8 + bit; 249 int child_irq = irq_find_mapping(stmpe_gpio->chip.irqdomain, 250 line); 251 252 handle_nested_irq(child_irq); 253 stat &= ~(1 << bit); 254 } 255 256 stmpe_reg_write(stmpe, statmsbreg + i, status[i]); 257 258 /* Edge detect register is not present on 801 */ 259 if (stmpe->partnum != STMPE801) 260 stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB] 261 + i, status[i]); 262 } 263 264 return IRQ_HANDLED; 265 } 266 267 static int stmpe_gpio_probe(struct platform_device *pdev) 268 { 269 struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent); 270 struct device_node *np = pdev->dev.of_node; 271 struct stmpe_gpio_platform_data *pdata; 272 struct stmpe_gpio *stmpe_gpio; 273 int ret; 274 int irq = 0; 275 276 pdata = stmpe->pdata->gpio; 277 278 irq = platform_get_irq(pdev, 0); 279 280 stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL); 281 if (!stmpe_gpio) 282 return -ENOMEM; 283 284 mutex_init(&stmpe_gpio->irq_lock); 285 286 stmpe_gpio->dev = &pdev->dev; 287 stmpe_gpio->stmpe = stmpe; 288 stmpe_gpio->chip = template_chip; 289 stmpe_gpio->chip.ngpio = stmpe->num_gpios; 290 stmpe_gpio->chip.dev = &pdev->dev; 291 #ifdef CONFIG_OF 292 stmpe_gpio->chip.of_node = np; 293 #endif 294 stmpe_gpio->chip.base = -1; 295 296 if (pdata) 297 stmpe_gpio->norequest_mask = pdata->norequest_mask; 298 else if (np) 299 of_property_read_u32(np, "st,norequest-mask", 300 &stmpe_gpio->norequest_mask); 301 302 if (irq < 0) 303 dev_info(&pdev->dev, 304 "device configured in no-irq mode: " 305 "irqs are not available\n"); 306 307 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO); 308 if (ret) 309 goto out_free; 310 311 if (irq > 0) { 312 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 313 stmpe_gpio_irq, IRQF_ONESHOT, 314 "stmpe-gpio", stmpe_gpio); 315 if (ret) { 316 dev_err(&pdev->dev, "unable to get irq: %d\n", ret); 317 goto out_disable; 318 } 319 ret = gpiochip_irqchip_add(&stmpe_gpio->chip, 320 &stmpe_gpio_irq_chip, 321 0, 322 handle_simple_irq, 323 IRQ_TYPE_NONE); 324 if (ret) { 325 dev_err(&pdev->dev, 326 "could not connect irqchip to gpiochip\n"); 327 return ret; 328 } 329 } 330 331 ret = gpiochip_add(&stmpe_gpio->chip); 332 if (ret) { 333 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); 334 goto out_disable; 335 } 336 337 if (pdata && pdata->setup) 338 pdata->setup(stmpe, stmpe_gpio->chip.base); 339 340 platform_set_drvdata(pdev, stmpe_gpio); 341 342 return 0; 343 344 out_disable: 345 stmpe_disable(stmpe, STMPE_BLOCK_GPIO); 346 out_free: 347 kfree(stmpe_gpio); 348 return ret; 349 } 350 351 static int stmpe_gpio_remove(struct platform_device *pdev) 352 { 353 struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev); 354 struct stmpe *stmpe = stmpe_gpio->stmpe; 355 struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio; 356 357 if (pdata && pdata->remove) 358 pdata->remove(stmpe, stmpe_gpio->chip.base); 359 360 gpiochip_remove(&stmpe_gpio->chip); 361 362 stmpe_disable(stmpe, STMPE_BLOCK_GPIO); 363 364 kfree(stmpe_gpio); 365 366 return 0; 367 } 368 369 static struct platform_driver stmpe_gpio_driver = { 370 .driver.name = "stmpe-gpio", 371 .driver.owner = THIS_MODULE, 372 .probe = stmpe_gpio_probe, 373 .remove = stmpe_gpio_remove, 374 }; 375 376 static int __init stmpe_gpio_init(void) 377 { 378 return platform_driver_register(&stmpe_gpio_driver); 379 } 380 subsys_initcall(stmpe_gpio_init); 381 382 static void __exit stmpe_gpio_exit(void) 383 { 384 platform_driver_unregister(&stmpe_gpio_driver); 385 } 386 module_exit(stmpe_gpio_exit); 387 388 MODULE_LICENSE("GPL v2"); 389 MODULE_DESCRIPTION("STMPExxxx GPIO driver"); 390 MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>"); 391