1 /*
2  * SPEAr platform SPI chipselect abstraction over gpiolib
3  *
4  * Copyright (C) 2012 ST Microelectronics
5  * Shiraz Hashim <shiraz.linux.kernel@gmail.com>
6  *
7  * This file is licensed under the terms of the GNU General Public
8  * License version 2. This program is licensed "as is" without any
9  * warranty of any kind, whether express or implied.
10  */
11 
12 #include <linux/err.h>
13 #include <linux/gpio.h>
14 #include <linux/io.h>
15 #include <linux/init.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/types.h>
19 
20 /* maximum chipselects */
21 #define NUM_OF_GPIO	4
22 
23 /*
24  * Provision is available on some SPEAr SoCs to control ARM PL022 spi cs
25  * through system registers. This register lies outside spi (pl022)
26  * address space into system registers.
27  *
28  * It provides control for spi chip select lines so that any chipselect
29  * (out of 4 possible chipselects in pl022) can be made low to select
30  * the particular slave.
31  */
32 
33 /**
34  * struct spear_spics - represents spi chip select control
35  * @base: base address
36  * @perip_cfg: configuration register
37  * @sw_enable_bit: bit to enable s/w control over chipselects
38  * @cs_value_bit: bit to program high or low chipselect
39  * @cs_enable_mask: mask to select bits required to select chipselect
40  * @cs_enable_shift: bit pos of cs_enable_mask
41  * @use_count: use count of a spi controller cs lines
42  * @last_off: stores last offset caller of set_value()
43  * @chip: gpio_chip abstraction
44  */
45 struct spear_spics {
46 	void __iomem		*base;
47 	u32			perip_cfg;
48 	u32			sw_enable_bit;
49 	u32			cs_value_bit;
50 	u32			cs_enable_mask;
51 	u32			cs_enable_shift;
52 	unsigned long		use_count;
53 	int			last_off;
54 	struct gpio_chip	chip;
55 };
56 
57 /* gpio framework specific routines */
58 static int spics_get_value(struct gpio_chip *chip, unsigned offset)
59 {
60 	return -ENXIO;
61 }
62 
63 static void spics_set_value(struct gpio_chip *chip, unsigned offset, int value)
64 {
65 	struct spear_spics *spics = gpiochip_get_data(chip);
66 	u32 tmp;
67 
68 	/* select chip select from register */
69 	tmp = readl_relaxed(spics->base + spics->perip_cfg);
70 	if (spics->last_off != offset) {
71 		spics->last_off = offset;
72 		tmp &= ~(spics->cs_enable_mask << spics->cs_enable_shift);
73 		tmp |= offset << spics->cs_enable_shift;
74 	}
75 
76 	/* toggle chip select line */
77 	tmp &= ~(0x1 << spics->cs_value_bit);
78 	tmp |= value << spics->cs_value_bit;
79 	writel_relaxed(tmp, spics->base + spics->perip_cfg);
80 }
81 
82 static int spics_direction_input(struct gpio_chip *chip, unsigned offset)
83 {
84 	return -ENXIO;
85 }
86 
87 static int spics_direction_output(struct gpio_chip *chip, unsigned offset,
88 		int value)
89 {
90 	spics_set_value(chip, offset, value);
91 	return 0;
92 }
93 
94 static int spics_request(struct gpio_chip *chip, unsigned offset)
95 {
96 	struct spear_spics *spics = gpiochip_get_data(chip);
97 	u32 tmp;
98 
99 	if (!spics->use_count++) {
100 		tmp = readl_relaxed(spics->base + spics->perip_cfg);
101 		tmp |= 0x1 << spics->sw_enable_bit;
102 		tmp |= 0x1 << spics->cs_value_bit;
103 		writel_relaxed(tmp, spics->base + spics->perip_cfg);
104 	}
105 
106 	return 0;
107 }
108 
109 static void spics_free(struct gpio_chip *chip, unsigned offset)
110 {
111 	struct spear_spics *spics = gpiochip_get_data(chip);
112 	u32 tmp;
113 
114 	if (!--spics->use_count) {
115 		tmp = readl_relaxed(spics->base + spics->perip_cfg);
116 		tmp &= ~(0x1 << spics->sw_enable_bit);
117 		writel_relaxed(tmp, spics->base + spics->perip_cfg);
118 	}
119 }
120 
121 static int spics_gpio_probe(struct platform_device *pdev)
122 {
123 	struct device_node *np = pdev->dev.of_node;
124 	struct spear_spics *spics;
125 	struct resource *res;
126 	int ret;
127 
128 	spics = devm_kzalloc(&pdev->dev, sizeof(*spics), GFP_KERNEL);
129 	if (!spics)
130 		return -ENOMEM;
131 
132 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
133 	spics->base = devm_ioremap_resource(&pdev->dev, res);
134 	if (IS_ERR(spics->base))
135 		return PTR_ERR(spics->base);
136 
137 	if (of_property_read_u32(np, "st-spics,peripcfg-reg",
138 				&spics->perip_cfg))
139 		goto err_dt_data;
140 	if (of_property_read_u32(np, "st-spics,sw-enable-bit",
141 				&spics->sw_enable_bit))
142 		goto err_dt_data;
143 	if (of_property_read_u32(np, "st-spics,cs-value-bit",
144 				&spics->cs_value_bit))
145 		goto err_dt_data;
146 	if (of_property_read_u32(np, "st-spics,cs-enable-mask",
147 				&spics->cs_enable_mask))
148 		goto err_dt_data;
149 	if (of_property_read_u32(np, "st-spics,cs-enable-shift",
150 				&spics->cs_enable_shift))
151 		goto err_dt_data;
152 
153 	platform_set_drvdata(pdev, spics);
154 
155 	spics->chip.ngpio = NUM_OF_GPIO;
156 	spics->chip.base = -1;
157 	spics->chip.request = spics_request;
158 	spics->chip.free = spics_free;
159 	spics->chip.direction_input = spics_direction_input;
160 	spics->chip.direction_output = spics_direction_output;
161 	spics->chip.get = spics_get_value;
162 	spics->chip.set = spics_set_value;
163 	spics->chip.label = dev_name(&pdev->dev);
164 	spics->chip.parent = &pdev->dev;
165 	spics->chip.owner = THIS_MODULE;
166 	spics->last_off = -1;
167 
168 	ret = devm_gpiochip_add_data(&pdev->dev, &spics->chip, spics);
169 	if (ret) {
170 		dev_err(&pdev->dev, "unable to add gpio chip\n");
171 		return ret;
172 	}
173 
174 	dev_info(&pdev->dev, "spear spics registered\n");
175 	return 0;
176 
177 err_dt_data:
178 	dev_err(&pdev->dev, "DT probe failed\n");
179 	return -EINVAL;
180 }
181 
182 static const struct of_device_id spics_gpio_of_match[] = {
183 	{ .compatible = "st,spear-spics-gpio" },
184 	{}
185 };
186 
187 static struct platform_driver spics_gpio_driver = {
188 	.probe = spics_gpio_probe,
189 	.driver = {
190 		.name = "spear-spics-gpio",
191 		.of_match_table = spics_gpio_of_match,
192 	},
193 };
194 
195 static int __init spics_gpio_init(void)
196 {
197 	return platform_driver_register(&spics_gpio_driver);
198 }
199 subsys_initcall(spics_gpio_init);
200