1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * GPIO interface for Intel Poulsbo SCH 4 * 5 * Copyright (c) 2010 CompuLab Ltd 6 * Author: Denis Turischev <denis@compulab.co.il> 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/errno.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/io.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/pci_ids.h> 16 #include <linux/platform_device.h> 17 18 #define GEN 0x00 19 #define GIO 0x04 20 #define GLV 0x08 21 22 struct sch_gpio { 23 struct gpio_chip chip; 24 spinlock_t lock; 25 unsigned short iobase; 26 unsigned short core_base; 27 unsigned short resume_base; 28 }; 29 30 static unsigned sch_gpio_offset(struct sch_gpio *sch, unsigned gpio, 31 unsigned reg) 32 { 33 unsigned base = 0; 34 35 if (gpio >= sch->resume_base) { 36 gpio -= sch->resume_base; 37 base += 0x20; 38 } 39 40 return base + reg + gpio / 8; 41 } 42 43 static unsigned sch_gpio_bit(struct sch_gpio *sch, unsigned gpio) 44 { 45 if (gpio >= sch->resume_base) 46 gpio -= sch->resume_base; 47 return gpio % 8; 48 } 49 50 static int sch_gpio_reg_get(struct sch_gpio *sch, unsigned gpio, unsigned reg) 51 { 52 unsigned short offset, bit; 53 u8 reg_val; 54 55 offset = sch_gpio_offset(sch, gpio, reg); 56 bit = sch_gpio_bit(sch, gpio); 57 58 reg_val = !!(inb(sch->iobase + offset) & BIT(bit)); 59 60 return reg_val; 61 } 62 63 static void sch_gpio_reg_set(struct sch_gpio *sch, unsigned gpio, unsigned reg, 64 int val) 65 { 66 unsigned short offset, bit; 67 u8 reg_val; 68 69 offset = sch_gpio_offset(sch, gpio, reg); 70 bit = sch_gpio_bit(sch, gpio); 71 72 reg_val = inb(sch->iobase + offset); 73 74 if (val) 75 outb(reg_val | BIT(bit), sch->iobase + offset); 76 else 77 outb((reg_val & ~BIT(bit)), sch->iobase + offset); 78 } 79 80 static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned gpio_num) 81 { 82 struct sch_gpio *sch = gpiochip_get_data(gc); 83 84 spin_lock(&sch->lock); 85 sch_gpio_reg_set(sch, gpio_num, GIO, 1); 86 spin_unlock(&sch->lock); 87 return 0; 88 } 89 90 static int sch_gpio_get(struct gpio_chip *gc, unsigned gpio_num) 91 { 92 struct sch_gpio *sch = gpiochip_get_data(gc); 93 return sch_gpio_reg_get(sch, gpio_num, GLV); 94 } 95 96 static void sch_gpio_set(struct gpio_chip *gc, unsigned gpio_num, int val) 97 { 98 struct sch_gpio *sch = gpiochip_get_data(gc); 99 100 spin_lock(&sch->lock); 101 sch_gpio_reg_set(sch, gpio_num, GLV, val); 102 spin_unlock(&sch->lock); 103 } 104 105 static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned gpio_num, 106 int val) 107 { 108 struct sch_gpio *sch = gpiochip_get_data(gc); 109 110 spin_lock(&sch->lock); 111 sch_gpio_reg_set(sch, gpio_num, GIO, 0); 112 spin_unlock(&sch->lock); 113 114 /* 115 * according to the datasheet, writing to the level register has no 116 * effect when GPIO is programmed as input. 117 * Actually the the level register is read-only when configured as input. 118 * Thus presetting the output level before switching to output is _NOT_ possible. 119 * Hence we set the level after configuring the GPIO as output. 120 * But we cannot prevent a short low pulse if direction is set to high 121 * and an external pull-up is connected. 122 */ 123 sch_gpio_set(gc, gpio_num, val); 124 return 0; 125 } 126 127 static int sch_gpio_get_direction(struct gpio_chip *gc, unsigned gpio_num) 128 { 129 struct sch_gpio *sch = gpiochip_get_data(gc); 130 131 return sch_gpio_reg_get(sch, gpio_num, GIO); 132 } 133 134 static const struct gpio_chip sch_gpio_chip = { 135 .label = "sch_gpio", 136 .owner = THIS_MODULE, 137 .direction_input = sch_gpio_direction_in, 138 .get = sch_gpio_get, 139 .direction_output = sch_gpio_direction_out, 140 .set = sch_gpio_set, 141 .get_direction = sch_gpio_get_direction, 142 }; 143 144 static int sch_gpio_probe(struct platform_device *pdev) 145 { 146 struct sch_gpio *sch; 147 struct resource *res; 148 149 sch = devm_kzalloc(&pdev->dev, sizeof(*sch), GFP_KERNEL); 150 if (!sch) 151 return -ENOMEM; 152 153 res = platform_get_resource(pdev, IORESOURCE_IO, 0); 154 if (!res) 155 return -EBUSY; 156 157 if (!devm_request_region(&pdev->dev, res->start, resource_size(res), 158 pdev->name)) 159 return -EBUSY; 160 161 spin_lock_init(&sch->lock); 162 sch->iobase = res->start; 163 sch->chip = sch_gpio_chip; 164 sch->chip.label = dev_name(&pdev->dev); 165 sch->chip.parent = &pdev->dev; 166 167 switch (pdev->id) { 168 case PCI_DEVICE_ID_INTEL_SCH_LPC: 169 sch->core_base = 0; 170 sch->resume_base = 10; 171 sch->chip.ngpio = 14; 172 173 /* 174 * GPIO[6:0] enabled by default 175 * GPIO7 is configured by the CMC as SLPIOVR 176 * Enable GPIO[9:8] core powered gpios explicitly 177 */ 178 sch_gpio_reg_set(sch, 8, GEN, 1); 179 sch_gpio_reg_set(sch, 9, GEN, 1); 180 /* 181 * SUS_GPIO[2:0] enabled by default 182 * Enable SUS_GPIO3 resume powered gpio explicitly 183 */ 184 sch_gpio_reg_set(sch, 13, GEN, 1); 185 break; 186 187 case PCI_DEVICE_ID_INTEL_ITC_LPC: 188 sch->core_base = 0; 189 sch->resume_base = 5; 190 sch->chip.ngpio = 14; 191 break; 192 193 case PCI_DEVICE_ID_INTEL_CENTERTON_ILB: 194 sch->core_base = 0; 195 sch->resume_base = 21; 196 sch->chip.ngpio = 30; 197 break; 198 199 case PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB: 200 sch->core_base = 0; 201 sch->resume_base = 2; 202 sch->chip.ngpio = 8; 203 break; 204 205 default: 206 return -ENODEV; 207 } 208 209 platform_set_drvdata(pdev, sch); 210 211 return devm_gpiochip_add_data(&pdev->dev, &sch->chip, sch); 212 } 213 214 static struct platform_driver sch_gpio_driver = { 215 .driver = { 216 .name = "sch_gpio", 217 }, 218 .probe = sch_gpio_probe, 219 }; 220 221 module_platform_driver(sch_gpio_driver); 222 223 MODULE_AUTHOR("Denis Turischev <denis@compulab.co.il>"); 224 MODULE_DESCRIPTION("GPIO interface for Intel Poulsbo SCH"); 225 MODULE_LICENSE("GPL v2"); 226 MODULE_ALIAS("platform:sch_gpio"); 227