1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/arch/arm/mach-sa1100/gpio.c 4 * 5 * Generic SA-1100 GPIO handling 6 */ 7 #include <linux/gpio/driver.h> 8 #include <linux/init.h> 9 #include <linux/module.h> 10 #include <linux/io.h> 11 #include <linux/syscore_ops.h> 12 #include <soc/sa1100/pwer.h> 13 #include <mach/hardware.h> 14 #include <mach/irqs.h> 15 16 struct sa1100_gpio_chip { 17 struct gpio_chip chip; 18 void __iomem *membase; 19 int irqbase; 20 u32 irqmask; 21 u32 irqrising; 22 u32 irqfalling; 23 u32 irqwake; 24 }; 25 26 #define sa1100_gpio_chip(x) container_of(x, struct sa1100_gpio_chip, chip) 27 28 enum { 29 R_GPLR = 0x00, 30 R_GPDR = 0x04, 31 R_GPSR = 0x08, 32 R_GPCR = 0x0c, 33 R_GRER = 0x10, 34 R_GFER = 0x14, 35 R_GEDR = 0x18, 36 R_GAFR = 0x1c, 37 }; 38 39 static int sa1100_gpio_get(struct gpio_chip *chip, unsigned offset) 40 { 41 return readl_relaxed(sa1100_gpio_chip(chip)->membase + R_GPLR) & 42 BIT(offset); 43 } 44 45 static void sa1100_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 46 { 47 int reg = value ? R_GPSR : R_GPCR; 48 49 writel_relaxed(BIT(offset), sa1100_gpio_chip(chip)->membase + reg); 50 } 51 52 static int sa1100_get_direction(struct gpio_chip *chip, unsigned offset) 53 { 54 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; 55 56 if (readl_relaxed(gpdr) & BIT(offset)) 57 return GPIO_LINE_DIRECTION_OUT; 58 59 return GPIO_LINE_DIRECTION_IN; 60 } 61 62 static int sa1100_direction_input(struct gpio_chip *chip, unsigned offset) 63 { 64 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; 65 unsigned long flags; 66 67 local_irq_save(flags); 68 writel_relaxed(readl_relaxed(gpdr) & ~BIT(offset), gpdr); 69 local_irq_restore(flags); 70 71 return 0; 72 } 73 74 static int sa1100_direction_output(struct gpio_chip *chip, unsigned offset, int value) 75 { 76 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; 77 unsigned long flags; 78 79 local_irq_save(flags); 80 sa1100_gpio_set(chip, offset, value); 81 writel_relaxed(readl_relaxed(gpdr) | BIT(offset), gpdr); 82 local_irq_restore(flags); 83 84 return 0; 85 } 86 87 static int sa1100_to_irq(struct gpio_chip *chip, unsigned offset) 88 { 89 return sa1100_gpio_chip(chip)->irqbase + offset; 90 } 91 92 static struct sa1100_gpio_chip sa1100_gpio_chip = { 93 .chip = { 94 .label = "gpio", 95 .get_direction = sa1100_get_direction, 96 .direction_input = sa1100_direction_input, 97 .direction_output = sa1100_direction_output, 98 .set = sa1100_gpio_set, 99 .get = sa1100_gpio_get, 100 .to_irq = sa1100_to_irq, 101 .base = 0, 102 .ngpio = GPIO_MAX + 1, 103 }, 104 .membase = (void *)&GPLR, 105 .irqbase = IRQ_GPIO0, 106 }; 107 108 /* 109 * SA1100 GPIO edge detection for IRQs: 110 * IRQs are generated on Falling-Edge, Rising-Edge, or both. 111 * Use this instead of directly setting GRER/GFER. 112 */ 113 static void sa1100_update_edge_regs(struct sa1100_gpio_chip *sgc) 114 { 115 void *base = sgc->membase; 116 u32 grer, gfer; 117 118 grer = sgc->irqrising & sgc->irqmask; 119 gfer = sgc->irqfalling & sgc->irqmask; 120 121 writel_relaxed(grer, base + R_GRER); 122 writel_relaxed(gfer, base + R_GFER); 123 } 124 125 static int sa1100_gpio_type(struct irq_data *d, unsigned int type) 126 { 127 struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d); 128 unsigned int mask = BIT(d->hwirq); 129 130 if (type == IRQ_TYPE_PROBE) { 131 if ((sgc->irqrising | sgc->irqfalling) & mask) 132 return 0; 133 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 134 } 135 136 if (type & IRQ_TYPE_EDGE_RISING) 137 sgc->irqrising |= mask; 138 else 139 sgc->irqrising &= ~mask; 140 if (type & IRQ_TYPE_EDGE_FALLING) 141 sgc->irqfalling |= mask; 142 else 143 sgc->irqfalling &= ~mask; 144 145 sa1100_update_edge_regs(sgc); 146 147 return 0; 148 } 149 150 /* 151 * GPIO IRQs must be acknowledged. 152 */ 153 static void sa1100_gpio_ack(struct irq_data *d) 154 { 155 struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d); 156 157 writel_relaxed(BIT(d->hwirq), sgc->membase + R_GEDR); 158 } 159 160 static void sa1100_gpio_mask(struct irq_data *d) 161 { 162 struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d); 163 unsigned int mask = BIT(d->hwirq); 164 165 sgc->irqmask &= ~mask; 166 167 sa1100_update_edge_regs(sgc); 168 } 169 170 static void sa1100_gpio_unmask(struct irq_data *d) 171 { 172 struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d); 173 unsigned int mask = BIT(d->hwirq); 174 175 sgc->irqmask |= mask; 176 177 sa1100_update_edge_regs(sgc); 178 } 179 180 static int sa1100_gpio_wake(struct irq_data *d, unsigned int on) 181 { 182 struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d); 183 int ret = sa11x0_gpio_set_wake(d->hwirq, on); 184 if (!ret) { 185 if (on) 186 sgc->irqwake |= BIT(d->hwirq); 187 else 188 sgc->irqwake &= ~BIT(d->hwirq); 189 } 190 return ret; 191 } 192 193 /* 194 * This is for GPIO IRQs 195 */ 196 static struct irq_chip sa1100_gpio_irq_chip = { 197 .name = "GPIO", 198 .irq_ack = sa1100_gpio_ack, 199 .irq_mask = sa1100_gpio_mask, 200 .irq_unmask = sa1100_gpio_unmask, 201 .irq_set_type = sa1100_gpio_type, 202 .irq_set_wake = sa1100_gpio_wake, 203 }; 204 205 static int sa1100_gpio_irqdomain_map(struct irq_domain *d, 206 unsigned int irq, irq_hw_number_t hwirq) 207 { 208 struct sa1100_gpio_chip *sgc = d->host_data; 209 210 irq_set_chip_data(irq, sgc); 211 irq_set_chip_and_handler(irq, &sa1100_gpio_irq_chip, handle_edge_irq); 212 irq_set_probe(irq); 213 214 return 0; 215 } 216 217 static const struct irq_domain_ops sa1100_gpio_irqdomain_ops = { 218 .map = sa1100_gpio_irqdomain_map, 219 .xlate = irq_domain_xlate_onetwocell, 220 }; 221 222 static struct irq_domain *sa1100_gpio_irqdomain; 223 224 /* 225 * IRQ 0-11 (GPIO) handler. We enter here with the 226 * irq_controller_lock held, and IRQs disabled. Decode the IRQ 227 * and call the handler. 228 */ 229 static void sa1100_gpio_handler(struct irq_desc *desc) 230 { 231 struct sa1100_gpio_chip *sgc = irq_desc_get_handler_data(desc); 232 unsigned int irq, mask; 233 void __iomem *gedr = sgc->membase + R_GEDR; 234 235 mask = readl_relaxed(gedr); 236 do { 237 /* 238 * clear down all currently active IRQ sources. 239 * We will be processing them all. 240 */ 241 writel_relaxed(mask, gedr); 242 243 irq = sgc->irqbase; 244 do { 245 if (mask & 1) 246 generic_handle_irq(irq); 247 mask >>= 1; 248 irq++; 249 } while (mask); 250 251 mask = readl_relaxed(gedr); 252 } while (mask); 253 } 254 255 static int sa1100_gpio_suspend(void) 256 { 257 struct sa1100_gpio_chip *sgc = &sa1100_gpio_chip; 258 259 /* 260 * Set the appropriate edges for wakeup. 261 */ 262 writel_relaxed(sgc->irqwake & sgc->irqrising, sgc->membase + R_GRER); 263 writel_relaxed(sgc->irqwake & sgc->irqfalling, sgc->membase + R_GFER); 264 265 /* 266 * Clear any pending GPIO interrupts. 267 */ 268 writel_relaxed(readl_relaxed(sgc->membase + R_GEDR), 269 sgc->membase + R_GEDR); 270 271 return 0; 272 } 273 274 static void sa1100_gpio_resume(void) 275 { 276 sa1100_update_edge_regs(&sa1100_gpio_chip); 277 } 278 279 static struct syscore_ops sa1100_gpio_syscore_ops = { 280 .suspend = sa1100_gpio_suspend, 281 .resume = sa1100_gpio_resume, 282 }; 283 284 static int __init sa1100_gpio_init_devicefs(void) 285 { 286 register_syscore_ops(&sa1100_gpio_syscore_ops); 287 return 0; 288 } 289 290 device_initcall(sa1100_gpio_init_devicefs); 291 292 static const int sa1100_gpio_irqs[] __initconst = { 293 /* Install handlers for GPIO 0-10 edge detect interrupts */ 294 IRQ_GPIO0_SC, 295 IRQ_GPIO1_SC, 296 IRQ_GPIO2_SC, 297 IRQ_GPIO3_SC, 298 IRQ_GPIO4_SC, 299 IRQ_GPIO5_SC, 300 IRQ_GPIO6_SC, 301 IRQ_GPIO7_SC, 302 IRQ_GPIO8_SC, 303 IRQ_GPIO9_SC, 304 IRQ_GPIO10_SC, 305 /* Install handler for GPIO 11-27 edge detect interrupts */ 306 IRQ_GPIO11_27, 307 }; 308 309 void __init sa1100_init_gpio(void) 310 { 311 struct sa1100_gpio_chip *sgc = &sa1100_gpio_chip; 312 int i; 313 314 /* clear all GPIO edge detects */ 315 writel_relaxed(0, sgc->membase + R_GFER); 316 writel_relaxed(0, sgc->membase + R_GRER); 317 writel_relaxed(-1, sgc->membase + R_GEDR); 318 319 gpiochip_add_data(&sa1100_gpio_chip.chip, NULL); 320 321 sa1100_gpio_irqdomain = irq_domain_add_simple(NULL, 322 28, IRQ_GPIO0, 323 &sa1100_gpio_irqdomain_ops, sgc); 324 325 for (i = 0; i < ARRAY_SIZE(sa1100_gpio_irqs); i++) 326 irq_set_chained_handler_and_data(sa1100_gpio_irqs[i], 327 sa1100_gpio_handler, sgc); 328 } 329